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From: Umang Chheda <umang.chheda@oss.qualcomm.com>
To: Ruidong Tian <tianruidong@linux.alibaba.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Lorenzo Pieralisi <lpieralisi@kernel.org>,
	Hanjun Guo <guohanjun@huawei.com>,
	Sudeep Holla <sudeep.holla@kernel.org>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>, Tony Luck <tony.luck@intel.com>,
	Borislav Petkov <bp@alien8.de>, Thomas Gleixner <tglx@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Robin Murphy <robin.murphy@arm.com>
Cc: linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org,
	zhuo.song@linux.alibaba.com, oliver.yang@linux.alibaba.com
Subject: Re: [PATCH v7 02/16] arm64: ras: Add probe/remove for arm64_ras driver
Date: Fri, 23 Oct 2026 15:29:35 +0530	[thread overview]
Message-ID: <01b1b1bd-2848-482e-af8b-8fab037c7a04@oss.qualcomm.com> (raw)
In-Reply-To: <20260602071540.3711528-3-tianruidong@linux.alibaba.com>

Hello Ruidong,

On 6/2/2026 12:45 PM, Ruidong Tian wrote:
> Introduce the back-end platform driver that binds to the devices
> created by the AEST front-end. Driver input is taken exclusively from
> fwnode properties, so the same probe path serves any future front-end
> (DT, hand-rolled) without conditional code.
> 
> The probe builds two layers of state:
> 
>   - struct ras_node:   one AEST error source
>   - struct ras_record: one error record inside a node
> 
> This split mirrors the hardware: a node owns the shared MMIO/ERRGSR
> window and policy, while records are the unit at which errors are
> reported, masked and polled. Later patches plug interrupts, decoding,
> storm mitigation and userspace ABI onto these two objects without
> touching the front-end.
> 
> Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
> Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com>
> ---
[...]

> +# SPDX-License-Identifier: GPL-2.0-only
> +
> +obj-$(CONFIG_ARM64_RAS_DRIVER) 	+= arm64_ras.o
> +
> +arm64_ras-y		:= ras-core.o
> diff --git a/drivers/ras/arm64/ras-core.c b/drivers/ras/arm64/ras-core.c
> new file mode 100644
> index 000000000000..b5448f4a841f
> --- /dev/null
> +++ b/drivers/ras/arm64/ras-core.c
> @@ -0,0 +1,266 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * ARM Error Source Table Support
> + *
> + * Copyright (c) 2025, Alibaba Group.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/ras.h>
> +
> +#include "ras.h"
> +
> +#undef pr_fmt
> +#define pr_fmt(fmt) "arm64_ras: " fmt
> +
> +static const char *const ras_node_name[] = {
> +	[ACPI_AEST_PROCESSOR_ERROR_NODE] = "processor",
> +	[ACPI_AEST_MEMORY_ERROR_NODE] = "memory",
> +	[ACPI_AEST_SMMU_ERROR_NODE] = "smmu",
> +	[ACPI_AEST_VENDOR_ERROR_NODE] = "vendor",
> +	[ACPI_AEST_GIC_ERROR_NODE] = "gic",
> +	[ACPI_AEST_PCIE_ERROR_NODE] = "pcie",
> +	[ACPI_AEST_PROXY_ERROR_NODE] = "proxy",
> +};

Now that the ARM RAS core framework is shared by both ACPI and DT
platforms, should we consider dropping the "ACPI_AEST" naming in the
common code and replacing it with a more generic prefix maybe something
like "ARM_RAS" ?

[...]
> +
> +const struct ras_group ras_group_config[] = {
> +	[ACPI_AEST_NODE_GROUP_FORMAT_4K] = {
> +		.errgsr_num = ERXGROUP_4K_ERRGSR_NUM,
> +		.size = ERXGROUP_4K_SIZE,
> +		.errgsr_offset = ERXGROUP_4K_OFFSET,
> +	},
> +	[ACPI_AEST_NODE_GROUP_FORMAT_16K] = {
> +		.errgsr_num = ERXGROUP_16K_ERRGSR_NUM,
> +		.size = ERXGROUP_16K_SIZE,
> +		.errgsr_offset = ERXGROUP_16K_OFFSET,
> +	},
> +	[ACPI_AEST_NODE_GROUP_FORMAT_64K] = {
> +		.errgsr_num = ERXGROUP_64K_ERRGSR_NUM,
> +		.size = ERXGROUP_64K_SIZE,
> +		.errgsr_offset = ERXGROUP_64K_OFFSET,
> +	},
> +};
> +
Thanks,
Umang

  reply	other threads:[~2026-10-23  9:59 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-02  7:15 [PATCH v7 00/16] Support Armv8 RAS Extensions for Kernel-first error handling Ruidong Tian
2026-06-02  7:15 ` [PATCH v7 01/16] ACPI/AEST: Register arm64_ras platform devices from AEST v2 Ruidong Tian
2026-06-02  7:15 ` [PATCH v7 02/16] arm64: ras: Add probe/remove for arm64_ras driver Ruidong Tian
2026-10-23  9:59   ` Umang Chheda [this message]
2026-10-23 12:09     ` Robin Murphy
2026-06-02  7:15 ` [PATCH v7 03/16] arm64: ras: Unify the read/write interface for system and MMIO registers Ruidong Tian
2026-06-02  7:15 ` [PATCH v7 04/16] arm64: ras: Support RAS Common Fault Injection Model Extension Ruidong Tian
2026-06-02  7:15 ` [PATCH v7 05/16] arm64: ras: Plumb AEST interrupts as platform IRQ resources Ruidong Tian
2026-06-02  7:15 ` [PATCH v7 06/16] arm64: ras: Enable error reporting Ruidong Tian
2026-06-02  7:15 ` [PATCH v7 07/16] arm64: ras: Add error record processing and interrupt handling Ruidong Tian
2026-06-02  7:15 ` [PATCH v7 08/16] arm64: ras: Handle memory failure for uncorrectable errors Ruidong Tian
2026-06-02  7:15 ` [PATCH v7 09/16] arm64: ras: Probe RAS architecture version Ruidong Tian
2026-06-02  7:15 ` [PATCH v7 10/16] arm64: ras: Support CE threshold of error record Ruidong Tian
2026-06-02  7:15 ` [PATCH v7 11/16] arm64: ras: Add RAS decode notifier chain Ruidong Tian
2026-06-02  7:15 ` [PATCH v7 12/16] arm64: ras: Expose config abi through debugfs Ruidong Tian
2026-06-02  7:15 ` [PATCH v7 13/16] arm64: ras: Introduce ras inject interface Ruidong Tian
2026-06-02  7:15 ` [PATCH v7 14/16] arm64: ras: support vendor node CMN700 Ruidong Tian
2026-06-02  7:15 ` [PATCH v7 15/16] arm64: ras: Introduce ras error storm mitigation Ruidong Tian
2026-06-02  7:15 ` [PATCH v7 16/16] trace, ras: add ARM RAS extension trace event Ruidong Tian
2026-07-08  2:41 ` [PATCH v7 00/16] Support Armv8 RAS Extensions for Kernel-first error handling Borislav Petkov
2026-07-08 17:22   ` Catalin Marinas
2026-07-20  8:26     ` Umang Chheda

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