Re: [PATCH] spi: realtek-rtl: add support for second CS

[Jonas Jelonek <jonas@jonasjelonek.de>]

Hi,

On 19.09.26 18:46, Mark Brown wrote:
> On Fri, Sep 18, 2026 at 09:47:40PM +0000, Jonas Jelonek wrote:
>> The initial driver assumed that the controller's second chip select was
>> vestigial because none of the devices examined at the time used it. This
>> does not hold for all hardware: there are devices with a peripheral
>> connected to CS1. Since the controller only advertises one chip select
>> and keeps CS1 permanently deasserted, those peripherals cannot be used.
>> +	/* CSB0/CSB1 are active low: deassert both. */
>>  	value = __raw_readl(REG(RTL_SPI_SFCSR));
>> -	/* Permanently disable CS1, since it's never used */
>> -	value |= RTL_SPI_SFCSR_CSB1;
>> -	/* Select CS0 for use */
>> -	value &= RTL_SPI_SFCSR_CS;
>> +	value |= RTL_SPI_SFCSR_CSB0 | RTL_SPI_SFCSR_CSB1;
>>  	__raw_writel(value, REG(RTL_SPI_SFCSR));
> The original code would ensure that all bits in the register are
> initialised to known values, the new code sets some bits and leaves the
> rest with whatever value they happened to have previously.  Probably we
> still want the initialisation of the other bits.

Yes, you're right. Thanks for pointing that out. Indeed, bits setting the
data length and the I/O mode sit in this register too. Zero is required to
have one byte data length and single I/O. I'll fix this in a v2.

Best,
Jonas