From: Mark Brown <broonie@kernel.org>
To: Jonas Jelonek <jonas@jonasjelonek.de>
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] spi: realtek-rtl: add support for second CS
Date: Sat, 19 Sep 2026 18:46:00 +0200 [thread overview]
Message-ID: <aq68SNTdUKzIm0K5@sirena.org.uk> (raw)
In-Reply-To: <20260918214740.3963349-1-jonas@jonasjelonek.de>
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On Fri, Sep 18, 2026 at 09:47:40PM +0000, Jonas Jelonek wrote:
> The initial driver assumed that the controller's second chip select was
> vestigial because none of the devices examined at the time used it. This
> does not hold for all hardware: there are devices with a peripheral
> connected to CS1. Since the controller only advertises one chip select
> and keeps CS1 permanently deasserted, those peripherals cannot be used.
> + /* CSB0/CSB1 are active low: deassert both. */
> value = __raw_readl(REG(RTL_SPI_SFCSR));
> - /* Permanently disable CS1, since it's never used */
> - value |= RTL_SPI_SFCSR_CSB1;
> - /* Select CS0 for use */
> - value &= RTL_SPI_SFCSR_CS;
> + value |= RTL_SPI_SFCSR_CSB0 | RTL_SPI_SFCSR_CSB1;
> __raw_writel(value, REG(RTL_SPI_SFCSR));
The original code would ensure that all bits in the register are
initialised to known values, the new code sets some bits and leaves the
rest with whatever value they happened to have previously. Probably we
still want the initialisation of the other bits.
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next prev parent reply other threads:[~2026-09-19 16:46 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-18 21:47 Jonas Jelonek
2026-09-19 16:46 ` Mark Brown [this message]
2026-09-19 17:02 ` Jonas Jelonek
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