Re: [PATCH v10 2/6] riscv_cbqri: resctrl: Add cache allocation via capacity block mask

["Zeng Heng" <zengheng@picoheart.com>]

Hi Drew,


在 11/5/26 上午12:35, Drew Fustini 写道:

...

> +/*
> + * Fill the rdt_resource fields for one picked rid. An rid with no picked
> + * controller is left untouched so it stays out of resctrl_arch_get_resource().
> + */
> +static void cbqri_resctrl_control_init(struct cbqri_resctrl_res *cbqri_res)
> +{
> +	struct rdt_resource *res = &cbqri_res->resctrl_res;
> +	struct cbqri_controller *ctrl;
> +
> +	if (!cbqri_res->nr_ctrls)
> +		return;
> +	ctrl = cbqri_res->ctrls[0];
> +
> +	switch (res->rid) {
> +	case RDT_RESOURCE_L2:
> +	case RDT_RESOURCE_L3:
> +		res->name = (res->rid == RDT_RESOURCE_L2) ? "L2" : "L3";
> +		res->schema_fmt = RESCTRL_SCHEMA_BITMAP;
> +		res->ctrl_scope = (res->rid == RDT_RESOURCE_L2) ?
> +				    RESCTRL_L2_CACHE : RESCTRL_L3_CACHE;
> +		res->cache.cbm_len = ctrl->cc.ncblks;
> +		res->cache.shareable_bits = 0;
> +		res->cache.min_cbm_bits = 1;
> +		res->cache.arch_has_sparse_bitmasks = false;

Currently, the driver sets arch_has_sparse_bitmasks to false, causing
resctrl to require a contiguous bits in cache allocation masks. For
example, L3:0=3 is accepted, whereas L3:0=11 is rejected because its
set bits are non-contiguous.

The default should allow both contiguous and non-contiguous masks,
provided they satisfy the other mask validity checks. A contiguity
restriction should only be imposed when a specific hardware
implementation can't support sparse masks explicitly.

So I propose enabling sparse cache allocation bitmasks by default.
Thanks.

> +		res->cdp_capable = ctrl->cc.supports_alloc_at_code;
> +		res->alloc_capable = ctrl->alloc_capable;
> +		INIT_LIST_HEAD(&res->ctrl_domains);
> +		INIT_LIST_HEAD(&res->mon_domains);
> +		break;
> +	default:
> +		break;
> +	}
> +}

Apart from this,

Reviewed-by: Zeng Heng <zengheng@picoheart.com>


Best regards,
Zeng Heng