* [PATCH 0/3] add CPUCL1/2 clock support for exynosauto v920 SoC [not found] <CGME20250428084728epcas2p486ddfccc41bfba9830bde544b6c292e3@epcas2p4.samsung.com> @ 2025-04-28 8:47 ` Shin Son [not found] ` <CGME20250428084728epcas2p34ffa0051a16c10ff1c358a98cc2c2fa4@epcas2p3.samsung.com> ` (2 more replies) 0 siblings, 3 replies; 8+ messages in thread From: Shin Son @ 2025-04-28 8:47 UTC (permalink / raw) To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley, Sunyeal Hong Cc: Shin Son, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel This patchset adds the CMU_CPUCL1 and CMU_CPUCL2 block to support exynosauto v920 SoC. Shin Son (3): dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions clk: samsung: exynosautov920: add cpucl1/2 clock support arm64: dts: exynosautov920: add cpucl1/2 clock DT nodes .../clock/samsung,exynosautov920-clock.yaml | 45 ++++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 26 +++ drivers/clk/samsung/clk-exynosautov920.c | 208 +++++++++++++++++- .../clock/samsung,exynosautov920.h | 32 +++ 4 files changed, 310 insertions(+), 1 deletion(-) -- 2.49.0 ^ permalink raw reply [flat|nested] 8+ messages in thread
[parent not found: <CGME20250428084728epcas2p34ffa0051a16c10ff1c358a98cc2c2fa4@epcas2p3.samsung.com>]
* [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions [not found] ` <CGME20250428084728epcas2p34ffa0051a16c10ff1c358a98cc2c2fa4@epcas2p3.samsung.com> @ 2025-04-28 8:47 ` Shin Son 2025-04-28 9:13 ` Krzysztof Kozlowski 0 siblings, 1 reply; 8+ messages in thread From: Shin Son @ 2025-04-28 8:47 UTC (permalink / raw) To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley, Sunyeal Hong Cc: Shin Son, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Add cpucl1 and cpucl2 clock definitions. CPUCL1/2 refer to CPU Cluster 1 and CPU Cluster 2, which provide clock support for the CPUs on Exynosauto V920 SoC. Signed-off-by: Shin Son <shin.son@samsung.com> --- .../clock/samsung,exynosautov920-clock.yaml | 45 +++++++++++++++++++ .../clock/samsung,exynosautov920.h | 32 +++++++++++++ 2 files changed, 77 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml index d12b17c177df..dbeae0cb0cb9 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml @@ -34,6 +34,8 @@ properties: enum: - samsung,exynosautov920-cmu-top - samsung,exynosautov920-cmu-cpucl0 + - samsung,exynosautov920-cmu-cpucl1 + - samsung,exynosautov920-cmu-cpucl2 - samsung,exynosautov920-cmu-peric0 - samsung,exynosautov920-cmu-peric1 - samsung,exynosautov920-cmu-misc @@ -94,6 +96,49 @@ allOf: - const: cluster - const: dbg + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-cmu-cpucl1 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL1 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL1 CLUSTER clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-cmu-cpucl2 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL2 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + + - if: properties: compatible: diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h index c57a1d749700..5e6896e9627f 100644 --- a/include/dt-bindings/clock/samsung,exynosautov920.h +++ b/include/dt-bindings/clock/samsung,exynosautov920.h @@ -181,6 +181,38 @@ #define CLK_DOUT_CPUCL0_DBG_PCLKDBG 14 #define CLK_DOUT_CPUCL0_NOCP 15 +/* CMU_CPUCL1 */ +#define CLK_FOUT_CPUCL1_PLL 1 + +#define CLK_MOUT_PLL_CPUCL1 2 +#define CLK_MOUT_CPUCL1_CLUSTER_USER 3 +#define CLK_MOUT_CPUCL1_SWITCH_USER 4 +#define CLK_MOUT_CPUCL1_CLUSTER 5 +#define CLK_MOUT_CPUCL1_CORE 6 + +#define CLK_DOUT_CLUSTER1_ACLK 7 +#define CLK_DOUT_CLUSTER1_ATCLK 8 +#define CLK_DOUT_CLUSTER1_MPCLK 9 +#define CLK_DOUT_CLUSTER1_PCLK 10 +#define CLK_DOUT_CLUSTER1_PERIPHCLK 11 +#define CLK_DOUT_CPUCL1_NOCP 12 + +/* CMU_CPUCL2 */ +#define CLK_FOUT_CPUCL2_PLL 1 + +#define CLK_MOUT_PLL_CPUCL2 2 +#define CLK_MOUT_CPUCL2_CLUSTER_USER 3 +#define CLK_MOUT_CPUCL2_SWITCH_USER 4 +#define CLK_MOUT_CPUCL2_CLUSTER 5 +#define CLK_MOUT_CPUCL2_CORE 6 + +#define CLK_DOUT_CLUSTER2_ACLK 7 +#define CLK_DOUT_CLUSTER2_ATCLK 8 +#define CLK_DOUT_CLUSTER2_MPCLK 9 +#define CLK_DOUT_CLUSTER2_PCLK 10 +#define CLK_DOUT_CLUSTER2_PERIPHCLK 11 +#define CLK_DOUT_CPUCL2_NOCP 12 + /* CMU_PERIC0 */ #define CLK_MOUT_PERIC0_IP_USER 1 #define CLK_MOUT_PERIC0_NOC_USER 2 -- 2.49.0 ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions 2025-04-28 8:47 ` [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions Shin Son @ 2025-04-28 9:13 ` Krzysztof Kozlowski 2025-04-28 10:41 ` 손신 0 siblings, 1 reply; 8+ messages in thread From: Krzysztof Kozlowski @ 2025-04-28 9:13 UTC (permalink / raw) To: Shin Son, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley, Sunyeal Hong Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 28/04/2025 10:47, Shin Son wrote: > Add cpucl1 and cpucl2 clock definitions. > > CPUCL1/2 refer to CPU Cluster 1 and CPU Cluster 2, > which provide clock support for the CPUs on Exynosauto V920 SoC. You should have sent all cpcl0-2 together, so we see complete picture. > > Signed-off-by: Shin Son <shin.son@samsung.com> > --- > .../clock/samsung,exynosautov920-clock.yaml | 45 +++++++++++++++++++ > .../clock/samsung,exynosautov920.h | 32 +++++++++++++ > 2 files changed, 77 insertions(+) > ... > + then: > + properties: > + clocks: > + items: > + - description: External reference clock (38.4 MHz) > + - description: CMU_CPUCL2 SWITCH clock (from CMU_TOP) > + - description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP) > + > + clock-names: > + items: > + - const: oscclk > + - const: switch > + - const: cluster > + > + Just one blank line. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions 2025-04-28 9:13 ` Krzysztof Kozlowski @ 2025-04-28 10:41 ` 손신 0 siblings, 0 replies; 8+ messages in thread From: 손신 @ 2025-04-28 10:41 UTC (permalink / raw) To: 'Krzysztof Kozlowski', 'Sylwester Nawrocki', 'Chanwoo Choi', 'Alim Akhtar', 'Michael Turquette', 'Stephen Boyd', 'Rob Herring', 'Conor Dooley', 'Sunyeal Hong' Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Hello Krzysztof Kozlowski, > -----Original Message----- > From: Krzysztof Kozlowski [mailto:krzk@kernel.org] > Sent: Monday, April 28, 2025 6:13 PM > To: Shin Son <shin.son@samsung.com>; Sylwester Nawrocki > <s.nawrocki@samsung.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim > Akhtar <alim.akhtar@samsung.com>; Michael Turquette > <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob Herring > <robh@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Sunyeal Hong > <sunyeal.hong@samsung.com> > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Subject: Re: [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl1/2 > clock definitions > > On 28/04/2025 10:47, Shin Son wrote: > > Add cpucl1 and cpucl2 clock definitions. > > > > CPUCL1/2 refer to CPU Cluster 1 and CPU Cluster 2, which provide clock > > support for the CPUs on Exynosauto V920 SoC. > > You should have sent all cpcl0-2 together, so we see complete picture. > > > > > Signed-off-by: Shin Son <shin.son@samsung.com> > > --- > > .../clock/samsung,exynosautov920-clock.yaml | 45 +++++++++++++++++++ > > .../clock/samsung,exynosautov920.h | 32 +++++++++++++ > > 2 files changed, 77 insertions(+) > > > > > ... > > > + then: > > + properties: > > + clocks: > > + items: > > + - description: External reference clock (38.4 MHz) > > + - description: CMU_CPUCL2 SWITCH clock (from CMU_TOP) > > + - description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP) > > + > > + clock-names: > > + items: > > + - const: oscclk > > + - const: switch > > + - const: cluster > > + > > + > Just one blank line. > > Best regards, > Krzysztof Thanks for the feedback. I will group related patches together next time for a more complete view. I will also remove the extra blank line and resend the patch. Best regards, Shin Son ^ permalink raw reply [flat|nested] 8+ messages in thread
[parent not found: <CGME20250428084728epcas2p17a0253f04de15c23ab6362113a0d47bb@epcas2p1.samsung.com>]
* [PATCH 2/3] clk: samsung: exynosautov920: add cpucl1/2 clock support [not found] ` <CGME20250428084728epcas2p17a0253f04de15c23ab6362113a0d47bb@epcas2p1.samsung.com> @ 2025-04-28 8:47 ` Shin Son 2025-04-28 9:14 ` Krzysztof Kozlowski 0 siblings, 1 reply; 8+ messages in thread From: Shin Son @ 2025-04-28 8:47 UTC (permalink / raw) To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley, Sunyeal Hong Cc: Shin Son, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Register compatible and cmu_info data to support clock CPUCL1/2 (CPU Cluster 1 and CPU Cluster 2), these provide clock for CPUCL1/2_SWTICH/CLUSTER. These clocks are required early during boot for the CPUs, so they are declared using CLK_OF_DECLARE instead of being registered through a platform driver. Signed-off-by: Shin Son <shin.son@samsung.com> --- drivers/clk/samsung/clk-exynosautov920.c | 208 ++++++++++++++++++++++- 1 file changed, 207 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c index 8021e0912e50..f8168eed4a66 100644 --- a/drivers/clk/samsung/clk-exynosautov920.c +++ b/drivers/clk/samsung/clk-exynosautov920.c @@ -18,7 +18,9 @@ /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1) -#define CLKS_NR_CPUCL0 (CLK_DOUT_CLUSTER0_PERIPHCLK + 1) +#define CLKS_NR_CPUCL0 (CLK_DOUT_CPUCL0_NOCP + 1) +#define CLKS_NR_CPUCL1 (CLK_DOUT_CPUCL1_NOCP + 1) +#define CLKS_NR_CPUCL2 (CLK_DOUT_CPUCL2_NOCP + 1) #define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1) #define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1) #define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1) @@ -1135,6 +1137,210 @@ static void __init exynosautov920_cmu_cpucl0_init(struct device_node *np) CLK_OF_DECLARE(exynosautov920_cmu_cpucl0, "samsung,exynosautov920-cmu-cpucl0", exynosautov920_cmu_cpucl0_init); +/* ---- CMU_CPUCL1 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_CPUCL1 (0x1ED00000) */ +#define PLL_LOCKTIME_PLL_CPUCL1 0x0000 +#define PLL_CON0_PLL_CPUCL1 0x0100 +#define PLL_CON1_PLL_CPUCL1 0x0104 +#define PLL_CON3_PLL_CPUCL1 0x010c +#define PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER 0x0600 +#define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610 + +#define CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER 0x1000 +#define CLK_CON_MUX_MUX_CLK_CPUCL1_CORE 0x1004 + +#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800 +#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1804 +#define CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK 0x1808 +#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK 0x180c +#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810 +#define CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP 0x181c + +static const unsigned long cpucl1_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_CPUCL1, + PLL_CON0_PLL_CPUCL1, + PLL_CON1_PLL_CPUCL1, + PLL_CON3_PLL_CPUCL1, + PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER, + PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, + CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER, + CLK_CON_MUX_MUX_CLK_CPUCL1_CORE, + CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, + CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, + CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK, + CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK, + CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, + CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP, +}; + +/* List of parent clocks for Muxes in CMU_CPUCL1 */ +PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" }; +PNAME(mout_cpucl1_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl1_cluster" }; +PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl1_switch" }; +PNAME(mout_cpucl1_cluster_p) = { "oscclk", "mout_cpucl1_cluster_user", + "mout_cpucl1_switch_user"}; +PNAME(mout_cpucl1_core_p) = { "oscclk", "mout_pll_cpucl1", + "mout_cpucl1_switch_user"}; + +static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = { + /* CMU_CPUCL1_PURECLKCOMP */ + PLL(pll_531x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk", + PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, cpu_pll_rates), +}; + +static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = { + MUX(CLK_MOUT_PLL_CPUCL1, "mout_pll_cpucl1", mout_pll_cpucl1_p, + PLL_CON0_PLL_CPUCL1, 4, 1), + MUX(CLK_MOUT_CPUCL1_CLUSTER_USER, "mout_cpucl1_cluster_user", mout_cpucl1_cluster_user_p, + PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER, 4, 1), + MUX(CLK_MOUT_CPUCL1_SWITCH_USER, "mout_cpucl1_switch_user", mout_cpucl1_switch_user_p, + PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 4, 1), + MUX(CLK_MOUT_CPUCL1_CLUSTER, "mout_cpucl1_cluster", mout_cpucl1_cluster_p, + CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER, 0, 2), + MUX(CLK_MOUT_CPUCL1_CORE, "mout_cpucl1_core", mout_cpucl1_core_p, + CLK_CON_MUX_MUX_CLK_CPUCL1_CORE, 0, 2), +}; + +static const struct samsung_div_clock cpucl1_div_clks[] __initconst = { + DIV(CLK_DOUT_CLUSTER1_ACLK, "dout_cluster1_aclk", + "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4), + DIV(CLK_DOUT_CLUSTER1_ATCLK, "dout_cluster1_atclk", + "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4), + DIV(CLK_DOUT_CLUSTER1_MPCLK, "dout_cluster1_mpclk", + "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK, 0, 4), + DIV(CLK_DOUT_CLUSTER1_PCLK, "dout_cluster1_pclk", + "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK, 0, 4), + DIV(CLK_DOUT_CLUSTER1_PERIPHCLK, "dout_cluster1_periphclk", + "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4), + DIV(CLK_DOUT_CPUCL1_NOCP, "dout_cpucl1_nocp", + "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP, 0, 4), +}; + +static const struct samsung_cmu_info cpucl1_cmu_info __initconst = { + .pll_clks = cpucl1_pll_clks, + .nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks), + .mux_clks = cpucl1_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks), + .div_clks = cpucl1_div_clks, + .nr_div_clks = ARRAY_SIZE(cpucl1_div_clks), + .nr_clk_ids = CLKS_NR_CPUCL1, + .clk_regs = cpucl1_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs), + .clk_name = "cpucl1", +}; + +static void __init exynosautov920_cmu_cpucl1_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info); +} + +/* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */ +CLK_OF_DECLARE(exynosautov920_cmu_cpucl1, "samsung,exynosautov920-cmu-cpucl1", + exynosautov920_cmu_cpucl1_init); + +/* ---- CMU_CPUCL2 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_CPUCL2 (0x1EE00000) */ +#define PLL_LOCKTIME_PLL_CPUCL2 0x0000 +#define PLL_CON0_PLL_CPUCL2 0x0100 +#define PLL_CON1_PLL_CPUCL2 0x0104 +#define PLL_CON3_PLL_CPUCL2 0x010c +#define PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER 0x0600 +#define PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER 0x0610 + +#define CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER 0x1000 +#define CLK_CON_MUX_MUX_CLK_CPUCL2_CORE 0x1004 + +#define CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK 0x1800 +#define CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK 0x1804 +#define CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK 0x1808 +#define CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK 0x180c +#define CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK 0x1810 +#define CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP 0x181c + +static const unsigned long cpucl2_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_CPUCL2, + PLL_CON0_PLL_CPUCL2, + PLL_CON1_PLL_CPUCL2, + PLL_CON3_PLL_CPUCL2, + PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER, + PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER, + CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER, + CLK_CON_MUX_MUX_CLK_CPUCL2_CORE, + CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK, + CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK, + CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK, + CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK, + CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK, + CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP, +}; + +/* List of parent clocks for Muxes in CMU_CPUCL2 */ +PNAME(mout_pll_cpucl2_p) = { "oscclk", "fout_cpucl2_pll" }; +PNAME(mout_cpucl2_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl2_cluster" }; +PNAME(mout_cpucl2_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl2_switch" }; +PNAME(mout_cpucl2_cluster_p) = { "oscclk", "mout_cpucl2_cluster_user", + "mout_cpucl2_switch_user"}; +PNAME(mout_cpucl2_core_p) = { "oscclk", "mout_pll_cpucl2", + "mout_cpucl2_switch_user"}; + +static const struct samsung_pll_clock cpucl2_pll_clks[] __initconst = { + /* CMU_CPUCL2_PURECLKCOMP */ + PLL(pll_531x, CLK_FOUT_CPUCL2_PLL, "fout_cpucl2_pll", "oscclk", + PLL_LOCKTIME_PLL_CPUCL2, PLL_CON3_PLL_CPUCL2, cpu_pll_rates), +}; + +static const struct samsung_mux_clock cpucl2_mux_clks[] __initconst = { + MUX(CLK_MOUT_PLL_CPUCL2, "mout_pll_cpucl2", mout_pll_cpucl2_p, + PLL_CON0_PLL_CPUCL2, 4, 1), + MUX(CLK_MOUT_CPUCL2_CLUSTER_USER, "mout_cpucl2_cluster_user", mout_cpucl2_cluster_user_p, + PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER, 4, 1), + MUX(CLK_MOUT_CPUCL2_SWITCH_USER, "mout_cpucl2_switch_user", mout_cpucl2_switch_user_p, + PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER, 4, 1), + MUX(CLK_MOUT_CPUCL2_CLUSTER, "mout_cpucl2_cluster", mout_cpucl2_cluster_p, + CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER, 0, 2), + MUX(CLK_MOUT_CPUCL2_CORE, "mout_cpucl2_core", mout_cpucl2_core_p, + CLK_CON_MUX_MUX_CLK_CPUCL2_CORE, 0, 2), +}; + +static const struct samsung_div_clock cpucl2_div_clks[] __initconst = { + DIV(CLK_DOUT_CLUSTER2_ACLK, "dout_cluster2_aclk", + "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK, 0, 4), + DIV(CLK_DOUT_CLUSTER2_ATCLK, "dout_cluster2_atclk", + "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK, 0, 4), + DIV(CLK_DOUT_CLUSTER2_MPCLK, "dout_cluster2_mpclk", + "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK, 0, 4), + DIV(CLK_DOUT_CLUSTER2_PCLK, "dout_cluster2_pclk", + "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK, 0, 4), + DIV(CLK_DOUT_CLUSTER2_PERIPHCLK, "dout_cluster2_periphclk", + "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK, 0, 4), + DIV(CLK_DOUT_CPUCL2_NOCP, "dout_cpucl2_nocp", + "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP, 0, 4), +}; + +static const struct samsung_cmu_info cpucl2_cmu_info __initconst = { + .pll_clks = cpucl2_pll_clks, + .nr_pll_clks = ARRAY_SIZE(cpucl2_pll_clks), + .mux_clks = cpucl2_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cpucl2_mux_clks), + .div_clks = cpucl2_div_clks, + .nr_div_clks = ARRAY_SIZE(cpucl2_div_clks), + .nr_clk_ids = CLKS_NR_CPUCL2, + .clk_regs = cpucl2_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cpucl2_clk_regs), + .clk_name = "cpucl2", +}; + +static void __init exynosautov920_cmu_cpucl2_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &cpucl2_cmu_info); +} + +/* Register CMU_CPUCL2 early, as CPU clocks should be available ASAP */ +CLK_OF_DECLARE(exynosautov920_cmu_cpucl2, "samsung,exynosautov920-cmu-cpucl2", + exynosautov920_cmu_cpucl2_init); + /* ---- CMU_PERIC0 --------------------------------------------------------- */ /* Register Offset definitions for CMU_PERIC0 (0x10800000) */ -- 2.49.0 ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] clk: samsung: exynosautov920: add cpucl1/2 clock support 2025-04-28 8:47 ` [PATCH 2/3] clk: samsung: exynosautov920: add cpucl1/2 clock support Shin Son @ 2025-04-28 9:14 ` Krzysztof Kozlowski 2025-04-28 10:47 ` 손신 0 siblings, 1 reply; 8+ messages in thread From: Krzysztof Kozlowski @ 2025-04-28 9:14 UTC (permalink / raw) To: Shin Son, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley, Sunyeal Hong Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 28/04/2025 10:47, Shin Son wrote: > Register compatible and cmu_info data to support clock CPUCL1/2 > (CPU Cluster 1 and CPU Cluster 2), > these provide clock for CPUCL1/2_SWTICH/CLUSTER. > > These clocks are required early during boot for the CPUs, > so they are declared using CLK_OF_DECLARE instead of being registered > through a platform driver. > > Signed-off-by: Shin Son <shin.son@samsung.com> > --- > drivers/clk/samsung/clk-exynosautov920.c | 208 ++++++++++++++++++++++- > 1 file changed, 207 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c > index 8021e0912e50..f8168eed4a66 100644 > --- a/drivers/clk/samsung/clk-exynosautov920.c > +++ b/drivers/clk/samsung/clk-exynosautov920.c > @@ -18,7 +18,9 @@ > > /* NOTE: Must be equal to the last clock ID increased by one */ > #define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1) > -#define CLKS_NR_CPUCL0 (CLK_DOUT_CLUSTER0_PERIPHCLK + 1) > +#define CLKS_NR_CPUCL0 (CLK_DOUT_CPUCL0_NOCP + 1) You just added that line a week ago and it is already incorrect? Then it needs patch on its own explaining what are you fixing. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH 2/3] clk: samsung: exynosautov920: add cpucl1/2 clock support 2025-04-28 9:14 ` Krzysztof Kozlowski @ 2025-04-28 10:47 ` 손신 0 siblings, 0 replies; 8+ messages in thread From: 손신 @ 2025-04-28 10:47 UTC (permalink / raw) To: 'Krzysztof Kozlowski', 'Sylwester Nawrocki', 'Chanwoo Choi', 'Alim Akhtar', 'Michael Turquette', 'Stephen Boyd', 'Rob Herring', 'Conor Dooley', 'Sunyeal Hong' Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Hello, Krzysztof Kozlowski. > -----Original Message----- > From: Krzysztof Kozlowski [mailto:krzk@kernel.org] > Sent: Monday, April 28, 2025 6:15 PM > To: Shin Son <shin.son@samsung.com>; Sylwester Nawrocki > <s.nawrocki@samsung.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim > Akhtar <alim.akhtar@samsung.com>; Michael Turquette > <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob Herring > <robh@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Sunyeal Hong > <sunyeal.hong@samsung.com> > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Subject: Re: [PATCH 2/3] clk: samsung: exynosautov920: add cpucl1/2 clock > support > > On 28/04/2025 10:47, Shin Son wrote: > > Register compatible and cmu_info data to support clock CPUCL1/2 (CPU > > Cluster 1 and CPU Cluster 2), these provide clock for > > CPUCL1/2_SWTICH/CLUSTER. > > > > These clocks are required early during boot for the CPUs, so they are > > declared using CLK_OF_DECLARE instead of being registered through a > > platform driver. > > > > Signed-off-by: Shin Son <shin.son@samsung.com> > > --- > > drivers/clk/samsung/clk-exynosautov920.c | 208 > > ++++++++++++++++++++++- > > 1 file changed, 207 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/clk/samsung/clk-exynosautov920.c > > b/drivers/clk/samsung/clk-exynosautov920.c > > index 8021e0912e50..f8168eed4a66 100644 > > --- a/drivers/clk/samsung/clk-exynosautov920.c > > +++ b/drivers/clk/samsung/clk-exynosautov920.c > > @@ -18,7 +18,9 @@ > > > > /* NOTE: Must be equal to the last clock ID increased by one */ > > #define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1) > > -#define CLKS_NR_CPUCL0 (CLK_DOUT_CLUSTER0_PERIPHCLK + 1) > > +#define CLKS_NR_CPUCL0 (CLK_DOUT_CPUCL0_NOCP + 1) > > > You just added that line a week ago and it is already incorrect? Then it > needs patch on its own explaining what are you fixing. > > > Best regards, > Krzysztof Understood. I will separate the fix into its own patch and resend it. Best regards, Shin Son ^ permalink raw reply [flat|nested] 8+ messages in thread
[parent not found: <CGME20250428084728epcas2p1d293e6a40eae00465c6b2f5f037dbfef@epcas2p1.samsung.com>]
* [PATCH 3/3] arm64: dts: exynosautov920: add cpucl1/2 clock DT nodes [not found] ` <CGME20250428084728epcas2p1d293e6a40eae00465c6b2f5f037dbfef@epcas2p1.samsung.com> @ 2025-04-28 8:47 ` Shin Son 0 siblings, 0 replies; 8+ messages in thread From: Shin Son @ 2025-04-28 8:47 UTC (permalink / raw) To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley, Sunyeal Hong Cc: Shin Son, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Add cmu_cpucl1/2(CPU Cluster 1 and CPU Cluster 2) clocks for switch, cluster domains respectively. Signed-off-by: Shin Son <shin.son@samsung.com> --- .../arm64/boot/dts/exynos/exynosautov920.dtsi | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index 9350c53f935e..2cb8041c8a9f 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1090,6 +1090,32 @@ cmu_cpucl0: clock-controller@1ec00000 { "cluster", "dbg"; }; + + cmu_cpucl1: clock-controller@1ed00000 { + compatible = "samsung,exynosautov920-cmu-cpucl1"; + reg = <0x1ed00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_CPUCL1_SWITCH>, + <&cmu_top DOUT_CLKCMU_CPUCL1_CLUSTER>; + clock-names = "oscclk", + "switch", + "cluster"; + }; + + cmu_cpucl2: clock-controller@1ee00000 { + compatible = "samsung,exynosautov920-cmu-cpucl2"; + reg = <0x1ee00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_CPUCL2_SWITCH>, + <&cmu_top DOUT_CLKCMU_CPUCL2_CLUSTER>; + clock-names = "oscclk", + "switch", + "cluster"; + }; }; timer { -- 2.49.0 ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-04-28 10:47 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
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2025-04-28 8:47 ` [PATCH 0/3] add CPUCL1/2 clock support for exynosauto v920 SoC Shin Son
[not found] ` <CGME20250428084728epcas2p34ffa0051a16c10ff1c358a98cc2c2fa4@epcas2p3.samsung.com>
2025-04-28 8:47 ` [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions Shin Son
2025-04-28 9:13 ` Krzysztof Kozlowski
2025-04-28 10:41 ` 손신
[not found] ` <CGME20250428084728epcas2p17a0253f04de15c23ab6362113a0d47bb@epcas2p1.samsung.com>
2025-04-28 8:47 ` [PATCH 2/3] clk: samsung: exynosautov920: add cpucl1/2 clock support Shin Son
2025-04-28 9:14 ` Krzysztof Kozlowski
2025-04-28 10:47 ` 손신
[not found] ` <CGME20250428084728epcas2p1d293e6a40eae00465c6b2f5f037dbfef@epcas2p1.samsung.com>
2025-04-28 8:47 ` [PATCH 3/3] arm64: dts: exynosautov920: add cpucl1/2 clock DT nodes Shin Son
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