From: Andrew Lunn <andrew@lunn.ch>
To: Kyle Switch <kyle.switch@motor-comm.com>
Cc: Frank.Sae@motor-comm.com, hkallweit1@gmail.com,
linux@armlinux.org.uk, davem@davemloft.net, edumazet@google.com,
kuba@kernel.org, pabeni@redhat.com, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, ming.xu@motor-comm.com,
xiaolin.xu@motor-comm.com, jianmin.wang@motor-comm.com,
jie.han@motor-comm.com
Subject: Re: [PATCH net-next v5] net: phy: Add driver for Motorcomm Quad 2.5GbE phy
Date: Tue, 21 Jul 2026 15:27:27 +0200 [thread overview]
Message-ID: <038431aa-5aaa-4c9c-87dc-bb0c0a1ed847@lunn.ch> (raw)
In-Reply-To: <20260721114810.660718-1-kyle.switch@motor-comm.com>
> +#define YT8824_UTP_TEMPLATE_MODE_CTRL (0x84)
> +#define YT8824_UTP_TEMPLATE_MODE_MASK GENMASK(15, 13)
> +#define YT8824_UTP_TEMPLATE_TEST_MODE1 BIT(13)
Is this MultiGBASE-T test mode register (Register 1.132)?
The test mode control is not a single bit, but three bits. So you
should not be using BIT(13).
Since this is a standard part of C45, please add a helper to phy-c45.c
Another thing i want to take a look at is the locking. It is pretty
ugly having to use so many __ functions, and not being able to use the
helpers. I want to see if we can avoid this.
Andrew
---
pw-bot: cr
next prev parent reply other threads:[~2026-07-21 13:27 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-21 11:48 Kyle Switch
2026-07-21 13:27 ` Andrew Lunn [this message]
2026-07-22 7:44 ` Kyle Switch
2026-07-21 14:18 ` Andrew Lunn
2026-07-22 8:06 ` Kyle Switch
2026-07-22 13:18 ` Andrew Lunn
2026-07-23 9:28 ` Kyle Switch
2026-07-23 14:27 ` Andrew Lunn
2026-07-24 11:46 ` Kyle Switch
2026-07-24 13:18 ` Andrew Lunn
2026-07-24 22:18 ` Andrew Lunn
2026-07-26 3:38 ` Kyle Switch
2026-07-26 4:24 ` Kyle Switch
2026-07-26 3:24 ` Kyle Switch
2026-07-26 14:51 ` Andrew Lunn
2026-07-27 8:47 ` Kyle Switch
2026-07-27 21:36 ` Andrew Lunn
2026-07-28 11:25 ` Kyle Switch
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