[PATCH 0/3] usb: dwc3: add snps,reinit-phy-on-resume quirk for USB2 PHY power loss during S3

[PATCH 0/3] usb: dwc3: add snps,reinit-phy-on-resume quirk for USB2 PHY power loss during S3

[Oliver White]

The Surface Laptop 7 (x1e80100-romulus) gates the USB2 PHY power domain
during S3 even when device_may_wakeup is set, causing PHY register
state to be lost. The DWC3 fast-resume path calls
phy_pm_runtime_get_sync() to restore the PHY, but this is a no-op for
PHY drivers that do not implement runtime PM (e.g. the Qualcomm eUSB2
driver), resulting in corrupted USB2 signalling on resume.

This series adds a new DT quirk flag that forces a full phy_exit() +
phy_init() cycle on each USB2 PHY during system resume, and enables it
for the Romulus board.

Patch 1 documents the new dt-binding property.
Patch 2 implements the quirk in the DWC3 core driver.
Patch 3 enables the quirk on x1e80100-microsoft-romulus.

Oliver White (3):
  dt-bindings: usb: dwc3: document snps,reinit-phy-on-resume
  usb: dwc3: add reinit-phy-on-resume quirk
  arm64: dts: qcom: x1e80100-microsoft-romulus: add phy-reinit-on-resume

 .../bindings/usb/snps,dwc3-common.yaml        | 10 ++++++++
 .../dts/qcom/x1e80100-microsoft-romulus.dtsi  |  4 +++
 drivers/usb/dwc3/core.c                       | 25 +++++++++++++++++++
 drivers/usb/dwc3/core.h                       |  1 +
 4 files changed, 40 insertions(+)

-- 
2.53.0

[PATCH 1/3] dt-bindings: usb: dwc3: document snps,reinit-phy-on-resume

[Oliver White]

Add the documentation for the 'snps,reinit-phy-on-resume' boolean
property. When set, the DWC3 core will perform a full phy_exit() +
phy_init() cycle on each USB2 PHY during the host-mode fast resume
path. This is needed on platforms where the USB2 PHY power domain
is gated during deep sleep even when device_may_wakeup is true.

Signed-off-by: Oliver White <oliverjwhite07@gmail.com>
---
 .../devicetree/bindings/usb/snps,dwc3-common.yaml      | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
index 6c0b8b653824..d12f6ae81ab8 100644
--- a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
+++ b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
@@ -212,6 +212,16 @@ properties:
       When set, run the SOF/ITP counter based on ref_clk.
     type: boolean
 
+  snps,reinit-phy-on-resume:
+    description:
+      When set, the DWC3 will re-initialize the USB2 PHYs during the
+      host-mode fast resume path (device_may_wakeup). Some platforms
+      cut PHY power during deep sleep even when USB wake is enabled,
+      and the standard PHY runtime PM resume is insufficient to restore
+      the PHY register state. This quirk forces a full phy_exit() +
+      phy_init() cycle on each USB2 PHY.
+    type: boolean
+
   snps,resume-hs-terminations:
     description:
       Fix the issue of HS terminations CRC error on resume by enabling this
-- 
2.53.0

[PATCH 2/3] usb: dwc3: add reinit-phy-on-resume quirk

[Oliver White]

Some platforms gate the USB2 PHY power domain during deep sleep
(S3) even when device_may_wakeup is set, which causes the PHY
register state to be lost. The DWC3 fast resume path (taken when
device_may_wakeup is true) relies on phy_pm_runtime_get_sync() to
restore the PHY, but this is a no-op for PHY drivers that do not
implement runtime PM (e.g. the Qualcomm eUSB2 driver).

Add a new boolean quirk 'snps,reinit-phy-on-resume' that, when set,
forces a full phy_exit() + phy_init() cycle on each USB2 PHY during
the host-mode fast resume path. This ensures the PHY registers are
properly re-programmed after power loss.

Signed-off-by: Oliver White <oliverjwhite07@gmail.com>
---
 drivers/usb/dwc3/core.c | 25 +++++++++++++++++++++++++
 drivers/usb/dwc3/core.h |  1 +
 2 files changed, 26 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 161a4d58b2ce..82baaab0d1d1 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1854,6 +1854,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
 
 	dwc->dis_split_quirk = device_property_read_bool(dev,
 				"snps,dis-split-quirk");
+	dwc->reinit_phy_on_resume = device_property_read_bool(dev,
+				"snps,reinit-phy-on-resume");
 
 	dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 	dwc->tx_de_emphasis = tx_de_emphasis;
@@ -2561,6 +2563,29 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
 			dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg);
 		}
 
+		/*
+		 * Some platforms gate USB2 PHY power during deep sleep even
+		 * when device_may_wakeup is true, causing register state to be
+		 * lost.  Re-initialize the PHY to ensure clean signalling.
+		 */
+		if (dwc->reinit_phy_on_resume && !PMSG_IS_AUTO(msg)) {
+			for (i = 0; i < dwc->num_usb2_ports; i++) {
+				int ret;
+
+				ret = phy_exit(dwc->usb2_generic_phy[i]);
+				if (ret)
+					dev_warn_ratelimited(dwc->dev,
+						"failed to exit usb2 phy %d: %d\n",
+						i, ret);
+
+				ret = phy_init(dwc->usb2_generic_phy[i]);
+				if (ret)
+					dev_warn_ratelimited(dwc->dev,
+						"failed to init usb2 phy %d: %d\n",
+						i, ret);
+			}
+		}
+
 		for (i = 0; i < dwc->num_usb2_ports; i++)
 			phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]);
 		for (i = 0; i < dwc->num_usb3_ports; i++)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index a35b3db1f9f3..f64cf709e194 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -1403,6 +1403,7 @@ struct dwc3 {
 	unsigned		dis_metastability_quirk:1;
 
 	unsigned		dis_split_quirk:1;
+	unsigned		reinit_phy_on_resume:1;
 	unsigned		async_callbacks:1;
 	unsigned		sys_wakeup:1;
 	unsigned		wakeup_configured:1;
-- 
2.53.0

[PATCH 3/3] arm64: dts: qcom: x1e80100-microsoft-romulus: add phy-reinit-on-resume

[Oliver White]

The Surface Laptop 7 gates the USB2 PHY power domain during deep sleep, causing the PHY register state to be lost. When the DWC3 multi-port controller resumes via the fast path (device_may_wakeup), the PHY is not re-initialized and USB2 devices (such as the wired keyboard on the USB-A port) may exhibit corrupted signalling, e.g. stuck modifier key reports.

Enable the 'snps,reinit-phy-on-resume' quirk to force a full PHY re-initialization cycle on resume.
---
 arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi
index 4356cb88e2bd..2de244ffb54d 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi
@@ -1731,6 +1731,10 @@ &usb_mp {
 	status = "okay";
 };
 
+&usb_mp_dwc3 {
+	snps,reinit-phy-on-resume;
+};
+
 &usb_mp_hsphy0 {
 	vdd-supply = <&vreg_l2e>;
 	vdda12-supply = <&vreg_l2j>;
-- 
2.53.0

Re: [PATCH 1/3] dt-bindings: usb: dwc3: document snps,reinit-phy-on-resume

[Rob Herring]

On Tue, Jun 02, 2026 at 11:12:34AM +1200, Oliver White wrote:
> Add the documentation for the 'snps,reinit-phy-on-resume' boolean
> property. When set, the DWC3 core will perform a full phy_exit() +
> phy_init() cycle on each USB2 PHY during the host-mode fast resume
> path. This is needed on platforms where the USB2 PHY power domain
> is gated during deep sleep even when device_may_wakeup is true.
> 
> Signed-off-by: Oliver White <oliverjwhite07@gmail.com>
> ---
>  .../devicetree/bindings/usb/snps,dwc3-common.yaml      | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
> index 6c0b8b653824..d12f6ae81ab8 100644
> --- a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
> +++ b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
> @@ -212,6 +212,16 @@ properties:
>        When set, run the SOF/ITP counter based on ref_clk.
>      type: boolean
>  
> +  snps,reinit-phy-on-resume:
> +    description:
> +      When set, the DWC3 will re-initialize the USB2 PHYs during the
> +      host-mode fast resume path (device_may_wakeup). Some platforms
> +      cut PHY power during deep sleep even when USB wake is enabled,
> +      and the standard PHY runtime PM resume is insufficient to restore
> +      the PHY register state. This quirk forces a full phy_exit() +
> +      phy_init() cycle on each USB2 PHY.
> +    type: boolean

This should be implied from a platform specific compatible string.

Rob

Re: [PATCH 1/3] dt-bindings: usb: dwc3: document snps,reinit-phy-on-resume

[Dmitry Baryshkov]

On Fri, Jun 05, 2026 at 02:06:38PM -0500, Rob Herring wrote:
> On Tue, Jun 02, 2026 at 11:12:34AM +1200, Oliver White wrote:
> > Add the documentation for the 'snps,reinit-phy-on-resume' boolean
> > property. When set, the DWC3 core will perform a full phy_exit() +
> > phy_init() cycle on each USB2 PHY during the host-mode fast resume
> > path. This is needed on platforms where the USB2 PHY power domain
> > is gated during deep sleep even when device_may_wakeup is true.
> > 
> > Signed-off-by: Oliver White <oliverjwhite07@gmail.com>
> > ---
> >  .../devicetree/bindings/usb/snps,dwc3-common.yaml      | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
> > index 6c0b8b653824..d12f6ae81ab8 100644
> > --- a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
> > +++ b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
> > @@ -212,6 +212,16 @@ properties:
> >        When set, run the SOF/ITP counter based on ref_clk.
> >      type: boolean
> >  
> > +  snps,reinit-phy-on-resume:
> > +    description:
> > +      When set, the DWC3 will re-initialize the USB2 PHYs during the
> > +      host-mode fast resume path (device_may_wakeup). Some platforms
> > +      cut PHY power during deep sleep even when USB wake is enabled,
> > +      and the standard PHY runtime PM resume is insufficient to restore
> > +      the PHY register state. This quirk forces a full phy_exit() +
> > +      phy_init() cycle on each USB2 PHY.
> > +    type: boolean
> 
> This should be implied from a platform specific compatible string.

Platform as in the "root node compatible"?

-- 
With best wishes
Dmitry

Re: [PATCH 3/3] arm64: dts: qcom: x1e80100-microsoft-romulus: add phy-reinit-on-resume

[Krzysztof Kozlowski]

On 02/06/2026 01:12, Oliver White wrote:
> The Surface Laptop 7 gates the USB2 PHY power domain during deep sleep, causing the PHY register state to be lost. When the DWC3 multi-port controller resumes via the fast path (device_may_wakeup), the PHY is not re-initialized and USB2 devices (such as the wired keyboard on the USB-A port) may exhibit corrupted signalling, e.g. stuck modifier key reports.
> 
> Enable the 'snps,reinit-phy-on-resume' quirk to force a full PHY re-initialization cycle on resume.

Please run scripts/checkpatch.pl on the patches and fix reported
warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
patches and (probably) fix more warnings. Some warnings can be ignored,
especially from --strict run, but the code here looks like it needs a
fix. Feel free to get in touch if the warning is not clear.

Please wrap commit message according to Linux coding style / submission
process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597

Please read submitting patches and DCO. DCO chain is missing here.

Best regards,
Krzysztof

Re: [PATCH 1/3] dt-bindings: usb: dwc3: document snps,reinit-phy-on-resume

[Rob Herring]

On Sat, Jun 6, 2026 at 6:21 AM Dmitry Baryshkov
<dmitry.baryshkov@oss.qualcomm.com> wrote:
>
> On Fri, Jun 05, 2026 at 02:06:38PM -0500, Rob Herring wrote:
> > On Tue, Jun 02, 2026 at 11:12:34AM +1200, Oliver White wrote:
> > > Add the documentation for the 'snps,reinit-phy-on-resume' boolean
> > > property. When set, the DWC3 core will perform a full phy_exit() +
> > > phy_init() cycle on each USB2 PHY during the host-mode fast resume
> > > path. This is needed on platforms where the USB2 PHY power domain
> > > is gated during deep sleep even when device_may_wakeup is true.
> > >
> > > Signed-off-by: Oliver White <oliverjwhite07@gmail.com>
> > > ---
> > >  .../devicetree/bindings/usb/snps,dwc3-common.yaml      | 10 ++++++++++
> > >  1 file changed, 10 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
> > > index 6c0b8b653824..d12f6ae81ab8 100644
> > > --- a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
> > > +++ b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
> > > @@ -212,6 +212,16 @@ properties:
> > >        When set, run the SOF/ITP counter based on ref_clk.
> > >      type: boolean
> > >
> > > +  snps,reinit-phy-on-resume:
> > > +    description:
> > > +      When set, the DWC3 will re-initialize the USB2 PHYs during the
> > > +      host-mode fast resume path (device_may_wakeup). Some platforms
> > > +      cut PHY power during deep sleep even when USB wake is enabled,
> > > +      and the standard PHY runtime PM resume is insufficient to restore
> > > +      the PHY register state. This quirk forces a full phy_exit() +
> > > +      phy_init() cycle on each USB2 PHY.
> > > +    type: boolean
> >
> > This should be implied from a platform specific compatible string.
>
> Platform as in the "root node compatible"?

No, the SoC specific one in the node you are trying to add this property to.

Rob

Re: [PATCH 1/3] dt-bindings: usb: dwc3: document snps,reinit-phy-on-resume

[Konrad Dybcio]

On 6/9/26 12:00 AM, Rob Herring wrote:
> On Sat, Jun 6, 2026 at 6:21 AM Dmitry Baryshkov
> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>>
>> On Fri, Jun 05, 2026 at 02:06:38PM -0500, Rob Herring wrote:
>>> On Tue, Jun 02, 2026 at 11:12:34AM +1200, Oliver White wrote:
>>>> Add the documentation for the 'snps,reinit-phy-on-resume' boolean
>>>> property. When set, the DWC3 core will perform a full phy_exit() +
>>>> phy_init() cycle on each USB2 PHY during the host-mode fast resume
>>>> path. This is needed on platforms where the USB2 PHY power domain
>>>> is gated during deep sleep even when device_may_wakeup is true.
>>>>
>>>> Signed-off-by: Oliver White <oliverjwhite07@gmail.com>
>>>> ---
>>>>  .../devicetree/bindings/usb/snps,dwc3-common.yaml      | 10 ++++++++++
>>>>  1 file changed, 10 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
>>>> index 6c0b8b653824..d12f6ae81ab8 100644
>>>> --- a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
>>>> +++ b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
>>>> @@ -212,6 +212,16 @@ properties:
>>>>        When set, run the SOF/ITP counter based on ref_clk.
>>>>      type: boolean
>>>>
>>>> +  snps,reinit-phy-on-resume:
>>>> +    description:
>>>> +      When set, the DWC3 will re-initialize the USB2 PHYs during the
>>>> +      host-mode fast resume path (device_may_wakeup). Some platforms
>>>> +      cut PHY power during deep sleep even when USB wake is enabled,
>>>> +      and the standard PHY runtime PM resume is insufficient to restore
>>>> +      the PHY register state. This quirk forces a full phy_exit() +
>>>> +      phy_init() cycle on each USB2 PHY.
>>>> +    type: boolean
>>>
>>> This should be implied from a platform specific compatible string.
>>
>> Platform as in the "root node compatible"?
> 
> No, the SoC specific one in the node you are trying to add this property to.

Taking a step back, wouldn't this point to an issue in the PHY driver
itself?

Konrad