* [PATCH 1/2] ARM: EXYNOS4: Add more register addresses of CMU and PMU. @ 2011-06-30 0:51 MyungJoo Ham 2011-06-30 0:51 ` [PATCH 2/2] ARM: EXYNOS4: Add more registers to be saved and restored for PM MyungJoo Ham 0 siblings, 1 reply; 4+ messages in thread From: MyungJoo Ham @ 2011-06-30 0:51 UTC (permalink / raw) To: linux-arm-kernel Cc: linux-samsung-soc, linux-kernel, Kukjin Kim, Russell King, Kyungmin Park, Jaecheol Lee, Sylwester Nawrocki, Greg Kroah-Hartman, myungjoo.ham Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> --- arch/arm/mach-exynos4/include/mach/regs-clock.h | 13 +++++++++++++ arch/arm/mach-exynos4/include/mach/regs-pmu.h | 16 ++++++++++++++++ 2 files changed, 29 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h index 64bdd24..f723e62 100644 --- a/arch/arm/mach-exynos4/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h @@ -17,13 +17,17 @@ #define S5P_CLKREG(x) (S5P_VA_CMU + (x)) +#define S5P_CLKSRC_LEFTBUS S5P_CLKREG(0x04200) #define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500) #define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600) #define S5P_CLKGATE_IP_LEFTBUS S5P_CLKREG(0x04800) +#define S5P_CLKOUT_CMU_LEFTBUS S5P_CLKREG(0x04A00) +#define S5P_CLKSRC_RIGHTBUS S5P_CLKREG(0x08200) #define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500) #define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) #define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800) +#define S5P_CLKOUT_CMU_RIGHTBUS S5P_CLKREG(0x08A00) #define S5P_EPLL_LOCK S5P_CLKREG(0x0C010) #define S5P_VPLL_LOCK S5P_CLKREG(0x0C020) @@ -36,7 +40,9 @@ #define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) #define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) #define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) +#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224) #define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228) +#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C) #define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) #define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) #define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) @@ -64,6 +70,7 @@ #define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) #define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) #define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) +#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580) #define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) #define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) @@ -91,6 +98,8 @@ #define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) #define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970) +#define S5P_CLKOUT_CMU_TOP S5P_CLKREG(0x0CA00) + #define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300) #define S5P_CLKSRC_DMC S5P_CLKREG(0x10200) #define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500) @@ -98,6 +107,8 @@ #define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600) #define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900) +#define S5P_CLKOUT_CMU_DMC S5P_CLKREG(0x10A00) + #define S5P_APLL_LOCK S5P_CLKREG(0x14000) #define S5P_MPLL_LOCK S5P_CLKREG(0x14004) #define S5P_APLL_CON0 S5P_CLKREG(0x14100) @@ -116,6 +127,8 @@ #define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) #define S5P_CLKGATE_IP_CPU S5P_CLKREG(0x14900) +#define S5P_CLKOUT_CMU_CPU S5P_CLKREG(0x14A00) + #define S5P_APLL_LOCKTIME (0x1C20) /* 300us */ #define S5P_APLLCON0_ENABLE_SHIFT (31) diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h index a964337..8c4596f 100644 --- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h @@ -33,8 +33,16 @@ #define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) #define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) +#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700) +#define S5P_USBOTG_PHY_CONTROL S5P_PMUREG(0x0704) #define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708) #define S5P_USBHOST_PHY_ENABLE (1 << 0) +#define S5P_DAC_CONTROL S5P_PMUREG(0x070C) +#define S5P_MIPI_CONTROL0 S5P_PMUREG(0x0710) +#define S5P_MIPI_CONTROL1 S5P_PMUREG(0x0714) +#define S5P_ADC_CONTROL S5P_PMUREG(0x0718) +#define S5P_PCIE_CONTROL S5P_PMUREG(0x071C) +#define S5P_SATA_CONTROL S5P_PMUREG(0x0720) #define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4) #define S5P_MIPI_DPHY_ENABLE (1 << 0) @@ -51,6 +59,8 @@ #define S5P_INFORM6 S5P_PMUREG(0x0818) #define S5P_INFORM7 S5P_PMUREG(0x081C) +#define S5P_PMU_DEBUG S5P_PMUREG(0x0A00) + #define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000) #define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004) #define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008) @@ -130,6 +140,8 @@ #define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088) #define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408) +#define S5P_ARM_CPU_L2_0_CONFIGURATION S5P_PMUREG(0x2600) +#define S5P_ARM_CPU_L2_1_CONFIGURATION S5P_PMUREG(0x2620) #define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48) #define S5P_CAM_OPTION S5P_PMUREG(0x3C08) #define S5P_TV_OPTION S5P_PMUREG(0x3C28) @@ -149,6 +161,10 @@ #define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188) #define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8) +#define S5P_XUSBXTI_CONFIGURATION S5P_PMUREG(0x3400) +#define S5P_XXTI_CONFIGURATION S5P_PMUREG(0x3420) +#define S5P_MAUDIO_CONFIGURATION S5P_PMUREG(0x3CC0) + #define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) #define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) #define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) -- 1.7.4.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2] ARM: EXYNOS4: Add more registers to be saved and restored for PM 2011-06-30 0:51 [PATCH 1/2] ARM: EXYNOS4: Add more register addresses of CMU and PMU MyungJoo Ham @ 2011-06-30 0:51 ` MyungJoo Ham 2011-07-18 8:00 ` Kukjin Kim 0 siblings, 1 reply; 4+ messages in thread From: MyungJoo Ham @ 2011-06-30 0:51 UTC (permalink / raw) To: linux-arm-kernel Cc: linux-samsung-soc, linux-kernel, Kukjin Kim, Russell King, Kyungmin Park, Jaecheol Lee, Sylwester Nawrocki, Greg Kroah-Hartman, myungjoo.ham We need more registers to be saved and restored for PM of Exynos4210. Otherwise, with additional drivers running, suspend-to-RAM fails to wake up properly. This patch adds registers omitted in the initial PM patches. Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> --- arch/arm/mach-exynos4/pm.c | 77 +++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 76 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c index a103c13..24c9265 100644 --- a/arch/arm/mach-exynos4/pm.c +++ b/arch/arm/mach-exynos4/pm.c @@ -27,6 +27,8 @@ #include <plat/cpu.h> #include <plat/pm.h> #include <plat/pll.h> +#include <plat/regs-srom.h> +#include <plat/regs-timer.h> #include <mach/regs-irq.h> #include <mach/regs-gpio.h> @@ -60,14 +62,20 @@ static struct sleep_save exynos4_vpll_save[] = { static struct sleep_save exynos4_core_save[] = { /* CMU side */ + SAVE_ITEM(S5P_CLKSRC_LEFTBUS), SAVE_ITEM(S5P_CLKDIV_LEFTBUS), SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), + SAVE_ITEM(S5P_CLKOUT_CMU_LEFTBUS), + SAVE_ITEM(S5P_CLKSRC_RIGHTBUS), SAVE_ITEM(S5P_CLKDIV_RIGHTBUS), SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS), + SAVE_ITEM(S5P_CLKOUT_CMU_RIGHTBUS), SAVE_ITEM(S5P_CLKSRC_TOP0), SAVE_ITEM(S5P_CLKSRC_TOP1), SAVE_ITEM(S5P_CLKSRC_CAM), + SAVE_ITEM(S5P_CLKSRC_TV), SAVE_ITEM(S5P_CLKSRC_MFC), + SAVE_ITEM(S5P_CLKSRC_G3D), SAVE_ITEM(S5P_CLKSRC_IMAGE), SAVE_ITEM(S5P_CLKSRC_LCD0), SAVE_ITEM(S5P_CLKSRC_LCD1), @@ -94,6 +102,7 @@ static struct sleep_save exynos4_core_save[] = { SAVE_ITEM(S5P_CLKDIV_PERIL4), SAVE_ITEM(S5P_CLKDIV_PERIL5), SAVE_ITEM(S5P_CLKDIV_TOP), + SAVE_ITEM(S5P_CLKSRC_MASK_TOP), SAVE_ITEM(S5P_CLKSRC_MASK_CAM), SAVE_ITEM(S5P_CLKSRC_MASK_TV), SAVE_ITEM(S5P_CLKSRC_MASK_LCD0), @@ -102,6 +111,7 @@ static struct sleep_save exynos4_core_save[] = { SAVE_ITEM(S5P_CLKSRC_MASK_FSYS), SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0), SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1), + SAVE_ITEM(S5P_CLKDIV2_RATIO), SAVE_ITEM(S5P_CLKGATE_SCLKCAM), SAVE_ITEM(S5P_CLKGATE_IP_CAM), SAVE_ITEM(S5P_CLKGATE_IP_TV), @@ -115,15 +125,59 @@ static struct sleep_save exynos4_core_save[] = { SAVE_ITEM(S5P_CLKGATE_IP_PERIL), SAVE_ITEM(S5P_CLKGATE_IP_PERIR), SAVE_ITEM(S5P_CLKGATE_BLOCK), + SAVE_ITEM(S5P_CLKOUT_CMU_TOP), SAVE_ITEM(S5P_CLKSRC_MASK_DMC), SAVE_ITEM(S5P_CLKSRC_DMC), SAVE_ITEM(S5P_CLKDIV_DMC0), SAVE_ITEM(S5P_CLKDIV_DMC1), SAVE_ITEM(S5P_CLKGATE_IP_DMC), + SAVE_ITEM(S5P_CLKOUT_CMU_DMC), + SAVE_ITEM(S5P_APLL_LOCK), + SAVE_ITEM(S5P_MPLL_LOCK), + SAVE_ITEM(S5P_APLL_CON0), + SAVE_ITEM(S5P_APLL_CON1), + SAVE_ITEM(S5P_MPLL_CON0), + SAVE_ITEM(S5P_MPLL_CON1), SAVE_ITEM(S5P_CLKSRC_CPU), SAVE_ITEM(S5P_CLKDIV_CPU), + SAVE_ITEM(S5P_CLKDIV_CPU + 0x4), SAVE_ITEM(S5P_CLKGATE_SCLKCPU), SAVE_ITEM(S5P_CLKGATE_IP_CPU), + SAVE_ITEM(S5P_CLKOUT_CMU_CPU), + + /* PMU */ + SAVE_ITEM(S5P_HDMI_PHY_CONTROL), + SAVE_ITEM(S5P_USBOTG_PHY_CONTROL), + SAVE_ITEM(S5P_USBHOST_PHY_CONTROL), + SAVE_ITEM(S5P_DAC_CONTROL), + SAVE_ITEM(S5P_MIPI_CONTROL0), + SAVE_ITEM(S5P_MIPI_CONTROL1), + SAVE_ITEM(S5P_ADC_CONTROL), + SAVE_ITEM(S5P_PCIE_CONTROL), + SAVE_ITEM(S5P_SATA_CONTROL), + SAVE_ITEM(S5P_PMU_DEBUG), + SAVE_ITEM(S5P_ARM_CORE0_CONFIGURATION), + SAVE_ITEM(S5P_ARM_CORE1_CONFIGURATION), + SAVE_ITEM(S5P_ARM_CPU_L2_0_CONFIGURATION), + SAVE_ITEM(S5P_ARM_CPU_L2_1_CONFIGURATION), + SAVE_ITEM(S5P_XUSBXTI_CONFIGURATION), + SAVE_ITEM(S5P_XXTI_CONFIGURATION), + SAVE_ITEM(S5P_PMU_CAM_CONF), + SAVE_ITEM(S5P_PMU_TV_CONF), + SAVE_ITEM(S5P_PMU_MFC_CONF), + SAVE_ITEM(S5P_PMU_G3D_CONF), + SAVE_ITEM(S5P_PMU_LCD0_CONF), + SAVE_ITEM(S5P_PMU_LCD1_CONF), + SAVE_ITEM(S5P_MAUDIO_CONFIGURATION), + SAVE_ITEM(S5P_PMU_GPS_CONF), + + /* System Controller side */ + SAVE_ITEM(S3C_VA_SYS + 0x0210), + SAVE_ITEM(S3C_VA_SYS + 0x0214), + SAVE_ITEM(S3C_VA_SYS + 0x0218), + SAVE_ITEM(S3C_VA_SYS + 0x0220), + SAVE_ITEM(S3C_VA_SYS + 0x0230), + /* GIC side */ SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), @@ -232,11 +286,32 @@ static struct sleep_save exynos4_core_save[] = { SAVE_ITEM(S5P_VA_GIC_DIST + 0xC20), SAVE_ITEM(S5P_VA_GIC_DIST + 0xC24), - SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000), SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010), SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020), SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030), + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040), + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050), + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060), + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070), + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080), + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090), + + /* SROM side */ + SAVE_ITEM(S5P_SROM_BW), + SAVE_ITEM(S5P_SROM_BC0), + SAVE_ITEM(S5P_SROM_BC1), + SAVE_ITEM(S5P_SROM_BC2), + SAVE_ITEM(S5P_SROM_BC3), + + /* PWM Register */ + SAVE_ITEM(S3C2410_TCFG0), + SAVE_ITEM(S3C2410_TCFG1), + SAVE_ITEM(S3C64XX_TINT_CSTAT), + SAVE_ITEM(S3C2410_TCON), + SAVE_ITEM(S3C2410_TCNTB(0)), + SAVE_ITEM(S3C2410_TCMPB(0)), + SAVE_ITEM(S3C2410_TCNTO(0)), }; static struct sleep_save exynos4_l2cc_save[] = { -- 1.7.4.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH 2/2] ARM: EXYNOS4: Add more registers to be saved and restored for PM 2011-06-30 0:51 ` [PATCH 2/2] ARM: EXYNOS4: Add more registers to be saved and restored for PM MyungJoo Ham @ 2011-07-18 8:00 ` Kukjin Kim 2011-07-19 6:02 ` MyungJoo Ham 0 siblings, 1 reply; 4+ messages in thread From: Kukjin Kim @ 2011-07-18 8:00 UTC (permalink / raw) To: 'MyungJoo Ham', linux-arm-kernel Cc: linux-samsung-soc, linux-kernel, 'Russell King', 'Kyungmin Park', 'Jaecheol Lee', 'Sylwester Nawrocki', 'Greg Kroah-Hartman', myungjoo.ham MyungJoo Ham wrote: > > We need more registers to be saved and restored for PM of Exynos4210. > Otherwise, with additional drivers running, suspend-to-RAM fails to wake > up properly. This patch adds registers omitted in the initial PM > patches. > > Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> > --- > arch/arm/mach-exynos4/pm.c | 77 > +++++++++++++++++++++++++++++++++++++++++++- > 1 files changed, 76 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c > index a103c13..24c9265 100644 > --- a/arch/arm/mach-exynos4/pm.c > +++ b/arch/arm/mach-exynos4/pm.c > @@ -27,6 +27,8 @@ > #include <plat/cpu.h> > #include <plat/pm.h> > #include <plat/pll.h> > +#include <plat/regs-srom.h> > +#include <plat/regs-timer.h> > > #include <mach/regs-irq.h> > #include <mach/regs-gpio.h> > @@ -60,14 +62,20 @@ static struct sleep_save exynos4_vpll_save[] = { > > static struct sleep_save exynos4_core_save[] = { > /* CMU side */ > + SAVE_ITEM(S5P_CLKSRC_LEFTBUS), I think, the reset/default value(0x0, SCLKMPLL) has no problem. > + SAVE_ITEM(S5P_CLKOUT_CMU_LEFTBUS), This is for debugging? So I think no need this. > + SAVE_ITEM(S5P_CLKSRC_RIGHTBUS), Same as 'CLKSRC_LEFTBUS' > + SAVE_ITEM(S5P_CLKOUT_CMU_RIGHTBUS), Same as 'CMU_LEFTBUS' > + SAVE_ITEM(S5P_CLKOUT_CMU_TOP), For debugging... > + SAVE_ITEM(S5P_CLKOUT_CMU_DMC), Same as above. (snip) > + SAVE_ITEM(S5P_APLL_LOCK), > + SAVE_ITEM(S5P_MPLL_LOCK), > + SAVE_ITEM(S5P_APLL_CON0), > + SAVE_ITEM(S5P_APLL_CON1), > + SAVE_ITEM(S5P_MPLL_CON0), > + SAVE_ITEM(S5P_MPLL_CON1), Basically, these value should be set in boot-loader after wake up. (snip) > + /* PMU */ > + SAVE_ITEM(S5P_HDMI_PHY_CONTROL), > + SAVE_ITEM(S5P_USBOTG_PHY_CONTROL), > + SAVE_ITEM(S5P_USBHOST_PHY_CONTROL), > + SAVE_ITEM(S5P_DAC_CONTROL), > + SAVE_ITEM(S5P_MIPI_CONTROL0), > + SAVE_ITEM(S5P_MIPI_CONTROL1), > + SAVE_ITEM(S5P_ADC_CONTROL), > + SAVE_ITEM(S5P_PCIE_CONTROL), > + SAVE_ITEM(S5P_SATA_CONTROL), > + SAVE_ITEM(S5P_PMU_DEBUG), > + SAVE_ITEM(S5P_ARM_CORE0_CONFIGURATION), > + SAVE_ITEM(S5P_ARM_CORE1_CONFIGURATION), > + SAVE_ITEM(S5P_ARM_CPU_L2_0_CONFIGURATION), > + SAVE_ITEM(S5P_ARM_CPU_L2_1_CONFIGURATION), > + SAVE_ITEM(S5P_XUSBXTI_CONFIGURATION), > + SAVE_ITEM(S5P_XXTI_CONFIGURATION), > + SAVE_ITEM(S5P_PMU_CAM_CONF), > + SAVE_ITEM(S5P_PMU_TV_CONF), > + SAVE_ITEM(S5P_PMU_MFC_CONF), > + SAVE_ITEM(S5P_PMU_G3D_CONF), > + SAVE_ITEM(S5P_PMU_LCD0_CONF), > + SAVE_ITEM(S5P_PMU_LCD1_CONF), > + SAVE_ITEM(S5P_MAUDIO_CONFIGURATION), > + SAVE_ITEM(S5P_PMU_GPS_CONF), Since PMU part is alive block, so no need. > + > + /* System Controller side */ > + SAVE_ITEM(S3C_VA_SYS + 0x0210), > + SAVE_ITEM(S3C_VA_SYS + 0x0214), > + SAVE_ITEM(S3C_VA_SYS + 0x0218), > + SAVE_ITEM(S3C_VA_SYS + 0x0220), > + SAVE_ITEM(S3C_VA_SYS + 0x0230), Hmm..really need this? > + > /* GIC side */ > SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), > SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), > @@ -232,11 +286,32 @@ static struct sleep_save exynos4_core_save[] = { > SAVE_ITEM(S5P_VA_GIC_DIST + 0xC20), > SAVE_ITEM(S5P_VA_GIC_DIST + 0xC24), > > - > SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000), > SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010), > SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020), > SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030), > + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040), > + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050), > + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060), > + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070), > + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080), > + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090), No need to save/restore external GIC part... (snip) > + /* PWM Register */ > + SAVE_ITEM(S3C2410_TCFG0), > + SAVE_ITEM(S3C2410_TCFG1), > + SAVE_ITEM(S3C64XX_TINT_CSTAT), > + SAVE_ITEM(S3C2410_TCON), > + SAVE_ITEM(S3C2410_TCNTB(0)), > + SAVE_ITEM(S3C2410_TCMPB(0)), > + SAVE_ITEM(S3C2410_TCNTO(0)), PWM? I'm not sure why this is needed here. (snip) Others, ok. Thanks. Best regards, Kgene. -- Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] ARM: EXYNOS4: Add more registers to be saved and restored for PM 2011-07-18 8:00 ` Kukjin Kim @ 2011-07-19 6:02 ` MyungJoo Ham 0 siblings, 0 replies; 4+ messages in thread From: MyungJoo Ham @ 2011-07-19 6:02 UTC (permalink / raw) To: Kukjin Kim Cc: linux-arm-kernel, linux-samsung-soc, linux-kernel, Russell King, Kyungmin Park, Jaecheol Lee, Sylwester Nawrocki, Greg Kroah-Hartman On Mon, Jul 18, 2011 at 5:00 PM, Kukjin Kim <kgene.kim@samsung.com> wrote: > MyungJoo Ham wrote: >> >> We need more registers to be saved and restored for PM of Exynos4210. >> Otherwise, with additional drivers running, suspend-to-RAM fails to wake >> up properly. This patch adds registers omitted in the initial PM >> patches. >> >> Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> >> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> >> --- >> arch/arm/mach-exynos4/pm.c | 77 >> +++++++++++++++++++++++++++++++++++++++++++- >> 1 files changed, 76 insertions(+), 1 deletions(-) >> >> diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c >> index a103c13..24c9265 100644 >> --- a/arch/arm/mach-exynos4/pm.c >> +++ b/arch/arm/mach-exynos4/pm.c >> @@ -27,6 +27,8 @@ >> #include <plat/cpu.h> >> #include <plat/pm.h> >> #include <plat/pll.h> >> +#include <plat/regs-srom.h> >> +#include <plat/regs-timer.h> >> >> #include <mach/regs-irq.h> >> #include <mach/regs-gpio.h> >> @@ -60,14 +62,20 @@ static struct sleep_save exynos4_vpll_save[] = { >> >> static struct sleep_save exynos4_core_save[] = { >> /* CMU side */ >> + SAVE_ITEM(S5P_CLKSRC_LEFTBUS), > > I think, the reset/default value(0x0, SCLKMPLL) has no problem. > >> + SAVE_ITEM(S5P_CLKOUT_CMU_LEFTBUS), > > This is for debugging? So I think no need this. > >> + SAVE_ITEM(S5P_CLKSRC_RIGHTBUS), > > Same as 'CLKSRC_LEFTBUS' > >> + SAVE_ITEM(S5P_CLKOUT_CMU_RIGHTBUS), > > Same as 'CMU_LEFTBUS' > >> + SAVE_ITEM(S5P_CLKOUT_CMU_TOP), > > For debugging... > >> + SAVE_ITEM(S5P_CLKOUT_CMU_DMC), > > Same as above. > > (snip) > >> + SAVE_ITEM(S5P_APLL_LOCK), >> + SAVE_ITEM(S5P_MPLL_LOCK), >> + SAVE_ITEM(S5P_APLL_CON0), >> + SAVE_ITEM(S5P_APLL_CON1), >> + SAVE_ITEM(S5P_MPLL_CON0), >> + SAVE_ITEM(S5P_MPLL_CON1), > > Basically, these value should be set in boot-loader after wake up. > > (snip) > >> + /* PMU */ >> + SAVE_ITEM(S5P_HDMI_PHY_CONTROL), >> + SAVE_ITEM(S5P_USBOTG_PHY_CONTROL), >> + SAVE_ITEM(S5P_USBHOST_PHY_CONTROL), >> + SAVE_ITEM(S5P_DAC_CONTROL), >> + SAVE_ITEM(S5P_MIPI_CONTROL0), >> + SAVE_ITEM(S5P_MIPI_CONTROL1), >> + SAVE_ITEM(S5P_ADC_CONTROL), >> + SAVE_ITEM(S5P_PCIE_CONTROL), >> + SAVE_ITEM(S5P_SATA_CONTROL), >> + SAVE_ITEM(S5P_PMU_DEBUG), >> + SAVE_ITEM(S5P_ARM_CORE0_CONFIGURATION), >> + SAVE_ITEM(S5P_ARM_CORE1_CONFIGURATION), >> + SAVE_ITEM(S5P_ARM_CPU_L2_0_CONFIGURATION), >> + SAVE_ITEM(S5P_ARM_CPU_L2_1_CONFIGURATION), >> + SAVE_ITEM(S5P_XUSBXTI_CONFIGURATION), >> + SAVE_ITEM(S5P_XXTI_CONFIGURATION), >> + SAVE_ITEM(S5P_PMU_CAM_CONF), >> + SAVE_ITEM(S5P_PMU_TV_CONF), >> + SAVE_ITEM(S5P_PMU_MFC_CONF), >> + SAVE_ITEM(S5P_PMU_G3D_CONF), >> + SAVE_ITEM(S5P_PMU_LCD0_CONF), >> + SAVE_ITEM(S5P_PMU_LCD1_CONF), >> + SAVE_ITEM(S5P_MAUDIO_CONFIGURATION), >> + SAVE_ITEM(S5P_PMU_GPS_CONF), > > Since PMU part is alive block, so no need. > >> + >> + /* System Controller side */ >> + SAVE_ITEM(S3C_VA_SYS + 0x0210), >> + SAVE_ITEM(S3C_VA_SYS + 0x0214), >> + SAVE_ITEM(S3C_VA_SYS + 0x0218), >> + SAVE_ITEM(S3C_VA_SYS + 0x0220), >> + SAVE_ITEM(S3C_VA_SYS + 0x0230), > > Hmm..really need this? > >> + >> /* GIC side */ >> SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), >> SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), >> @@ -232,11 +286,32 @@ static struct sleep_save exynos4_core_save[] = { >> SAVE_ITEM(S5P_VA_GIC_DIST + 0xC20), >> SAVE_ITEM(S5P_VA_GIC_DIST + 0xC24), >> >> - >> SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000), >> SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010), >> SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020), >> SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030), >> + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040), >> + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050), >> + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060), >> + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070), >> + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080), >> + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090), > > No need to save/restore external GIC part... > > (snip) > >> + /* PWM Register */ >> + SAVE_ITEM(S3C2410_TCFG0), >> + SAVE_ITEM(S3C2410_TCFG1), >> + SAVE_ITEM(S3C64XX_TINT_CSTAT), >> + SAVE_ITEM(S3C2410_TCON), >> + SAVE_ITEM(S3C2410_TCNTB(0)), >> + SAVE_ITEM(S3C2410_TCMPB(0)), >> + SAVE_ITEM(S3C2410_TCNTO(0)), > > PWM? I'm not sure why this is needed here. > > (snip) > > Others, ok. > > Thanks. > > Best regards, > Kgene. > -- > Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer, > SW Solution Development Team, Samsung Electronics Co., Ltd. > > Hello, Removing the registers you've mentioned didn't break the PM test as NURI board also does not use debug clocks. And, PWM driver appears to backup and restore ctirical register; thus, we don't need to back them up at pm.c. That's good. For PLLs, I'll let it rely on bootloader as you've mentioned. The corrected patch will follow this reply soon. Thanks. - MyungJoo -- MyungJoo Ham (함명주), Ph.D. Mobile Software Platform Lab, Digital Media and Communications (DMC) Business Samsung Electronics cell: 82-10-6714-2858 ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2011-07-19 6:02 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2011-06-30 0:51 [PATCH 1/2] ARM: EXYNOS4: Add more register addresses of CMU and PMU MyungJoo Ham 2011-06-30 0:51 ` [PATCH 2/2] ARM: EXYNOS4: Add more registers to be saved and restored for PM MyungJoo Ham 2011-07-18 8:00 ` Kukjin Kim 2011-07-19 6:02 ` MyungJoo Ham
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