[PATCH 00/13] Add clock support for Exynos8855 SoC

[PATCH 00/13] Add clock support for Exynos8855 SoC

[raghav.s]

This patch series adds clock support for below blocks
found in Exynos8855 SoC

TOP & PERIC
PERIS
HSI
USB

This is the minimal clock support provided for other IPs to
be added. More clocks (MUXs, DIVs, GATEs) will be added
as we add more consumers of the clocks

There are many other blocks, for which the support will be
added in forthcoming patch series.

Alim Akhtar (1):
  clk: samsung: clk-pll: Add supoprt for pll_4313

raghav.s (12):
  dt-bindings: clock: exynos8855: add top & peric clock definitions
  clk: samsung: exynos8855: add block top and peric clock support
  arm64: dts: exynos8855: add cmu_top & cmu_peric clock DT nodes
  dt-bindings: clock: exynos8855: add peris clock definitions
  clk: samsung: exynos8855: add block peris clock support
  arm64: dts: exynos8855: add cmu_peris clock DT nodes
  dt-bindings: clock: exynos8855: add hsi clock definitions
  clk: samsung: exynos8855: add block hsi clock support
  arm64: dts: exynos8855: add cmu_hsi clock DT nodes
  dt-bindings: clock: exynos8855: add usb clock definitions
  clk: samsung: exynos8855: add block usb clock support
  arm64: dts: exynos8855: add cmu_usb clock DT nodes

 .../clock/samsung,exynos8855-clock.yaml       | 178 +++++
 arch/arm64/boot/dts/exynos/exynos8855.dtsi    |  63 ++
 drivers/clk/samsung/Makefile                  |   1 +
 drivers/clk/samsung/clk-exynos8855.c          | 710 ++++++++++++++++++
 drivers/clk/samsung/clk-pll.c                 |  11 +-
 drivers/clk/samsung/clk-pll.h                 |   1 +
 .../dt-bindings/clock/samsung,exynos8855.h    | 120 +++
 7 files changed, 1083 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml
 create mode 100644 drivers/clk/samsung/clk-exynos8855.c
 create mode 100644 include/dt-bindings/clock/samsung,exynos8855.h


base-commit: b4515cf4156356e8f4fe6e0fdc17f59adab9772f
-- 
2.34.1

[PATCH 01/13] clk: samsung: clk-pll: Add supoprt for pll_4313

[raghav.s]

From: Alim Akhtar <alim.akhtar@samsung.com>

PLLs 4313 are found in the Exynos8855 SoC and it is similar
to pll_531x except for CON8 offset, so re-using code for
pll_4313

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: raghav.s <raghav.s@samsung.com>
---
 drivers/clk/samsung/clk-pll.c | 11 ++++++++++-
 drivers/clk/samsung/clk-pll.h |  1 +
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index e74552846ba3..b7605aa3c647 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -1306,7 +1306,15 @@ static unsigned long samsung_pll531x_recalc_rate(struct clk_hw *hw,
 	u64 mdiv, fout = parent_rate;
 
 	pll_con0 = readl_relaxed(pll->con_reg);
-	pll_con8 = readl_relaxed(pll->con_reg + 20);
+	if (pll->type == pll_4313) {
+		/* Offset for PLL_CON8 which hold FDIV different for PLL_4313
+		 * which is PLL_LOCKTIME_OFFSET - 0x4
+		 */
+		pll_con8 = readl_relaxed(pll->lock_reg - 4);
+	} else {
+		pll_con8 = readl_relaxed(pll->con_reg + 20);
+	}
+
 	mdiv = (pll_con0 >> PLL531X_MDIV_SHIFT) & PLL531X_MDIV_MASK;
 	pdiv = (pll_con0 >> PLL531X_PDIV_SHIFT) & PLL531X_PDIV_MASK;
 	sdiv = (pll_con0 >> PLL531X_SDIV_SHIFT) & PLL531X_SDIV_MASK;
@@ -1728,6 +1736,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 		break;
 	case pll_531x:
 	case pll_4311:
+	case pll_4313:
 		init.ops = &samsung_pll531x_clk_ops;
 		break;
 	case pll_1031x:
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index d6eb3246611b..ad47dd7b3ed2 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -49,6 +49,7 @@ enum samsung_pll_type {
 	pll_0718x,
 	pll_0732x,
 	pll_4311,
+	pll_4313,
 	pll_1017x,
 	pll_1031x,
 	pll_a9fracm,
-- 
2.34.1

Re: [PATCH 01/13] clk: samsung: clk-pll: Add supoprt for pll_4313

[Krzysztof Kozlowski]

On 28/07/2026 14:10, raghav.s wrote:
> From: Alim Akhtar <alim.akhtar@samsung.com>
> 
> PLLs 4313 are found in the Exynos8855 SoC and it is similar
> to pll_531x except for CON8 offset, so re-using code for
> pll_4313
> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> Signed-off-by: raghav.s <raghav.s@samsung.com>

Looks like name duplicates login.

Best regards,
Krzysztof

RE: [PATCH 01/13] clk: samsung: clk-pll: Add supoprt for pll_4313

[Raghav Sharma]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Tuesday, July 28, 2026 5:29 PM
> To: raghav.s <raghav.s@samsung.com>; s.nawrocki@samsung.com;
> cw00.choi@samsung.com; peter.griffin@linaro.org;
> alim.akhtar@samsung.com; mturquette@baylibre.com; sboyd@kernel.org;
> bmasney@redhat.com; robh@kernel.org; conor+dt@kernel.org
> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; hajun.sung@samsung.com;
> is.gandhi@samsung.com; ts.amit@samsung.com;
> pokala.reddy@samsung.com
> Subject: Re: [PATCH 01/13] clk: samsung: clk-pll: Add supoprt for pll_4313
> 
> On 28/07/2026 14:10, raghav.s wrote:
> > From: Alim Akhtar <alim.akhtar@samsung.com>
> >
> > PLLs 4313 are found in the Exynos8855 SoC and it is similar to
> > pll_531x except for CON8 offset, so re-using code for
> > pll_4313
> >
> > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> > Signed-off-by: raghav.s <raghav.s@samsung.com>
> 
> Looks like name duplicates login.
> 
> Best regards,
> Krzysztof

Hi Krzysztof
Looks like this was an issue with my gitconfig, will fix this
Thanks for pointing out

Regards
Raghav

[PATCH 02/13] dt-bindings: clock: exynos8855: add top & peric clock definitions

[raghav.s]

Add device tree clock binding definitions for CMU_TOP & CMU_PERIC

Signed-off-by: raghav.s <raghav.s@samsung.com>
---
 .../clock/samsung,exynos8855-clock.yaml       | 115 ++++++++++++++++++
 .../dt-bindings/clock/samsung,exynos8855.h    |  82 +++++++++++++
 2 files changed, 197 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml
 create mode 100644 include/dt-bindings/clock/samsung,exynos8855.h

diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml
new file mode 100644
index 000000000000..073c19debd0d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos8855-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos 8855 SoC clock controller
+
+maintainers:
+  - Raghav Sharma <raghav.s@samsung.com>
+
+description: |
+  Exynos 8855 clock controller is comprised of several CMU units, generating
+  clocks for different domains. Those CMU units are modeled as separate device
+  tree nodes, and might depend on each other. Root clocks in that clock tree are
+  two external clocks:: OSCCLK/XTCXO (76.8 MHz) and RTCCLK/XrtcXTI (32768 Hz).
+  The external OSCCLK must be defined as fixed-rate clock in dts.
+
+  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
+  dividers; all other clocks of function blocks (other CMUs) are usually
+  derived from CMU_TOP.
+
+  Each clock is assigned an identifier and client nodes can use this identifier
+  to specify the clock which they consume. All clocks available for usage
+  in clock consumer nodes are defined as preprocessor macros in
+  'include/dt-bindings/clock/samsung,exynos8855.h' header.
+
+properties:
+  compatible:
+    enum:
+      - samsung,exynos8855-cmu-peric
+      - samsung,exynos8855-cmu-top
+
+  clocks:
+    minItems: 1
+    maxItems: 4
+
+  clock-names:
+    minItems: 1
+    maxItems: 4
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos8855-cmu-peric
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (76.8 MHz)
+            - description: CMU_PERIC NOC clock (from CMU_TOP)
+            - description: CMU_PERIC MMC_CARD clock (from CMU_TOP)
+            - description: CMU_PERIC IP clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+            - const: mmc_card
+            - const: ip
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos8855-cmu-top
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (76.8 MHz)
+
+        clock-names:
+          items:
+            - const: oscclk
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clocks
+  - clock-names
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/samsung,exynos8855.h>
+
+    cmu_peric0: clock-controller@15400000 {
+        compatible = "samsung,exynos8855-cmu-peric";
+        reg = <0x15400000 0x8000>;
+        #clock-cells = <1>;
+
+        clocks = <&xtcxo>,
+                 <&cmu_top CLKCMU_DOUT_PERIC_NOC>,
+                 <&cmu_top CLKCMU_DOUT_PERIC_MMC_CARD>,
+                 <&cmu_top CLKCMU_DOUT_PERIC_IP>;
+        clock-names = "oscclk",
+                      "bus",
+                      "mmc_card",
+                      "ip";
+    };
+
+...
diff --git a/include/dt-bindings/clock/samsung,exynos8855.h b/include/dt-bindings/clock/samsung,exynos8855.h
new file mode 100644
index 000000000000..14369b749fb2
--- /dev/null
+++ b/include/dt-bindings/clock/samsung,exynos8855.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2026 Samsung Electronics Co., Ltd.
+ * Author: Raghav Sharma <raghav.s@samsung.com>
+ *
+ * Device Tree binding constants for Exynos 8855 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS8855_H
+#define _DT_BINDINGS_CLOCK_EXYNOS8855_H
+
+/* CMU_TOP  */
+#define FOUT_SHARED0_PLL		   1
+#define FOUT_SHARED1_PLL		   2
+#define FOUT_SHARED2_PLL		   3
+#define FOUT_SHARED3_PLL		   4
+#define FOUT_SHARED4_PLL		   5
+#define FOUT_MMC_PLL			   6
+#define MOUT_SHARED0_PLL		   7
+#define MOUT_SHARED1_PLL		   8
+#define MOUT_SHARED2_PLL		   9
+#define MOUT_SHARED3_PLL		   10
+#define MOUT_SHARED4_PLL		   11
+#define MOUT_MMC_PLL			   12
+#define CLKCMU_MOUT_PERIC_NOC              13
+#define CLKCMU_MOUT_PERIC_MMC_CARD         14
+#define CLKCMU_MOUT_PERIC_IP               15
+#define CLKCMU_DOUT_PERIC_NOC              16
+#define CLKCMU_DOUT_PERIC_MMC_CARD         17
+#define CLKCMU_DOUT_PERIC_IP               18
+#define DOUT_SHARED0_DIV1		   19
+#define DOUT_SHARED0_DIV2		   20
+#define DOUT_SHARED0_DIV3		   21
+#define DOUT_SHARED0_DIV4		   22
+#define DOUT_SHARED1_DIV1		   23
+#define DOUT_SHARED1_DIV2		   24
+#define DOUT_SHARED1_DIV3		   25
+#define DOUT_SHARED1_DIV4		   26
+#define DOUT_SHARED2_DIV1		   27
+#define DOUT_SHARED2_DIV2		   28
+#define DOUT_SHARED2_DIV3		   29
+#define DOUT_SHARED2_DIV4		   30
+#define DOUT_SHARED3_DIV1		   31
+#define DOUT_SHARED3_DIV2		   32
+#define DOUT_SHARED3_DIV3		   33
+#define DOUT_SHARED3_DIV4		   34
+#define DOUT_SHARED4_DIV1		   35
+#define DOUT_SHARED4_DIV2		   36
+#define DOUT_SHARED4_DIV3		   37
+#define DOUT_SHARED4_DIV4		   38
+#define FOUT_MMC_PLL_DIV1                  39
+#define FOUT_MMC_PLL_DIV2                  40
+
+/* CMU_PERIC */
+#define CLK_MOUT_PERIC_IP_USER             1
+#define CLK_MOUT_PERIC_MMC_CARD_USER       2
+#define CLK_MOUT_PERIC_NOC_USER            3
+#define CLK_MOUT_PERIC_I2C                 4
+#define CLK_MOUT_PERIC_UART_DBG            5
+#define CLK_MOUT_PERIC_USI00               6
+#define CLK_MOUT_PERIC_USI01               7
+#define CLK_MOUT_PERIC_USI02               8
+#define CLK_MOUT_PERIC_USI03               9
+#define CLK_MOUT_PERIC_USI04               10
+#define CLK_MOUT_PERIC_USI09_USI_OIS       11
+#define CLK_MOUT_PERIC_USI10_USI_OIS       12
+#define CLK_DOUT_PERIC_NOCP                13
+#define CLK_DOUT_PERIC_UART_DBG            14
+#define CLK_DOUT_PERIC_USI00_USI           15
+#define CLK_DOUT_PERIC_USI01_USI           16
+#define CLK_DOUT_PERIC_USI02_USI           17
+#define CLK_DOUT_PERIC_USI03_USI           18
+#define CLK_DOUT_PERIC_USI04_USI           19
+#define CLK_DOUT_PERIC_USI09_USI_OIS       20
+#define CLK_DOUT_PERIC_USI10_USI_OIS       21
+#define CLK_DOUT_PERIC_USI_I2C             22
+#define CLK_GOUT_CMU_PERIC_IPCLKPORT_PCLK  23
+#define CLK_GOUT_SYSREG_PERIC_IPCLKPORT_PCLK 24
+#define CLK_GOUT_UART_DBG_PERIC_IPCLKPORT_PCLK 25
+#define CLK_GOUT_USI_PERIC_IPCLKPORT_PCLK  26
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS8855_H */
-- 
2.34.1

[PATCH 03/13] clk: samsung: exynos8855: add block top and peric clock support

[raghav.s]

Register compatible and cmu_info data to support clocks.
CMU_TOP & CMU_PERIC, these provide clocks for TOP & PERIC

Signed-off-by: raghav.s <raghav.s@samsung.com>
---
 drivers/clk/samsung/Makefile         |   1 +
 drivers/clk/samsung/clk-exynos8855.c | 420 +++++++++++++++++++++++++++
 2 files changed, 421 insertions(+)
 create mode 100644 drivers/clk/samsung/clk-exynos8855.c

diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b3c4ef4e0dbf..29a11f5de121 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos8895.o
 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos990.o
 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynosautov9.o
 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynosautov920.o
+obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)  += clk-exynos8855.o
 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-gs101.o
 obj-$(CONFIG_EXYNOS_ACPM_CLK)		+= clk-acpm.o
 obj-$(CONFIG_S3C64XX_COMMON_CLK)	+= clk-s3c64xx.o
diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c
new file mode 100644
index 000000000000..93528f0077a4
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos8855.c
@@ -0,0 +1,420 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2026 Samsung Electronics Co., Ltd.
+ * Author: Raghav Sharma <raghav.s@samsung.com>
+ *
+ * Common Clock Framework support for Exynos 8855 SoC.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/samsung,exynos8855.h>
+
+#include "clk.h"
+#include "clk-exynos-arm64.h"
+
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_TOP                     (FOUT_MMC_PLL_DIV2 + 1)
+#define CLKS_NR_PERIC                   (CLK_GOUT_USI_PERIC_IPCLKPORT_PCLK + 1)
+
+/* ---- CMU_TOP --------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_TOP (0x13900000) */
+/* PLL */
+#define PLL_LOCKTIME_PLL_SHARED0		             0x8
+#define PLL_LOCKTIME_PLL_SHARED1		             0x10
+#define PLL_LOCKTIME_PLL_SHARED2		             0x18
+#define PLL_LOCKTIME_PLL_MMC                                 0x20
+#define PLL_LOCKTIME_PLL_SHARED3		             0x28
+#define PLL_LOCKTIME_PLL_SHARED4		             0x38
+#define PLL_CON0_PLL_MMC			             0x1c0
+#define PLL_CON3_PLL_MMC			             0x1cc
+#define PLL_CON0_PLL_SHARED0			             0x100
+#define PLL_CON3_PLL_SHARED0			             0x10c
+#define PLL_CON0_PLL_SHARED1			             0x140
+#define PLL_CON3_PLL_SHARED1			             0x14c
+#define PLL_CON0_PLL_SHARED2			             0x180
+#define PLL_CON3_PLL_SHARED2			             0x18c
+#define PLL_CON0_PLL_SHARED3			             0x200
+#define PLL_CON3_PLL_SHARED3			             0x20c
+#define PLL_CON0_PLL_SHARED4			             0x280
+#define PLL_CON3_PLL_SHARED4			             0x28c
+
+/* MUX */
+#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_NOC                 0x1078
+#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_MMC_CARD            0x107c
+#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_IP                  0x1080
+
+/* DIV */
+#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_NOC                 0x1878
+#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_MMC_CARD            0x187c
+#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_IP                  0x1880
+
+static const unsigned long top_clk_regs[] __initconst = {
+	PLL_LOCKTIME_PLL_MMC,
+	PLL_LOCKTIME_PLL_SHARED0,
+	PLL_LOCKTIME_PLL_SHARED1,
+	PLL_LOCKTIME_PLL_SHARED2,
+	PLL_LOCKTIME_PLL_SHARED3,
+	PLL_LOCKTIME_PLL_SHARED4,
+	PLL_CON0_PLL_MMC,
+	PLL_CON3_PLL_MMC,
+	PLL_CON0_PLL_SHARED0,
+	PLL_CON3_PLL_SHARED0,
+	PLL_CON0_PLL_SHARED1,
+	PLL_CON3_PLL_SHARED1,
+	PLL_CON0_PLL_SHARED2,
+	PLL_CON3_PLL_SHARED2,
+	PLL_CON0_PLL_SHARED3,
+	PLL_CON3_PLL_SHARED3,
+	PLL_CON0_PLL_SHARED4,
+	PLL_CON3_PLL_SHARED4,
+	CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_NOC,
+	CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_MMC_CARD,
+	CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_IP,
+	CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_NOC,
+	CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_MMC_CARD,
+	CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_IP,
+};
+
+static const struct samsung_pll_clock top_pll_clks[] __initconst = {
+	PLL(pll_4313, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
+	PLL(pll_4313, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
+	PLL(pll_4313, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
+	PLL(pll_4313, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
+	PLL(pll_4313, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
+	PLL(pll_4313, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
+};
+
+/* List of parent clocks for Muxes in CMU_TOP */
+PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
+PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
+PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
+PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
+PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
+PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
+
+PNAME(mout_clkcmu_peric_noc_p)            = { "dout_shared0_div2", "dout_shared0_div3",
+						"dout_shared1_div2", "dout_shared1_div3",
+						"dout_shared2_div2", "dout_shared2_div3",
+						"fout_mmc_pll_div2", "dout_shared3_div3"};
+PNAME(mout_clkcmu_peric_mmc_card_p)       = { "oscclk", "dout_shared0_div2",
+						"fout_mmc_pll_div1", "dout_shared1_div2",
+						"dout_shared2_div2", "dout_shared2_div3",
+						"dout_shared3_div2", "dout_shared3_div3"};
+PNAME(mout_clkcmu_peric_ip_p)            = { "dout_shared0_div4", "dout_shared1_div4"};
+
+static const struct samsung_mux_clock top_mux_clks[] __initconst = {
+	MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
+	    PLL_CON0_PLL_SHARED0, 4, 1),
+	MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
+	    PLL_CON0_PLL_SHARED1, 4, 1),
+	MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
+	    PLL_CON0_PLL_SHARED2, 4, 1),
+	MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
+	    PLL_CON0_PLL_SHARED3, 4, 1),
+	MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p,
+	    PLL_CON0_PLL_SHARED4, 4, 1),
+	MUX(MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
+	    PLL_CON0_PLL_MMC, 4, 1),
+	MUX(CLKCMU_MOUT_PERIC_NOC, "mout_clkcmu_peric_noc",
+	    mout_clkcmu_peric_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_NOC, 0, 3),
+	MUX(CLKCMU_MOUT_PERIC_MMC_CARD, "mout_clkcmu_peric_mmc_card",
+	    mout_clkcmu_peric_mmc_card_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_MMC_CARD, 0, 3),
+	MUX(CLKCMU_MOUT_PERIC_IP, "mout_clkcmu_peric_ip",
+	    mout_clkcmu_peric_ip_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_IP, 0, 1),
+};
+
+static const struct samsung_div_clock top_div_clks[] __initconst = {
+	DIV(CLKCMU_DOUT_PERIC_NOC, "dout_clkcmu_peric_noc",
+	    "mout_clkcmu_peric_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_NOC,
+	    0, 4),
+	DIV(CLKCMU_DOUT_PERIC_MMC_CARD, "dout_clkcmu_peric_mmc_card",
+	    "mout_clkcmu_peric_mmc_card", CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_MMC_CARD,
+	    0, 10),
+	DIV(CLKCMU_DOUT_PERIC_IP, "dout_clkcmu_peric_ip",
+	    "mout_clkcmu_peric_ip", CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_IP,
+	    0, 4),
+
+};
+
+static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
+	FFACTOR(DOUT_SHARED0_DIV1, "dout_shared0_div1",
+		"mout_shared0_pll", 1, 1, 0),
+	FFACTOR(DOUT_SHARED0_DIV2, "dout_shared0_div2",
+		"mout_shared0_pll", 1, 2, 0),
+	FFACTOR(DOUT_SHARED0_DIV3, "dout_shared0_div3",
+		"mout_shared0_pll", 1, 3, 0),
+	FFACTOR(DOUT_SHARED0_DIV4, "dout_shared0_div4",
+		"mout_shared0_pll", 1, 4, 0),
+	FFACTOR(DOUT_SHARED1_DIV1, "dout_shared1_div1",
+		"mout_shared1_pll", 1, 1, 0),
+	FFACTOR(DOUT_SHARED1_DIV2, "dout_shared1_div2",
+		"mout_shared1_pll", 1, 2, 0),
+	FFACTOR(DOUT_SHARED1_DIV3, "dout_shared1_div3",
+		"mout_shared1_pll", 1, 3, 0),
+	FFACTOR(DOUT_SHARED1_DIV4, "dout_shared1_div4",
+		"mout_shared1_pll", 1, 4, 0),
+	FFACTOR(DOUT_SHARED2_DIV1, "dout_shared2_div1",
+		"mout_shared2_pll", 1, 1, 0),
+	FFACTOR(DOUT_SHARED2_DIV2, "dout_shared2_div2",
+		"mout_shared2_pll", 1, 2, 0),
+	FFACTOR(DOUT_SHARED2_DIV3, "dout_shared2_div3",
+		"mout_shared2_pll", 1, 3, 0),
+	FFACTOR(DOUT_SHARED2_DIV4, "dout_shared2_div4",
+		"mout_shared2_pll", 1, 4, 0),
+	FFACTOR(DOUT_SHARED3_DIV1, "dout_shared3_div1",
+		"mout_shared3_pll", 1, 1, 0),
+	FFACTOR(DOUT_SHARED3_DIV2, "dout_shared3_div2",
+		"mout_shared3_pll", 1, 2, 0),
+	FFACTOR(DOUT_SHARED3_DIV3, "dout_shared3_div3",
+		"mout_shared3_pll", 1, 3, 0),
+	FFACTOR(DOUT_SHARED3_DIV4, "dout_shared3_div4",
+		"mout_shared3_pll", 1, 4, 0),
+	FFACTOR(DOUT_SHARED4_DIV1, "dout_shared4_div1",
+		"mout_shared4_pll", 1, 1, 0),
+	FFACTOR(DOUT_SHARED4_DIV2, "dout_shared4_div2",
+		"mout_shared4_pll", 1, 2, 0),
+	FFACTOR(DOUT_SHARED4_DIV3, "dout_shared4_div3",
+		"mout_shared4_pll", 1, 3, 0),
+	FFACTOR(DOUT_SHARED4_DIV4, "dout_shared4_div4",
+		"mout_shared4_pll", 1, 4, 0),
+	FFACTOR(FOUT_MMC_PLL_DIV1, "fout_mmc_pll_div1",
+		"mout_mmc_pll", 1, 1, 0),
+	FFACTOR(FOUT_MMC_PLL_DIV2, "fout_mmc_pll_div2",
+		"mout_mmc_pll", 1, 2, 0),
+
+};
+
+static const struct samsung_cmu_info top_cmu_info __initconst = {
+	.pll_clks		= top_pll_clks,
+	.nr_pll_clks		= ARRAY_SIZE(top_pll_clks),
+	.mux_clks               = top_mux_clks,
+	.nr_mux_clks            = ARRAY_SIZE(top_mux_clks),
+	.div_clks               = top_div_clks,
+	.nr_div_clks            = ARRAY_SIZE(top_div_clks),
+	.fixed_factor_clks	= top_fixed_factor_clks,
+	.nr_fixed_factor_clks	= ARRAY_SIZE(top_fixed_factor_clks),
+	.nr_clk_ids             = CLKS_NR_TOP,
+	.clk_regs               = top_clk_regs,
+	.nr_clk_regs            = ARRAY_SIZE(top_clk_regs),
+};
+
+static void __init exynos8855_cmu_top_init(struct device_node *np)
+{
+	exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
+}
+
+/* Register CMU_TOP early, as it's a dependency for other early domains */
+CLK_OF_DECLARE(exynos8855_cmu_top, "samsung,exynos8855-cmu-top",
+	       exynos8855_cmu_top_init);
+
+/* ---- CMU_PERIC --------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_PERIC (0x15400000) */
+#define CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_IP_USER            0x600
+#define CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_MMC_CARD_USER      0x610
+#define CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_NOC_USER           0x620
+#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_I2C                    0x1000
+#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_UART_DBG               0x1004
+#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI00                  0x1008
+#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI01                  0x100c
+#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI02                  0x1010
+#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI03                  0x1014
+#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI04                  0x1018
+#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI09_USI_OIS          0x101c
+#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI10_USI_OIS          0x1020
+#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_NOCP                   0x1800
+#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_UART_DBG               0x1804
+#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI00_USI              0x1808
+#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI01_USI              0x180c
+#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI02_USI              0x1810
+#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI03_USI              0x1814
+#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI04_USI              0x1818
+#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI09_USI_OIS          0x181c
+#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI10_USI_OIS          0x1820
+#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI_I2C                0x1824
+#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_CMU_PERIC_IPCLKPORT_PCLK    0x2004
+#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_SYSREG_PERIC_IPCLKPORT_PCLK 0x2060
+#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_UART_DBG_IPCLKPORT_PCLK     0x2064
+#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_USI00_USI_IPCLKPORT_PCLK    0x206c
+
+static const unsigned long peric_clk_regs[] __initconst = {
+	CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_IP_USER,
+	CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_MMC_CARD_USER,
+	CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_NOC_USER,
+	CMU_PERIC_CLK_CON_MUX_CLK_PERIC_I2C,
+	CMU_PERIC_CLK_CON_MUX_CLK_PERIC_UART_DBG,
+	CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI00,
+	CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI01,
+	CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI02,
+	CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI03,
+	CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI04,
+	CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI09_USI_OIS,
+	CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI10_USI_OIS,
+	CMU_PERIC_CLK_CON_DIV_CLK_PERIC_NOCP,
+	CMU_PERIC_CLK_CON_DIV_CLK_PERIC_UART_DBG,
+	CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI00_USI,
+	CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI01_USI,
+	CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI02_USI,
+	CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI03_USI,
+	CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI04_USI,
+	CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI09_USI_OIS,
+	CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI10_USI_OIS,
+	CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI_I2C,
+	CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_CMU_PERIC_IPCLKPORT_PCLK,
+	CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_SYSREG_PERIC_IPCLKPORT_PCLK,
+	CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_UART_DBG_IPCLKPORT_PCLK,
+	CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_USI00_USI_IPCLKPORT_PCLK,
+};
+
+/* List of parent clocks for Muxes in CMU_PERIC */
+PNAME(mout_clkcmu_peric_ip_user_p) = { "oscclk", "dout_clkcmu_peric_ip" };
+PNAME(mout_clkcmu_peric_mmc_card_user_p) = { "oscclk", "dout_clkcmu_peric_mmc_card" };
+PNAME(mout_clkcmu_peric_noc_user_p) = { "oscclk", "dout_clkcmu_peric_noc" };
+PNAME(mout_clkcmu_peric_i2c_p) = { "oscclk", "mout_clkcmu_peric_ip_user" };
+PNAME(mout_clkcmu_peric_uart_dbg_p) = { "oscclk", "mout_clkcmu_peric_ip_user" };
+PNAME(mout_clkcmu_peric_usi0n_p) = { "oscclk", "mout_clkcmu_peric_ip_user" };
+PNAME(mout_clkcmu_peric_usi09_usi_ois_p) = { "oscclk", "mout_clkcmu_peric_ip_user" };
+PNAME(mout_clkcmu_peric_usi10_usi_ois_p) = { "oscclk", "mout_clkcmu_peric_ip_user" };
+
+static const struct samsung_mux_clock peric_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_PERIC_IP_USER, "mout_clkcmu_peric_ip_user",
+	    mout_clkcmu_peric_ip_user_p, CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_IP_USER, 4, 1),
+	MUX(CLK_MOUT_PERIC_MMC_CARD_USER, "mout_clkcmu_peric_mmc_card_user",
+	    mout_clkcmu_peric_mmc_card_user_p, CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_MMC_CARD_USER,
+		4, 1),
+	MUX(CLK_MOUT_PERIC_NOC_USER, "mout_clkcmu_peric_noc_user",
+	    mout_clkcmu_peric_noc_user_p, CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_NOC_USER, 4, 1),
+	MUX(CLK_MOUT_PERIC_I2C, "mout_clkcmu_peric_i2c",
+	    mout_clkcmu_peric_i2c_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_I2C, 0, 1),
+	MUX(CLK_MOUT_PERIC_UART_DBG, "mout_clkcmu_peric_uart_dbg",
+	    mout_clkcmu_peric_uart_dbg_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_UART_DBG, 0, 1),
+	MUX(CLK_MOUT_PERIC_USI00, "mout_clkcmu_peric_usi00",
+	    mout_clkcmu_peric_usi0n_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI00, 0, 1),
+	MUX(CLK_MOUT_PERIC_USI01, "mout_clkcmu_peric_usi01",
+	    mout_clkcmu_peric_usi0n_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI01, 0, 1),
+	MUX(CLK_MOUT_PERIC_USI02, "mout_clkcmu_peric_usi02",
+	    mout_clkcmu_peric_usi0n_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI02, 0, 1),
+	MUX(CLK_MOUT_PERIC_USI03, "mout_clkcmu_peric_usi03",
+	    mout_clkcmu_peric_usi0n_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI03, 0, 1),
+	MUX(CLK_MOUT_PERIC_USI04, "mout_clkcmu_peric_usi04",
+	    mout_clkcmu_peric_usi0n_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI04, 0, 1),
+	MUX(CLK_MOUT_PERIC_USI09_USI_OIS, "mout_clkcmu_peric_usi09_usi_ois",
+	    mout_clkcmu_peric_usi09_usi_ois_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI09_USI_OIS, 0, 1),
+	MUX(CLK_MOUT_PERIC_USI10_USI_OIS, "mout_clkcmu_peric_usi10_usi_ois",
+	    mout_clkcmu_peric_usi10_usi_ois_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI10_USI_OIS, 0, 1),
+};
+
+static const struct samsung_div_clock peric_div_clks[] __initconst = {
+	DIV(CLK_DOUT_PERIC_NOCP, "dout_clkcmu_peric_nocp",
+	    "mout_clkcmu_peric_noc_user", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_NOCP,
+	    0, 4),
+	DIV(CLK_DOUT_PERIC_UART_DBG, "dout_clkcmu_peric_uart_dbg",
+	    "mout_clkcmu_peric_uart_dbg", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_UART_DBG,
+	    0, 4),
+	DIV(CLK_DOUT_PERIC_USI00_USI, "dout_clkcmu_peric_usi00_usi",
+	    "mout_clkcmu_peric_usi00", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI00_USI,
+	    0, 4),
+	DIV(CLK_DOUT_PERIC_USI01_USI, "dout_clkcmu_peric_usi01_usi",
+	    "mout_clkcmu_peric_usi01", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI01_USI,
+	    0, 4),
+	DIV(CLK_DOUT_PERIC_USI02_USI, "dout_clkcmu_peric_usi02_usi",
+	    "mout_clkcmu_peric_usi02", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI02_USI,
+	    0, 4),
+	DIV(CLK_DOUT_PERIC_USI03_USI, "dout_clkcmu_peric_usi03_usi",
+	    "mout_clkcmu_peric_usi03", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI03_USI,
+	    0, 4),
+	DIV(CLK_DOUT_PERIC_USI04_USI, "dout_clkcmu_peric_usi04_usi",
+	    "mout_clkcmu_peric_usi04", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI04_USI,
+	    0, 4),
+	DIV(CLK_DOUT_PERIC_USI09_USI_OIS, "dout_clkcmu_peric_usi09_usi_ois",
+	    "mout_clkcmu_peric_usi09_usi_ois", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI09_USI_OIS,
+	    0, 4),
+	DIV(CLK_DOUT_PERIC_USI10_USI_OIS, "dout_clkcmu_peric_usi10_usi_ois",
+	    "mout_clkcmu_peric_usi10_usi_ois", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI10_USI_OIS,
+	    0, 4),
+	DIV(CLK_DOUT_PERIC_USI_I2C, "dout_clkcmu_peric_usi_i2c",
+	    "mout_clkcmu_peric_i2c", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI_I2C,
+	    0, 4),
+};
+
+static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
+	/* System will hang if this critical clock is gated */
+	GATE(CLK_GOUT_CMU_PERIC_IPCLKPORT_PCLK, "gout_cmu_peric_ipclkport_pclk",
+	     "dout_clkcmu_peric_nocp",
+	     CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_CMU_PERIC_IPCLKPORT_PCLK,
+	     21, CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_SYSREG_PERIC_IPCLKPORT_PCLK, "gout_sysreg_peric_ipclkport_pclk",
+	     "dout_clkcmu_peric_nocp",
+	     CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_SYSREG_PERIC_IPCLKPORT_PCLK,
+	     21, 0, 0),
+	/* System will hang if this critical clock is gated */
+	GATE(CLK_GOUT_UART_DBG_PERIC_IPCLKPORT_PCLK, "gout_uart_dbg_peric_ipclkport_pclk",
+	     "dout_clkcmu_peric_uart_dbg",
+	     CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_UART_DBG_IPCLKPORT_PCLK,
+	     21, CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_USI_PERIC_IPCLKPORT_PCLK, "gout_usi_peric_ipclkport_pclk",
+	     "dout_clkcmu_peric_nocp",
+	     CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_USI00_USI_IPCLKPORT_PCLK,
+	     21, 0, 0),
+};
+
+static const struct samsung_cmu_info peric_cmu_info __initconst = {
+	.mux_clks               = peric_mux_clks,
+	.nr_mux_clks            = ARRAY_SIZE(peric_mux_clks),
+	.div_clks               = peric_div_clks,
+	.nr_div_clks            = ARRAY_SIZE(peric_div_clks),
+	.gate_clks              = peric_gate_clks,
+	.nr_gate_clks           = ARRAY_SIZE(peric_gate_clks),
+	.nr_clk_ids             = CLKS_NR_PERIC,
+	.clk_regs               = peric_clk_regs,
+	.nr_clk_regs            = ARRAY_SIZE(peric_clk_regs),
+	.clk_name               = "bus",
+};
+
+static int __init exynos8855_cmu_probe(struct platform_device *pdev)
+{
+	const struct samsung_cmu_info *info;
+	struct device *dev = &pdev->dev;
+
+	info = of_device_get_match_data(dev);
+	exynos_arm64_register_cmu(dev, dev->of_node, info);
+
+	return 0;
+}
+
+static const struct of_device_id exynos8855_cmu_of_match[] = {
+	{
+		.compatible = "samsung,exynos8855-cmu-peric",
+		.data = &peric_cmu_info,
+	}, {
+		.compatible = "samsung,exynos8855-cmu-top",
+		.data = &top_cmu_info,
+	},
+	{ }
+};
+
+static struct platform_driver exynos8855_cmu_driver __refdata = {
+	.driver = {
+		.name = "exynos8855-cmu",
+		.of_match_table = exynos8855_cmu_of_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = exynos8855_cmu_probe,
+};
+
+static int __init exynos8855_cmu_init(void)
+{
+	return platform_driver_register(&exynos8855_cmu_driver);
+}
+core_initcall(exynos8855_cmu_init);
-- 
2.34.1

Re: [PATCH 03/13] clk: samsung: exynos8855: add block top and peric clock support

[Uwe Kleine-König]

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Hello,

On Tue, Jul 28, 2026 at 05:41:01PM +0530, raghav.s wrote:
> +#include <linux/mod_devicetable.h>
> [...]
> +#include <linux/platform_device.h>

<linux/platform_device.h> already makes sure that of_device_id
is available and <linux/mod_devicetable.h> will go away soon.

So please don't #include the latter.

Best regards
Uwe

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RE: [PATCH 03/13] clk: samsung: exynos8855: add block top and peric clock support

[Raghav Sharma]

> -----Original Message-----
> From: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
> Sent: Wednesday, July 29, 2026 6:08 PM
> To: raghav.s <raghav.s@samsung.com>
> Cc: krzk@kernel.org; s.nawrocki@samsung.com; cw00.choi@samsung.com;
> peter.griffin@linaro.org; alim.akhtar@samsung.com;
> mturquette@baylibre.com; sboyd@kernel.org; bmasney@redhat.com;
> robh@kernel.org; conor+dt@kernel.org; linux-samsung-
> soc@vger.kernel.org; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; hajun.sung@samsung.com;
> is.gandhi@samsung.com; ts.amit@samsung.com;
> pokala.reddy@samsung.com
> Subject: Re: [PATCH 03/13] clk: samsung: exynos8855: add block top and
> peric clock support
> 
> Hello,
> 
> On Tue, Jul 28, 2026 at 05:41:01PM +0530, raghav.s wrote:
> > +#include <linux/mod_devicetable.h>
> > [...]
> > +#include <linux/platform_device.h>
> 
> <linux/platform_device.h> already makes sure that of_device_id is
available
> and <linux/mod_devicetable.h> will go away soon.
> 
> So please don't #include the latter.
> 
> Best regards
> Uwe

Hi Uwe
Thanks for letting me know, I will remove this header from my code:
<linux/mod_devicetable.h>

Regards
Raghav

Re: [PATCH 03/13] clk: samsung: exynos8855: add block top and peric clock support

[Peter Griffin]

Hi Raghav,

Thanks for your patch, it's great to see more Exynos SoC support being
upstreamed.

On Tue, 28 Jul 2026 at 12:52, raghav.s <raghav.s@samsung.com> wrote:
>
> Register compatible and cmu_info data to support clocks.
> CMU_TOP & CMU_PERIC, these provide clocks for TOP & PERIC
>
> Signed-off-by: raghav.s <raghav.s@samsung.com>
> ---
>  drivers/clk/samsung/Makefile         |   1 +
>  drivers/clk/samsung/clk-exynos8855.c | 420 +++++++++++++++++++++++++++
>  2 files changed, 421 insertions(+)
>  create mode 100644 drivers/clk/samsung/clk-exynos8855.c
>
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index b3c4ef4e0dbf..29a11f5de121 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos8895.o
>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)  += clk-exynos990.o
>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)  += clk-exynosautov9.o
>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)  += clk-exynosautov920.o
> +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)  += clk-exynos8855.o
>  obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)  += clk-gs101.o
>  obj-$(CONFIG_EXYNOS_ACPM_CLK)          += clk-acpm.o
>  obj-$(CONFIG_S3C64XX_COMMON_CLK)       += clk-s3c64xx.o
> diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c
> new file mode 100644
> index 000000000000..93528f0077a4
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-exynos8855.c
> @@ -0,0 +1,420 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2026 Samsung Electronics Co., Ltd.
> + * Author: Raghav Sharma <raghav.s@samsung.com>
> + *
> + * Common Clock Framework support for Exynos 8855 SoC.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/clock/samsung,exynos8855.h>
> +
> +#include "clk.h"
> +#include "clk-exynos-arm64.h"
> +
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define CLKS_NR_TOP                     (FOUT_MMC_PLL_DIV2 + 1)
> +#define CLKS_NR_PERIC                   (CLK_GOUT_USI_PERIC_IPCLKPORT_PCLK + 1)
> +
> +/* ---- CMU_TOP --------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_TOP (0x13900000) */
> +/* PLL */
> +#define PLL_LOCKTIME_PLL_SHARED0                            0x8
> +#define PLL_LOCKTIME_PLL_SHARED1                            0x10
> +#define PLL_LOCKTIME_PLL_SHARED2                            0x18
> +#define PLL_LOCKTIME_PLL_MMC                                 0x20
> +#define PLL_LOCKTIME_PLL_SHARED3                            0x28
> +#define PLL_LOCKTIME_PLL_SHARED4                            0x38
> +#define PLL_CON0_PLL_MMC                                    0x1c0
> +#define PLL_CON3_PLL_MMC                                    0x1cc
> +#define PLL_CON0_PLL_SHARED0                                0x100
> +#define PLL_CON3_PLL_SHARED0                                0x10c
> +#define PLL_CON0_PLL_SHARED1                                0x140
> +#define PLL_CON3_PLL_SHARED1                                0x14c
> +#define PLL_CON0_PLL_SHARED2                                0x180
> +#define PLL_CON3_PLL_SHARED2                                0x18c
> +#define PLL_CON0_PLL_SHARED3                                0x200
> +#define PLL_CON3_PLL_SHARED3                                0x20c
> +#define PLL_CON0_PLL_SHARED4                                0x280
> +#define PLL_CON3_PLL_SHARED4                                0x28c
> +
> +/* MUX */
> +#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_NOC                 0x1078
> +#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_MMC_CARD            0x107c
> +#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_IP                  0x1080
> +
> +/* DIV */
> +#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_NOC                 0x1878
> +#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_MMC_CARD            0x187c
> +#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_IP                  0x1880
> +
> +static const unsigned long top_clk_regs[] __initconst = {
> +       PLL_LOCKTIME_PLL_MMC,
> +       PLL_LOCKTIME_PLL_SHARED0,
> +       PLL_LOCKTIME_PLL_SHARED1,
> +       PLL_LOCKTIME_PLL_SHARED2,
> +       PLL_LOCKTIME_PLL_SHARED3,
> +       PLL_LOCKTIME_PLL_SHARED4,
> +       PLL_CON0_PLL_MMC,
> +       PLL_CON3_PLL_MMC,
> +       PLL_CON0_PLL_SHARED0,
> +       PLL_CON3_PLL_SHARED0,
> +       PLL_CON0_PLL_SHARED1,
> +       PLL_CON3_PLL_SHARED1,
> +       PLL_CON0_PLL_SHARED2,
> +       PLL_CON3_PLL_SHARED2,
> +       PLL_CON0_PLL_SHARED3,
> +       PLL_CON3_PLL_SHARED3,
> +       PLL_CON0_PLL_SHARED4,
> +       PLL_CON3_PLL_SHARED4,
> +       CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_NOC,
> +       CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_MMC_CARD,
> +       CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_IP,
> +       CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_NOC,
> +       CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_MMC_CARD,
> +       CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_IP,
> +};

You are missing many registers for the CMU from the top_clk_regs array
and only exposing the registers for the gates/mux/div etc you are
exposing to CCF. When the CMU's power domain is turned off/on (maybe
not for top, but for peric and others) the suspend/resume callbacks
won't restore the state for any of the missing registers. In such a
senario the system will likely hang because all the gates/divs/mux etc
that aren't exposed to CCF will rely on the CMU being in automatic
mode from the bootloader.

In the next version please add all the CMU registers so that state
isn't lost during suspend/resume (this applies to the other CMUs being
added as well).

> +
> +static const struct samsung_pll_clock top_pll_clks[] __initconst = {
> +       PLL(pll_4313, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
> +           PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
> +       PLL(pll_4313, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
> +           PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
> +       PLL(pll_4313, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
> +           PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
> +       PLL(pll_4313, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
> +           PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
> +       PLL(pll_4313, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
> +           PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
> +       PLL(pll_4313, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
> +           PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
> +};
> +
> +/* List of parent clocks for Muxes in CMU_TOP */
> +PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
> +PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
> +PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
> +PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
> +PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
> +PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
> +
> +PNAME(mout_clkcmu_peric_noc_p)            = { "dout_shared0_div2", "dout_shared0_div3",
> +                                               "dout_shared1_div2", "dout_shared1_div3",
> +                                               "dout_shared2_div2", "dout_shared2_div3",
> +                                               "fout_mmc_pll_div2", "dout_shared3_div3"};
> +PNAME(mout_clkcmu_peric_mmc_card_p)       = { "oscclk", "dout_shared0_div2",
> +                                               "fout_mmc_pll_div1", "dout_shared1_div2",
> +                                               "dout_shared2_div2", "dout_shared2_div3",
> +                                               "dout_shared3_div2", "dout_shared3_div3"};
> +PNAME(mout_clkcmu_peric_ip_p)            = { "dout_shared0_div4", "dout_shared1_div4"};
> +
> +static const struct samsung_mux_clock top_mux_clks[] __initconst = {
> +       MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
> +           PLL_CON0_PLL_SHARED0, 4, 1),
> +       MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
> +           PLL_CON0_PLL_SHARED1, 4, 1),
> +       MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
> +           PLL_CON0_PLL_SHARED2, 4, 1),
> +       MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
> +           PLL_CON0_PLL_SHARED3, 4, 1),
> +       MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p,
> +           PLL_CON0_PLL_SHARED4, 4, 1),
> +       MUX(MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
> +           PLL_CON0_PLL_MMC, 4, 1),
> +       MUX(CLKCMU_MOUT_PERIC_NOC, "mout_clkcmu_peric_noc",
> +           mout_clkcmu_peric_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_NOC, 0, 3),
> +       MUX(CLKCMU_MOUT_PERIC_MMC_CARD, "mout_clkcmu_peric_mmc_card",
> +           mout_clkcmu_peric_mmc_card_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_MMC_CARD, 0, 3),
> +       MUX(CLKCMU_MOUT_PERIC_IP, "mout_clkcmu_peric_ip",
> +           mout_clkcmu_peric_ip_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_IP, 0, 1),
> +};
> +
> +static const struct samsung_div_clock top_div_clks[] __initconst = {
> +       DIV(CLKCMU_DOUT_PERIC_NOC, "dout_clkcmu_peric_noc",
> +           "mout_clkcmu_peric_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_NOC,
> +           0, 4),
> +       DIV(CLKCMU_DOUT_PERIC_MMC_CARD, "dout_clkcmu_peric_mmc_card",
> +           "mout_clkcmu_peric_mmc_card", CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_MMC_CARD,
> +           0, 10),
> +       DIV(CLKCMU_DOUT_PERIC_IP, "dout_clkcmu_peric_ip",
> +           "mout_clkcmu_peric_ip", CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_IP,
> +           0, 4),
> +
> +};
> +
> +static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
> +       FFACTOR(DOUT_SHARED0_DIV1, "dout_shared0_div1",
> +               "mout_shared0_pll", 1, 1, 0),
> +       FFACTOR(DOUT_SHARED0_DIV2, "dout_shared0_div2",
> +               "mout_shared0_pll", 1, 2, 0),
> +       FFACTOR(DOUT_SHARED0_DIV3, "dout_shared0_div3",
> +               "mout_shared0_pll", 1, 3, 0),
> +       FFACTOR(DOUT_SHARED0_DIV4, "dout_shared0_div4",
> +               "mout_shared0_pll", 1, 4, 0),
> +       FFACTOR(DOUT_SHARED1_DIV1, "dout_shared1_div1",
> +               "mout_shared1_pll", 1, 1, 0),
> +       FFACTOR(DOUT_SHARED1_DIV2, "dout_shared1_div2",
> +               "mout_shared1_pll", 1, 2, 0),
> +       FFACTOR(DOUT_SHARED1_DIV3, "dout_shared1_div3",
> +               "mout_shared1_pll", 1, 3, 0),
> +       FFACTOR(DOUT_SHARED1_DIV4, "dout_shared1_div4",
> +               "mout_shared1_pll", 1, 4, 0),
> +       FFACTOR(DOUT_SHARED2_DIV1, "dout_shared2_div1",
> +               "mout_shared2_pll", 1, 1, 0),
> +       FFACTOR(DOUT_SHARED2_DIV2, "dout_shared2_div2",
> +               "mout_shared2_pll", 1, 2, 0),
> +       FFACTOR(DOUT_SHARED2_DIV3, "dout_shared2_div3",
> +               "mout_shared2_pll", 1, 3, 0),
> +       FFACTOR(DOUT_SHARED2_DIV4, "dout_shared2_div4",
> +               "mout_shared2_pll", 1, 4, 0),
> +       FFACTOR(DOUT_SHARED3_DIV1, "dout_shared3_div1",
> +               "mout_shared3_pll", 1, 1, 0),
> +       FFACTOR(DOUT_SHARED3_DIV2, "dout_shared3_div2",
> +               "mout_shared3_pll", 1, 2, 0),
> +       FFACTOR(DOUT_SHARED3_DIV3, "dout_shared3_div3",
> +               "mout_shared3_pll", 1, 3, 0),
> +       FFACTOR(DOUT_SHARED3_DIV4, "dout_shared3_div4",
> +               "mout_shared3_pll", 1, 4, 0),
> +       FFACTOR(DOUT_SHARED4_DIV1, "dout_shared4_div1",
> +               "mout_shared4_pll", 1, 1, 0),
> +       FFACTOR(DOUT_SHARED4_DIV2, "dout_shared4_div2",
> +               "mout_shared4_pll", 1, 2, 0),
> +       FFACTOR(DOUT_SHARED4_DIV3, "dout_shared4_div3",
> +               "mout_shared4_pll", 1, 3, 0),
> +       FFACTOR(DOUT_SHARED4_DIV4, "dout_shared4_div4",
> +               "mout_shared4_pll", 1, 4, 0),
> +       FFACTOR(FOUT_MMC_PLL_DIV1, "fout_mmc_pll_div1",
> +               "mout_mmc_pll", 1, 1, 0),
> +       FFACTOR(FOUT_MMC_PLL_DIV2, "fout_mmc_pll_div2",
> +               "mout_mmc_pll", 1, 2, 0),
> +
> +};
> +
> +static const struct samsung_cmu_info top_cmu_info __initconst = {
> +       .pll_clks               = top_pll_clks,
> +       .nr_pll_clks            = ARRAY_SIZE(top_pll_clks),
> +       .mux_clks               = top_mux_clks,
> +       .nr_mux_clks            = ARRAY_SIZE(top_mux_clks),
> +       .div_clks               = top_div_clks,
> +       .nr_div_clks            = ARRAY_SIZE(top_div_clks),
> +       .fixed_factor_clks      = top_fixed_factor_clks,
> +       .nr_fixed_factor_clks   = ARRAY_SIZE(top_fixed_factor_clks),
> +       .nr_clk_ids             = CLKS_NR_TOP,
> +       .clk_regs               = top_clk_regs,
> +       .nr_clk_regs            = ARRAY_SIZE(top_clk_regs),
> +};
> +
> +static void __init exynos8855_cmu_top_init(struct device_node *np)
> +{
> +       exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
> +}
> +
> +/* Register CMU_TOP early, as it's a dependency for other early domains */
> +CLK_OF_DECLARE(exynos8855_cmu_top, "samsung,exynos8855-cmu-top",
> +              exynos8855_cmu_top_init);
> +
> +/* ---- CMU_PERIC --------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_PERIC (0x15400000) */
> +#define CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_IP_USER            0x600
> +#define CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_MMC_CARD_USER      0x610
> +#define CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_NOC_USER           0x620
> +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_I2C                    0x1000
> +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_UART_DBG               0x1004
> +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI00                  0x1008
> +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI01                  0x100c
> +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI02                  0x1010
> +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI03                  0x1014
> +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI04                  0x1018
> +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI09_USI_OIS          0x101c
> +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI10_USI_OIS          0x1020
> +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_NOCP                   0x1800
> +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_UART_DBG               0x1804
> +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI00_USI              0x1808
> +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI01_USI              0x180c
> +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI02_USI              0x1810
> +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI03_USI              0x1814
> +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI04_USI              0x1818
> +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI09_USI_OIS          0x181c
> +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI10_USI_OIS          0x1820
> +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI_I2C                0x1824
> +#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_CMU_PERIC_IPCLKPORT_PCLK    0x2004
> +#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_SYSREG_PERIC_IPCLKPORT_PCLK 0x2060
> +#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_UART_DBG_IPCLKPORT_PCLK     0x2064
> +#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_USI00_USI_IPCLKPORT_PCLK    0x206c
> +
> +static const unsigned long peric_clk_regs[] __initconst = {
> +       CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_IP_USER,
> +       CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_MMC_CARD_USER,
> +       CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_NOC_USER,
> +       CMU_PERIC_CLK_CON_MUX_CLK_PERIC_I2C,
> +       CMU_PERIC_CLK_CON_MUX_CLK_PERIC_UART_DBG,
> +       CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI00,
> +       CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI01,
> +       CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI02,
> +       CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI03,
> +       CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI04,
> +       CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI09_USI_OIS,
> +       CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI10_USI_OIS,
> +       CMU_PERIC_CLK_CON_DIV_CLK_PERIC_NOCP,
> +       CMU_PERIC_CLK_CON_DIV_CLK_PERIC_UART_DBG,
> +       CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI00_USI,
> +       CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI01_USI,
> +       CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI02_USI,
> +       CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI03_USI,
> +       CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI04_USI,
> +       CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI09_USI_OIS,
> +       CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI10_USI_OIS,
> +       CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI_I2C,
> +       CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_CMU_PERIC_IPCLKPORT_PCLK,
> +       CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_SYSREG_PERIC_IPCLKPORT_PCLK,
> +       CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_UART_DBG_IPCLKPORT_PCLK,
> +       CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_USI00_USI_IPCLKPORT_PCLK,
> +};
> +
> +/* List of parent clocks for Muxes in CMU_PERIC */
> +PNAME(mout_clkcmu_peric_ip_user_p) = { "oscclk", "dout_clkcmu_peric_ip" };
> +PNAME(mout_clkcmu_peric_mmc_card_user_p) = { "oscclk", "dout_clkcmu_peric_mmc_card" };
> +PNAME(mout_clkcmu_peric_noc_user_p) = { "oscclk", "dout_clkcmu_peric_noc" };
> +PNAME(mout_clkcmu_peric_i2c_p) = { "oscclk", "mout_clkcmu_peric_ip_user" };
> +PNAME(mout_clkcmu_peric_uart_dbg_p) = { "oscclk", "mout_clkcmu_peric_ip_user" };
> +PNAME(mout_clkcmu_peric_usi0n_p) = { "oscclk", "mout_clkcmu_peric_ip_user" };
> +PNAME(mout_clkcmu_peric_usi09_usi_ois_p) = { "oscclk", "mout_clkcmu_peric_ip_user" };
> +PNAME(mout_clkcmu_peric_usi10_usi_ois_p) = { "oscclk", "mout_clkcmu_peric_ip_user" };
> +
> +static const struct samsung_mux_clock peric_mux_clks[] __initconst = {
> +       MUX(CLK_MOUT_PERIC_IP_USER, "mout_clkcmu_peric_ip_user",
> +           mout_clkcmu_peric_ip_user_p, CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_IP_USER, 4, 1),
> +       MUX(CLK_MOUT_PERIC_MMC_CARD_USER, "mout_clkcmu_peric_mmc_card_user",
> +           mout_clkcmu_peric_mmc_card_user_p, CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_MMC_CARD_USER,
> +               4, 1),
> +       MUX(CLK_MOUT_PERIC_NOC_USER, "mout_clkcmu_peric_noc_user",
> +           mout_clkcmu_peric_noc_user_p, CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_NOC_USER, 4, 1),
> +       MUX(CLK_MOUT_PERIC_I2C, "mout_clkcmu_peric_i2c",
> +           mout_clkcmu_peric_i2c_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_I2C, 0, 1),
> +       MUX(CLK_MOUT_PERIC_UART_DBG, "mout_clkcmu_peric_uart_dbg",
> +           mout_clkcmu_peric_uart_dbg_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_UART_DBG, 0, 1),
> +       MUX(CLK_MOUT_PERIC_USI00, "mout_clkcmu_peric_usi00",
> +           mout_clkcmu_peric_usi0n_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI00, 0, 1),
> +       MUX(CLK_MOUT_PERIC_USI01, "mout_clkcmu_peric_usi01",
> +           mout_clkcmu_peric_usi0n_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI01, 0, 1),
> +       MUX(CLK_MOUT_PERIC_USI02, "mout_clkcmu_peric_usi02",
> +           mout_clkcmu_peric_usi0n_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI02, 0, 1),
> +       MUX(CLK_MOUT_PERIC_USI03, "mout_clkcmu_peric_usi03",
> +           mout_clkcmu_peric_usi0n_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI03, 0, 1),
> +       MUX(CLK_MOUT_PERIC_USI04, "mout_clkcmu_peric_usi04",
> +           mout_clkcmu_peric_usi0n_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI04, 0, 1),
> +       MUX(CLK_MOUT_PERIC_USI09_USI_OIS, "mout_clkcmu_peric_usi09_usi_ois",
> +           mout_clkcmu_peric_usi09_usi_ois_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI09_USI_OIS, 0, 1),
> +       MUX(CLK_MOUT_PERIC_USI10_USI_OIS, "mout_clkcmu_peric_usi10_usi_ois",
> +           mout_clkcmu_peric_usi10_usi_ois_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI10_USI_OIS, 0, 1),
> +};
> +
> +static const struct samsung_div_clock peric_div_clks[] __initconst = {
> +       DIV(CLK_DOUT_PERIC_NOCP, "dout_clkcmu_peric_nocp",
> +           "mout_clkcmu_peric_noc_user", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_NOCP,
> +           0, 4),
> +       DIV(CLK_DOUT_PERIC_UART_DBG, "dout_clkcmu_peric_uart_dbg",
> +           "mout_clkcmu_peric_uart_dbg", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_UART_DBG,
> +           0, 4),
> +       DIV(CLK_DOUT_PERIC_USI00_USI, "dout_clkcmu_peric_usi00_usi",
> +           "mout_clkcmu_peric_usi00", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI00_USI,
> +           0, 4),
> +       DIV(CLK_DOUT_PERIC_USI01_USI, "dout_clkcmu_peric_usi01_usi",
> +           "mout_clkcmu_peric_usi01", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI01_USI,
> +           0, 4),
> +       DIV(CLK_DOUT_PERIC_USI02_USI, "dout_clkcmu_peric_usi02_usi",
> +           "mout_clkcmu_peric_usi02", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI02_USI,
> +           0, 4),
> +       DIV(CLK_DOUT_PERIC_USI03_USI, "dout_clkcmu_peric_usi03_usi",
> +           "mout_clkcmu_peric_usi03", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI03_USI,
> +           0, 4),
> +       DIV(CLK_DOUT_PERIC_USI04_USI, "dout_clkcmu_peric_usi04_usi",
> +           "mout_clkcmu_peric_usi04", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI04_USI,
> +           0, 4),
> +       DIV(CLK_DOUT_PERIC_USI09_USI_OIS, "dout_clkcmu_peric_usi09_usi_ois",
> +           "mout_clkcmu_peric_usi09_usi_ois", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI09_USI_OIS,
> +           0, 4),
> +       DIV(CLK_DOUT_PERIC_USI10_USI_OIS, "dout_clkcmu_peric_usi10_usi_ois",
> +           "mout_clkcmu_peric_usi10_usi_ois", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI10_USI_OIS,
> +           0, 4),
> +       DIV(CLK_DOUT_PERIC_USI_I2C, "dout_clkcmu_peric_usi_i2c",
> +           "mout_clkcmu_peric_i2c", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI_I2C,
> +           0, 4),
> +};
> +
> +static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
> +       /* System will hang if this critical clock is gated */
> +       GATE(CLK_GOUT_CMU_PERIC_IPCLKPORT_PCLK, "gout_cmu_peric_ipclkport_pclk",
> +            "dout_clkcmu_peric_nocp",
> +            CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_CMU_PERIC_IPCLKPORT_PCLK,
> +            21, CLK_IS_CRITICAL, 0),

Rather than use manual clock gating in the Linux driver, add have to
add CLK_IS_CRITICAL / CLK_IGNORE_UNUSED flags, I would suggest putting
the CMU in automatic mode from the beginning. Support for automatic
clock gating was recently added for gs101 in
https://lore.kernel.org/lkml/20251222-automatic-clocks-v7-0-fec86fa89874@linaro.org/
so it should be straightforward to do. I noticed another SoC clock
driver was posted recently that had it enabled as well. The advantage
is you then don't need to boot with clk_ignore_unused kernel command
line, and all the unused clocks in the system will be automatically
gated, saving power. Additionally with the CMU in auto mode, it is
then also easier to expose all the gates to CCF (as you don't need to
worry about experimenting with CLK_IS_CRITICAL / CLK_IGNORE_UNUSED
flags). Also when you dump /sys/kernel/debug/clk/clk_summary you get a
complete view of the clock tree of the SoC.

> +       GATE(CLK_GOUT_SYSREG_PERIC_IPCLKPORT_PCLK, "gout_sysreg_peric_ipclkport_pclk",
> +            "dout_clkcmu_peric_nocp",
> +            CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_SYSREG_PERIC_IPCLKPORT_PCLK,
> +            21, 0, 0),
> +       /* System will hang if this critical clock is gated */
> +       GATE(CLK_GOUT_UART_DBG_PERIC_IPCLKPORT_PCLK, "gout_uart_dbg_peric_ipclkport_pclk",
> +            "dout_clkcmu_peric_uart_dbg",
> +            CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_UART_DBG_IPCLKPORT_PCLK,
> +            21, CLK_IS_CRITICAL, 0),

For gs101 we used a name mangling scheme for the Linux clock names
which removed some of the repetitive strings like _IPCLKPORT from the
Linux clock name string. The intention was to keep the register offset
macro matching the datasheet, but the Linux clock name could be
mangled to be more human readable.

I suggest for exynos8855 you follow the same clock name mangling
strategy, so we keep some consistency for the clock names on newer
Exynos SoCs. So far we haven't encountered any clashes by doing this.
The clock name mangling strategy is mentioned in clk-gs101 (I pasted
relevant bit below)

/*
 * Register name to clock name mangling strategy used in this file
 *
 * Replace PLL_CON0_PLL            with CLK_MOUT_PLL and mout_pll
 * Replace CLK_CON_MUX_MUX_CLKCMU  with CLK_MOUT_CMU and mout_cmu
 * Replace CLK_CON_DIV_CLKCMU      with CLK_DOUT_CMU and dout_cmu
 * Replace CLK_CON_DIV_DIV_CLKCMU  with CLK_DOUT_CMU and dout_cmu
 * Replace CLK_CON_GAT_CLKCMU      with CLK_GOUT_CMU and gout_cmu
 * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu
 *
 * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC
 */

Also IIRC some of the gs101 commits contain the regex's used which may
be useful.

Thanks,

Peter

[PATCH 04/13] arm64: dts: exynos8855: add cmu_top & cmu_peric clock DT nodes

[raghav.s]

Add required dt node for cmu_top & cmu_peric block

Signed-off-by: raghav.s <raghav.s@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos8855.dtsi | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
index 9d82fceb5130..0053730b3e01 100644
--- a/arch/arm64/boot/dts/exynos/exynos8855.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
@@ -10,6 +10,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/samsung,exynos8855.h>
 
 / {
 	compatible = "samsung,exynos8855";
@@ -165,12 +166,35 @@ pinctrl_cmgp: pinctrl@12030000 {
 			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		cmu_top: clock-controller@13900000 {
+			compatible = "samsung,exynos8855-cmu-top";
+			reg = <0x13900000 0x8000>;
+			#clock-cells = <1>;
+			clocks = <&oscclk>;
+			clock-names = "oscclk";
+		};
+
 		pinctrl_usi: pinctrl@15030000 {
 			compatible = "samsung,exynos8855-pinctrl";
 			reg = <0x15030000 0x1000>;
 			interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		cmu_peric: clock-controller@15400000 {
+			compatible = "samsung,exynos8855-cmu-peric";
+			reg = <0x15400000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLKCMU_DOUT_PERIC_NOC>,
+				 <&cmu_top CLKCMU_DOUT_PERIC_MMC_CARD>,
+				 <&cmu_top CLKCMU_DOUT_PERIC_IP>;
+			clock-names = "oscclk",
+				      "bus",
+				      "mmc_card",
+				      "ip";
+		};
+
 		pinctrl_peric: pinctrl@15440000 {
 			compatible = "samsung,exynos8855-pinctrl";
 			reg = <0x15440000 0x1000>;
-- 
2.34.1

Re: [PATCH 04/13] arm64: dts: exynos8855: add cmu_top & cmu_peric clock DT nodes

[Krzysztof Kozlowski]

On 28/07/2026 14:11, raghav.s wrote:
> Add required dt node for cmu_top & cmu_peric block
> 
> Signed-off-by: raghav.s <raghav.s@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos8855.dtsi | 24 ++++++++++++++++++++++
>  1 file changed, 24 insertions(+)

Please organize your patches in reasonable order. DTS is never in the
middle, see submitting patches (both documents) and maintainer-soc profile.

Best regards,
Krzysztof

RE: [PATCH 04/13] arm64: dts: exynos8855: add cmu_top & cmu_peric clock DT nodes

[Alim Akhtar]

Hi Krzysztof,

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Tuesday, July 28, 2026 5:30 PM
> To: raghav.s <raghav.s@samsung.com>; s.nawrocki@samsung.com;
> cw00.choi@samsung.com; peter.griffin@linaro.org;
> alim.akhtar@samsung.com; mturquette@baylibre.com; sboyd@kernel.org;
> bmasney@redhat.com; robh@kernel.org; conor+dt@kernel.org
> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; hajun.sung@samsung.com;
> is.gandhi@samsung.com; ts.amit@samsung.com;
> pokala.reddy@samsung.com
> Subject: Re: [PATCH 04/13] arm64: dts: exynos8855: add cmu_top &
> cmu_peric clock DT nodes
> 
> On 28/07/2026 14:11, raghav.s wrote:
> > Add required dt node for cmu_top & cmu_peric block
> >
> > Signed-off-by: raghav.s <raghav.s@samsung.com>
> > ---
> >  arch/arm64/boot/dts/exynos/exynos8855.dtsi | 24
> > ++++++++++++++++++++++
> >  1 file changed, 24 insertions(+)
> 
> Please organize your patches in reasonable order. DTS is never in the middle,
> see submitting patches (both documents) and maintainer-soc profile.
> 
The thought was to add clks block wise and hence we see DTS coming in between but for the other blocks. 
e.g. patch-2 and 3 adds binding and driver for TOP and PERIC and this patch-4 adds DTS. 
And patch-5 and 6 adds binding and driver for PERIS and patch-7 adds DTS and so on.

Cover-letter should have explained this. 

Are you suggesting to re-order all the binding first followed by all blocks driver and then add a single DTS for all clock controller? 

Does current approach helps in review? 

> Best regards,
> Krzysztof

Re: [PATCH 04/13] arm64: dts: exynos8855: add cmu_top & cmu_peric clock DT nodes

[Krzysztof Kozlowski]

On 28/07/2026 14:23, Alim Akhtar wrote:
> Hi Krzysztof,
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: Tuesday, July 28, 2026 5:30 PM
>> To: raghav.s <raghav.s@samsung.com>; s.nawrocki@samsung.com;
>> cw00.choi@samsung.com; peter.griffin@linaro.org;
>> alim.akhtar@samsung.com; mturquette@baylibre.com; sboyd@kernel.org;
>> bmasney@redhat.com; robh@kernel.org; conor+dt@kernel.org
>> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org;
>> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
>> kernel@vger.kernel.org; hajun.sung@samsung.com;
>> is.gandhi@samsung.com; ts.amit@samsung.com;
>> pokala.reddy@samsung.com
>> Subject: Re: [PATCH 04/13] arm64: dts: exynos8855: add cmu_top &
>> cmu_peric clock DT nodes
>>
>> On 28/07/2026 14:11, raghav.s wrote:
>>> Add required dt node for cmu_top & cmu_peric block
>>>
>>> Signed-off-by: raghav.s <raghav.s@samsung.com>
>>> ---
>>>  arch/arm64/boot/dts/exynos/exynos8855.dtsi | 24
>>> ++++++++++++++++++++++
>>>  1 file changed, 24 insertions(+)
>>
>> Please organize your patches in reasonable order. DTS is never in the middle,
>> see submitting patches (both documents) and maintainer-soc profile.
>>
> The thought was to add clks block wise and hence we see DTS coming in between but for the other blocks. 
> e.g. patch-2 and 3 adds binding and driver for TOP and PERIC and this patch-4 adds DTS. 
> And patch-5 and 6 adds binding and driver for PERIS and patch-7 adds DTS and so on.
> 
> Cover-letter should have explained this. 
> 
> Are you suggesting to re-order all the binding first followed by all blocks driver and then add a single DTS for all clock controller? 
> 
> Does current approach helps in review? 

If you ask this, you did not read the docs.

Best regards,
Krzysztof

RE: [PATCH 04/13] arm64: dts: exynos8855: add cmu_top & cmu_peric clock DT nodes

[Alim Akhtar]

Hi Krzysztof

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Tuesday, July 28, 2026 5:55 PM
> To: Alim Akhtar <alim.akhtar@samsung.com>; 'raghav.s'
> <raghav.s@samsung.com>; s.nawrocki@samsung.com;
> cw00.choi@samsung.com; peter.griffin@linaro.org;
> mturquette@baylibre.com; sboyd@kernel.org; bmasney@redhat.com;
> robh@kernel.org; conor+dt@kernel.org
> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; hajun.sung@samsung.com;
> is.gandhi@samsung.com; ts.amit@samsung.com;
> pokala.reddy@samsung.com
> Subject: Re: [PATCH 04/13] arm64: dts: exynos8855: add cmu_top &
> cmu_peric clock DT nodes
> 
> On 28/07/2026 14:23, Alim Akhtar wrote:
> > Hi Krzysztof,
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzk@kernel.org>
> >> Sent: Tuesday, July 28, 2026 5:30 PM
> >> To: raghav.s <raghav.s@samsung.com>; s.nawrocki@samsung.com;
> >> cw00.choi@samsung.com; peter.griffin@linaro.org;
> >> alim.akhtar@samsung.com; mturquette@baylibre.com;
> sboyd@kernel.org;
> >> bmasney@redhat.com; robh@kernel.org; conor+dt@kernel.org
> >> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org;
> >> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> >> linux- kernel@vger.kernel.org; hajun.sung@samsung.com;
> >> is.gandhi@samsung.com; ts.amit@samsung.com;
> pokala.reddy@samsung.com
> >> Subject: Re: [PATCH 04/13] arm64: dts: exynos8855: add cmu_top &
> >> cmu_peric clock DT nodes
> >>
> >> On 28/07/2026 14:11, raghav.s wrote:
> >>> Add required dt node for cmu_top & cmu_peric block
> >>>
> >>> Signed-off-by: raghav.s <raghav.s@samsung.com>
> >>> ---
> >>>  arch/arm64/boot/dts/exynos/exynos8855.dtsi | 24
> >>> ++++++++++++++++++++++
> >>>  1 file changed, 24 insertions(+)
> >>
> >> Please organize your patches in reasonable order. DTS is never in the
> >> middle, see submitting patches (both documents) and maintainer-soc
> profile.
> >>
> > The thought was to add clks block wise and hence we see DTS coming in
> between but for the other blocks.
> > e.g. patch-2 and 3 adds binding and driver for TOP and PERIC and this patch-
> 4 adds DTS.
> > And patch-5 and 6 adds binding and driver for PERIS and patch-7 adds DTS
> and so on.
> >
> > Cover-letter should have explained this.
> >
> > Are you suggesting to re-order all the binding first followed by all blocks
> driver and then add a single DTS for all clock controller?
> >
> > Does current approach helps in review?
> 
> If you ask this, you did not read the docs.
> 
I think I just explain the reason why DTS came in-between for each block.
Probably this series should have been sent in multiple chunks, if not, then as you pointed and docs says DTS to be placed at the end of driver changes. Agreed. 
 
> Best regards,
> Krzysztof

[PATCH 05/13] dt-bindings: clock: exynos8855: add peris clock definitions

[raghav.s]

Add device tree clock binding definitions for CMU_PERIS

Signed-off-by: raghav.s <raghav.s@samsung.com>
---
 .../clock/samsung,exynos8855-clock.yaml       | 21 +++++++++++++++++++
 .../dt-bindings/clock/samsung,exynos8855.h    | 16 ++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml
index 073c19debd0d..62277c67fec1 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml
@@ -29,6 +29,7 @@ properties:
   compatible:
     enum:
       - samsung,exynos8855-cmu-peric
+      - samsung,exynos8855-cmu-peris
       - samsung,exynos8855-cmu-top
 
   clocks:
@@ -68,6 +69,26 @@ allOf:
             - const: mmc_card
             - const: ip
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos8855-cmu-peris
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (76.8 MHz)
+            - description: CMU_PERIS GIC clock (from CMU_TOP)
+            - description: CMU_PERIS NOC clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: gic
+            - const: bus
+
   - if:
       properties:
         compatible:
diff --git a/include/dt-bindings/clock/samsung,exynos8855.h b/include/dt-bindings/clock/samsung,exynos8855.h
index 14369b749fb2..9efaf3e330b4 100644
--- a/include/dt-bindings/clock/samsung,exynos8855.h
+++ b/include/dt-bindings/clock/samsung,exynos8855.h
@@ -50,6 +50,11 @@
 #define DOUT_SHARED4_DIV4		   38
 #define FOUT_MMC_PLL_DIV1                  39
 #define FOUT_MMC_PLL_DIV2                  40
+#define CLKCMU_MOUT_PERIS_GIC              41
+#define CLKCMU_MOUT_PERIS_NOC              42
+#define CLKCMU_DOUT_PERIS_GIC              43
+#define CLKCMU_DOUT_PERIS_NOC              44
+#define FOUT_MMC_PLL_CLKOUT_DIV2           45
 
 /* CMU_PERIC */
 #define CLK_MOUT_PERIC_IP_USER             1
@@ -79,4 +84,15 @@
 #define CLK_GOUT_UART_DBG_PERIC_IPCLKPORT_PCLK 25
 #define CLK_GOUT_USI_PERIC_IPCLKPORT_PCLK  26
 
+/* CMU_PERIS */
+#define CLK_MOUT_PERIS_NOC_USER            1
+#define CLK_MOUT_PERIS_GIC                 2
+#define CLK_MOUT_PERIS_GIC_USER            3
+#define CLK_DOUT_PERIS_NOCP                4
+#define CLK_DOUT_PERIS_OTP                 5
+#define CLK_GOUT_CMU_PERIS_IPCLKPORT_PCLK  6
+#define CLK_GOUT_SYSREG_PERIS_IPCLKPORT_PCLK 7
+#define CLK_GOUT_WDT0_PERIS_IPCLKPORT_PCLK   8
+#define CLK_GOUT_WDT1_PERIS_IPCLKPORT_PCLK   9
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS8855_H */
-- 
2.34.1

[PATCH 06/13] clk: samsung: exynos8855: add block peris clock support

[raghav.s]

Register compatible and cmu_info data to support clocks.
CMU_PERIS, this provides clocks for PERIS

Signed-off-by: raghav.s <raghav.s@samsung.com>
---
 drivers/clk/samsung/clk-exynos8855.c | 117 ++++++++++++++++++++++++++-
 1 file changed, 114 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c
index 93528f0077a4..40745f04be0c 100644
--- a/drivers/clk/samsung/clk-exynos8855.c
+++ b/drivers/clk/samsung/clk-exynos8855.c
@@ -17,8 +17,9 @@
 #include "clk-exynos-arm64.h"
 
 /* NOTE: Must be equal to the last clock ID increased by one */
-#define CLKS_NR_TOP                     (FOUT_MMC_PLL_DIV2 + 1)
+#define CLKS_NR_TOP                     (FOUT_MMC_PLL_CLKOUT_DIV2 + 1)
 #define CLKS_NR_PERIC                   (CLK_GOUT_USI_PERIC_IPCLKPORT_PCLK + 1)
+#define CLKS_NR_PERIS                   (CLK_GOUT_WDT1_PERIS_IPCLKPORT_PCLK + 1)
 
 /* ---- CMU_TOP --------------------------------------------------------- */
 
@@ -52,6 +53,10 @@
 #define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_NOC                 0x1878
 #define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_MMC_CARD            0x187c
 #define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_IP                  0x1880
+#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_GIC                 0x10c4
+#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_NOC                 0x10c8
+#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_GIC                 0x18c0
+#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_NOC                 0x18c4
 
 static const unsigned long top_clk_regs[] __initconst = {
 	PLL_LOCKTIME_PLL_MMC,
@@ -78,6 +83,10 @@ static const unsigned long top_clk_regs[] __initconst = {
 	CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_NOC,
 	CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_MMC_CARD,
 	CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_IP,
+	CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_GIC,
+	CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_NOC,
+	CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_GIC,
+	CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_NOC,
 };
 
 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
@@ -112,6 +121,14 @@ PNAME(mout_clkcmu_peric_mmc_card_p)       = { "oscclk", "dout_shared0_div2",
 						"dout_shared2_div2", "dout_shared2_div3",
 						"dout_shared3_div2", "dout_shared3_div3"};
 PNAME(mout_clkcmu_peric_ip_p)            = { "dout_shared0_div4", "dout_shared1_div4"};
+PNAME(mout_clkcmu_peris_gic_p)            = { "dout_shared0_div2", "dout_shared0_div3",
+						"dout_shared1_div2", "dout_shared1_div3",
+						"dout_shared1_div4", "dout_shared2_div2",
+						"fout_mmc_pll_clkout_div2", "dout_shared3_div3"};
+PNAME(mout_clkcmu_peris_noc_p)            = { "dout_shared0_div2", "dout_shared0_div3",
+						"dout_shared1_div2", "dout_shared1_div3",
+						"dout_shared1_div4", "dout_shared2_div2",
+						"fout_mmc_pll_div2", "dout_shared3_div3"};
 
 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
 	MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
@@ -132,6 +149,10 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
 	    mout_clkcmu_peric_mmc_card_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_MMC_CARD, 0, 3),
 	MUX(CLKCMU_MOUT_PERIC_IP, "mout_clkcmu_peric_ip",
 	    mout_clkcmu_peric_ip_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_IP, 0, 1),
+	MUX(CLKCMU_MOUT_PERIS_GIC, "mout_clkcmu_peris_gic",
+	    mout_clkcmu_peris_gic_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_GIC, 0, 3),
+	MUX(CLKCMU_MOUT_PERIS_NOC, "mout_clkcmu_peris_noc",
+	    mout_clkcmu_peris_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_NOC, 0, 3),
 };
 
 static const struct samsung_div_clock top_div_clks[] __initconst = {
@@ -144,7 +165,12 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
 	DIV(CLKCMU_DOUT_PERIC_IP, "dout_clkcmu_peric_ip",
 	    "mout_clkcmu_peric_ip", CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_IP,
 	    0, 4),
-
+	DIV(CLKCMU_DOUT_PERIS_GIC, "dout_clkcmu_peris_gic",
+	    "mout_clkcmu_peris_gic", CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_GIC,
+	    0, 4),
+	DIV(CLKCMU_DOUT_PERIS_NOC, "dout_clkcmu_peris_noc",
+	    "mout_clkcmu_peris_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_NOC,
+	    0, 4),
 };
 
 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
@@ -192,7 +218,8 @@ static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initcon
 		"mout_mmc_pll", 1, 1, 0),
 	FFACTOR(FOUT_MMC_PLL_DIV2, "fout_mmc_pll_div2",
 		"mout_mmc_pll", 1, 2, 0),
-
+	FFACTOR(FOUT_MMC_PLL_CLKOUT_DIV2, "fout_mmc_pll_clkout_div2",
+		"mout_mmc_pll", 1, 2, 0),
 };
 
 static const struct samsung_cmu_info top_cmu_info __initconst = {
@@ -382,6 +409,87 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = {
 	.clk_name               = "bus",
 };
 
+/* ---- CMU_PERIS --------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_PERIS (0x10030000) */
+#define CMU_PERIS_PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER           0x600
+#define CMU_PERIS_CLK_CON_MUX_CLK_PERIS_GIC                    0x1000
+#define CMU_PERIS_PLL_CON0_MUX_CLK_PERIS_GIC_USER              0x610
+#define CMU_PERIS_CLK_CON_DIV_CLK_PERIS_NOCP                   0x1800
+#define CMU_PERIS_CLK_CON_DIV_CLK_PERIS_OTP                    0x1804
+#define CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_CMU_PERIS_IPCLKPORT_PCLK     0x201c
+#define CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK  0x2040
+#define CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK          0x2048
+#define CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK          0x204c
+
+static const unsigned long peris_clk_regs[] __initconst = {
+	CMU_PERIS_PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER,
+	CMU_PERIS_CLK_CON_MUX_CLK_PERIS_GIC,
+	CMU_PERIS_PLL_CON0_MUX_CLK_PERIS_GIC_USER,
+	CMU_PERIS_CLK_CON_DIV_CLK_PERIS_NOCP,
+	CMU_PERIS_CLK_CON_DIV_CLK_PERIS_OTP,
+	CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_CMU_PERIS_IPCLKPORT_PCLK,
+	CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
+	CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK,
+	CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK,
+};
+
+/* List of parent clocks for Muxes in CMU_PERIS */
+PNAME(mout_clkcmu_peris_noc_user_p) = { "oscclk", "dout_clkcmu_peris_noc" };
+PNAME(mout_clk_peris_gic_p) = { "oscclk", "mout_clkcmu_peris_gic_user" };
+PNAME(mout_clkcmu_peris_gic_user_p) = { "oscclk", "dout_clkcmu_peris_gic" };
+
+static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_PERIS_NOC_USER, "mout_clkcmu_peris_noc_user",
+	    mout_clkcmu_peris_noc_user_p, CMU_PERIS_PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER, 4, 1),
+	MUX(CLK_MOUT_PERIS_GIC, "mout_clk_peris_gic",
+	    mout_clk_peris_gic_p, CMU_PERIS_CLK_CON_MUX_CLK_PERIS_GIC, 0, 1),
+	MUX(CLK_MOUT_PERIS_GIC_USER, "mout_clkcmu_peris_gic_user",
+	    mout_clkcmu_peris_gic_user_p, CMU_PERIS_PLL_CON0_MUX_CLK_PERIS_GIC_USER, 4, 1),
+};
+
+static const struct samsung_div_clock peris_div_clks[] __initconst = {
+	DIV(CLK_DOUT_PERIS_NOCP, "dout_clkcmu_peris_nocp",
+	    "mout_clkcmu_peris_noc_user", CMU_PERIS_CLK_CON_DIV_CLK_PERIS_NOCP,
+	    0, 4),
+	DIV(CLK_DOUT_PERIS_OTP, "dout_clkcmu_peris_otp",
+	    "oscclk", CMU_PERIS_CLK_CON_DIV_CLK_PERIS_OTP,
+	    0, 4),
+};
+
+static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
+	/* System will hang if this critical clock is gated */
+	GATE(CLK_GOUT_CMU_PERIS_IPCLKPORT_PCLK, "gout_cmu_peris_ipclkport_pclk",
+	     "dout_clkcmu_peris_nocp",
+	     CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_CMU_PERIS_IPCLKPORT_PCLK,
+	     21, CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_SYSREG_PERIS_IPCLKPORT_PCLK, "gout_sysreg_peris_ipclkport_pclk",
+	     "dout_clkcmu_peris_nocp",
+	     CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
+	     21, 0, 0),
+	GATE(CLK_GOUT_WDT0_PERIS_IPCLKPORT_PCLK, "gout_wdt0_peris_ipclkport_pclk",
+	     "dout_clkcmu_peris_nocp",
+	     CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK,
+	     21, 0, 0),
+	GATE(CLK_GOUT_WDT1_PERIS_IPCLKPORT_PCLK, "gout_wdt1_peris_ipclkport_pclk",
+	     "dout_clkcmu_peris_nocp",
+	     CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK,
+	     21, 0, 0),
+};
+
+static const struct samsung_cmu_info peris_cmu_info __initconst = {
+	.mux_clks               = peris_mux_clks,
+	.nr_mux_clks            = ARRAY_SIZE(peris_mux_clks),
+	.div_clks               = peris_div_clks,
+	.nr_div_clks            = ARRAY_SIZE(peris_div_clks),
+	.gate_clks              = peris_gate_clks,
+	.nr_gate_clks           = ARRAY_SIZE(peris_gate_clks),
+	.nr_clk_ids             = CLKS_NR_PERIS,
+	.clk_regs               = peris_clk_regs,
+	.nr_clk_regs            = ARRAY_SIZE(peris_clk_regs),
+	.clk_name               = "bus",
+};
+
 static int __init exynos8855_cmu_probe(struct platform_device *pdev)
 {
 	const struct samsung_cmu_info *info;
@@ -397,6 +505,9 @@ static const struct of_device_id exynos8855_cmu_of_match[] = {
 	{
 		.compatible = "samsung,exynos8855-cmu-peric",
 		.data = &peric_cmu_info,
+	}, {
+		.compatible = "samsung,exynos8855-cmu-peris",
+		.data = &peris_cmu_info,
 	}, {
 		.compatible = "samsung,exynos8855-cmu-top",
 		.data = &top_cmu_info,
-- 
2.34.1

Re: [PATCH 06/13] clk: samsung: exynos8855: add block peris clock support

[Krzysztof Kozlowski]

On 28/07/2026 14:11, raghav.s wrote:
> Register compatible and cmu_info data to support clocks.
> CMU_PERIS, this provides clocks for PERIS
> 
> Signed-off-by: raghav.s <raghav.s@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos8855.c | 117 ++++++++++++++++++++++++++-
>  1 file changed, 114 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c
> index 93528f0077a4..40745f04be0c 100644
> --- a/drivers/clk/samsung/clk-exynos8855.c
> +++ b/drivers/clk/samsung/clk-exynos8855.c
> @@ -17,8 +17,9 @@
>  #include "clk-exynos-arm64.h"
>  
>  /* NOTE: Must be equal to the last clock ID increased by one */
> -#define CLKS_NR_TOP                     (FOUT_MMC_PLL_DIV2 + 1)

You just added this line, so changing this is odd. Are your patches
correctly split?


Best regards,
Krzysztof

RE: [PATCH 06/13] clk: samsung: exynos8855: add block peris clock support

[Raghav Sharma]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Tuesday, July 28, 2026 5:31 PM
> To: raghav.s <raghav.s@samsung.com>; s.nawrocki@samsung.com;
> cw00.choi@samsung.com; peter.griffin@linaro.org;
> alim.akhtar@samsung.com; mturquette@baylibre.com; sboyd@kernel.org;
> bmasney@redhat.com; robh@kernel.org; conor+dt@kernel.org
> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; hajun.sung@samsung.com;
> is.gandhi@samsung.com; ts.amit@samsung.com;
> pokala.reddy@samsung.com
> Subject: Re: [PATCH 06/13] clk: samsung: exynos8855: add block peris clock
> support
> 
> On 28/07/2026 14:11, raghav.s wrote:
> > Register compatible and cmu_info data to support clocks.
> > CMU_PERIS, this provides clocks for PERIS
> >
> > Signed-off-by: raghav.s <raghav.s@samsung.com>
> > ---
> >  drivers/clk/samsung/clk-exynos8855.c | 117
> > ++++++++++++++++++++++++++-
> >  1 file changed, 114 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/clk/samsung/clk-exynos8855.c
> > b/drivers/clk/samsung/clk-exynos8855.c
> > index 93528f0077a4..40745f04be0c 100644
> > --- a/drivers/clk/samsung/clk-exynos8855.c
> > +++ b/drivers/clk/samsung/clk-exynos8855.c
> > @@ -17,8 +17,9 @@
> >  #include "clk-exynos-arm64.h"
> >
> >  /* NOTE: Must be equal to the last clock ID increased by one */
> > -#define CLKS_NR_TOP                     (FOUT_MMC_PLL_DIV2 + 1)
> 
> You just added this line, so changing this is odd. Are your patches correctly
> split?
> 
> 
> Best regards,
> Krzysztof

Hi Krzysztof
We will re-check the patches' order
Thanks for your reply
Regards
Raghav

[PATCH 07/13] arm64: dts: exynos8855: add cmu_peris clock DT nodes

[raghav.s]

Add required dt node for cmu_peris block

Signed-off-by: raghav.s <raghav.s@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos8855.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
index 0053730b3e01..a8f5ff0a7f1a 100644
--- a/arch/arm64/boot/dts/exynos/exynos8855.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
@@ -141,6 +141,19 @@ soc: soc@0 {
 		#size-cells = <1>;
 		ranges = <0x0 0x0 0x0 0x20000000>;
 
+		cmu_peris: clock-controller@10030000 {
+			compatible = "samsung,exynos8855-cmu-peris";
+			reg = <0x10030000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLKCMU_DOUT_PERIS_GIC>,
+				 <&cmu_top CLKCMU_DOUT_PERIS_NOC>;
+			clock-names = "oscclk",
+				      "gic",
+				      "bus";
+		};
+
 		gic: interrupt-controller@10200000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;
-- 
2.34.1

[PATCH 08/13] dt-bindings: clock: exynos8855: add hsi clock definitions

[raghav.s]

Add device tree clock binding definitions for CMU_HSI

Signed-off-by: raghav.s <raghav.s@samsung.com>
---
 .../clock/samsung,exynos8855-clock.yaml       | 21 +++++++++++++++++++
 .../dt-bindings/clock/samsung,exynos8855.h    | 10 +++++++++
 2 files changed, 31 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml
index 62277c67fec1..e97b65f8be5f 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml
@@ -28,6 +28,7 @@ description: |
 properties:
   compatible:
     enum:
+      - samsung,exynos8855-cmu-hsi
       - samsung,exynos8855-cmu-peric
       - samsung,exynos8855-cmu-peris
       - samsung,exynos8855-cmu-top
@@ -47,6 +48,26 @@ properties:
     maxItems: 1
 
 allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos8855-cmu-hsi
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (76.8 MHz)
+            - description: CMU_HSI NOC clock (from CMU_TOP)
+            - description: CMU_HSI UFS_EMBD clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+            - const: ufs_embd
+
   - if:
       properties:
         compatible:
diff --git a/include/dt-bindings/clock/samsung,exynos8855.h b/include/dt-bindings/clock/samsung,exynos8855.h
index 9efaf3e330b4..44484a9d67f5 100644
--- a/include/dt-bindings/clock/samsung,exynos8855.h
+++ b/include/dt-bindings/clock/samsung,exynos8855.h
@@ -55,6 +55,10 @@
 #define CLKCMU_DOUT_PERIS_GIC              43
 #define CLKCMU_DOUT_PERIS_NOC              44
 #define FOUT_MMC_PLL_CLKOUT_DIV2           45
+#define CLKCMU_MOUT_HSI_NOC                46
+#define CLKCMU_MOUT_HSI_UFS_EMBD           47
+#define CLKCMU_DOUT_HSI_NOC                48
+#define CLKCMU_DOUT_HSI_UFS_EMBD           49
 
 /* CMU_PERIC */
 #define CLK_MOUT_PERIC_IP_USER             1
@@ -95,4 +99,10 @@
 #define CLK_GOUT_WDT0_PERIS_IPCLKPORT_PCLK   8
 #define CLK_GOUT_WDT1_PERIS_IPCLKPORT_PCLK   9
 
+/* CMU_HSI */
+#define CLK_MOUT_HSI_NOC_USER              1
+#define CLK_MOUT_HSI_UFS_EMBD_USER         2
+#define CLK_GOUT_CMU_HSI_IPCLKPORT_PCLK    3
+#define CLK_GOUT_SYSREG_HSI_IPCLKPORT_PCLK 4
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS8855_H */
-- 
2.34.1

[PATCH 09/13] clk: samsung: exynos8855: add block hsi clock support

[raghav.s]

Register compatible and cmu_info data to support clocks.
CMU_HSI, this provides clocks for HSI

Signed-off-by: raghav.s <raghav.s@samsung.com>
---
 drivers/clk/samsung/clk-exynos8855.c | 81 +++++++++++++++++++++++++++-
 1 file changed, 80 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c
index 40745f04be0c..293f461f26cf 100644
--- a/drivers/clk/samsung/clk-exynos8855.c
+++ b/drivers/clk/samsung/clk-exynos8855.c
@@ -17,9 +17,10 @@
 #include "clk-exynos-arm64.h"
 
 /* NOTE: Must be equal to the last clock ID increased by one */
-#define CLKS_NR_TOP                     (FOUT_MMC_PLL_CLKOUT_DIV2 + 1)
+#define CLKS_NR_TOP                     (CLKCMU_DOUT_HSI_UFS_EMBD + 1)
 #define CLKS_NR_PERIC                   (CLK_GOUT_USI_PERIC_IPCLKPORT_PCLK + 1)
 #define CLKS_NR_PERIS                   (CLK_GOUT_WDT1_PERIS_IPCLKPORT_PCLK + 1)
+#define CLKS_NR_HSI                     (CLK_GOUT_SYSREG_HSI_IPCLKPORT_PCLK  + 1)
 
 /* ---- CMU_TOP --------------------------------------------------------- */
 
@@ -57,6 +58,10 @@
 #define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_NOC                 0x10c8
 #define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_GIC                 0x18c0
 #define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_NOC                 0x18c4
+#define CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_NOC                   0x1050
+#define CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_UFS_EMBD              0x1054
+#define CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_NOC                   0x1850
+#define CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD              0x1854
 
 static const unsigned long top_clk_regs[] __initconst = {
 	PLL_LOCKTIME_PLL_MMC,
@@ -87,6 +92,10 @@ static const unsigned long top_clk_regs[] __initconst = {
 	CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_NOC,
 	CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_GIC,
 	CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_NOC,
+	CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_NOC,
+	CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_UFS_EMBD,
+	CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_NOC,
+	CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD,
 };
 
 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
@@ -129,6 +138,14 @@ PNAME(mout_clkcmu_peris_noc_p)            = { "dout_shared0_div2", "dout_shared0
 						"dout_shared1_div2", "dout_shared1_div3",
 						"dout_shared1_div4", "dout_shared2_div2",
 						"fout_mmc_pll_div2", "dout_shared3_div3"};
+PNAME(mout_clkcmu_hsi_noc_p)            = { "dout_shared0_div2", "dout_shared0_div3",
+						"dout_shared1_div2", "dout_shared1_div3",
+						"dout_shared2_div2", "dout_shared2_div3",
+						"dout_shared3_div2", "dout_shared3_div3"};
+PNAME(mout_clkcmu_hsi_ufs_embd_p)            = { "dout_shared0_div2", "dout_shared0_div3",
+						"dout_shared1_div2", "dout_shared1_div3",
+						"dout_shared2_div2", "dout_shared2_div3",
+						"dout_shared3_div2", "dout_shared3_div3"};
 
 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
 	MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
@@ -153,6 +170,10 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
 	    mout_clkcmu_peris_gic_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_GIC, 0, 3),
 	MUX(CLKCMU_MOUT_PERIS_NOC, "mout_clkcmu_peris_noc",
 	    mout_clkcmu_peris_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_NOC, 0, 3),
+	MUX(CLKCMU_MOUT_HSI_NOC, "mout_clkcmu_hsi_noc",
+	    mout_clkcmu_hsi_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_NOC, 0, 3),
+	MUX(CLKCMU_MOUT_HSI_UFS_EMBD, "mout_clkcmu_hsi_ufs_embd",
+	    mout_clkcmu_hsi_ufs_embd_p, CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_UFS_EMBD, 0, 3),
 };
 
 static const struct samsung_div_clock top_div_clks[] __initconst = {
@@ -171,6 +192,12 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
 	DIV(CLKCMU_DOUT_PERIS_NOC, "dout_clkcmu_peris_noc",
 	    "mout_clkcmu_peris_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_NOC,
 	    0, 4),
+	DIV(CLKCMU_DOUT_HSI_NOC, "dout_clkcmu_hsi_noc",
+	    "mout_clkcmu_hsi_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_NOC,
+	    0, 4),
+	DIV(CLKCMU_DOUT_HSI_UFS_EMBD, "dout_clkcmu_hsi_ufs_embd",
+	    "mout_clkcmu_hsi_ufs_embd", CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD,
+	    0, 4),
 };
 
 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
@@ -490,6 +517,55 @@ static const struct samsung_cmu_info peris_cmu_info __initconst = {
 	.clk_name               = "bus",
 };
 
+/* ---- CMU_HSI --------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_HSI (0x17000000) */
+#define CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_NOC_USER               0x600
+#define CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER          0x610
+#define CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_CMU_HSI_IPCLKPORT_PCLK        0x2000
+#define CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK     0x2038
+
+static const unsigned long hsi_clk_regs[] __initconst = {
+	CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_NOC_USER,
+	CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER,
+	CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_CMU_HSI_IPCLKPORT_PCLK,
+	CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK,
+};
+
+/* List of parent clocks for Muxes in CMU_HSI */
+PNAME(mout_clkcmu_hsi_noc_user_p) = { "oscclk", "dout_clkcmu_hsi_noc" };
+PNAME(mout_clkcmu_hsi_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_hsi_ufs_embd" };
+
+static const struct samsung_mux_clock hsi_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_HSI_NOC_USER, "mout_clkcmu_hsi_noc_user",
+	    mout_clkcmu_hsi_noc_user_p, CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_NOC_USER, 4, 1),
+	MUX(CLK_MOUT_HSI_UFS_EMBD_USER, "mout_clkcmu_hsi_ufs_embd_user",
+	    mout_clkcmu_hsi_ufs_embd_user_p, CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER, 4, 1),
+};
+
+static const struct samsung_gate_clock hsi_gate_clks[] __initconst = {
+	/* System will hang if this critical clock is gated */
+	GATE(CLK_GOUT_CMU_HSI_IPCLKPORT_PCLK, "gout_cmu_hsi_ipclkport_pclk",
+	     "mout_clkcmu_hsi_noc_user",
+	     CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_CMU_HSI_IPCLKPORT_PCLK,
+	     21, CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_SYSREG_HSI_IPCLKPORT_PCLK, "gout_sysreg_hsi_ipclkport_pclk",
+	     "mout_clkcmu_hsi_noc_user",
+	     CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK,
+	     21, 0, 0),
+};
+
+static const struct samsung_cmu_info hsi_cmu_info __initconst = {
+	.mux_clks               = hsi_mux_clks,
+	.nr_mux_clks            = ARRAY_SIZE(hsi_mux_clks),
+	.gate_clks              = hsi_gate_clks,
+	.nr_gate_clks           = ARRAY_SIZE(hsi_gate_clks),
+	.nr_clk_ids             = CLKS_NR_HSI,
+	.clk_regs               = hsi_clk_regs,
+	.nr_clk_regs            = ARRAY_SIZE(hsi_clk_regs),
+	.clk_name               = "bus",
+};
+
 static int __init exynos8855_cmu_probe(struct platform_device *pdev)
 {
 	const struct samsung_cmu_info *info;
@@ -503,6 +579,9 @@ static int __init exynos8855_cmu_probe(struct platform_device *pdev)
 
 static const struct of_device_id exynos8855_cmu_of_match[] = {
 	{
+		.compatible = "samsung,exynos8855-cmu-hsi",
+		.data = &hsi_cmu_info,
+	}, {
 		.compatible = "samsung,exynos8855-cmu-peric",
 		.data = &peric_cmu_info,
 	}, {
-- 
2.34.1

[PATCH 10/13] arm64: dts: exynos8855: add cmu_hsi clock DT nodes

[raghav.s]

Add required dt node for cmu_hsi block

Signed-off-by: raghav.s <raghav.s@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos8855.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
index a8f5ff0a7f1a..ad66eda62e31 100644
--- a/arch/arm64/boot/dts/exynos/exynos8855.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
@@ -220,6 +220,19 @@ pinctrl_pericmmc: pinctrl@154f0000 {
 			interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		cmu_hsi: clock-controller@17000000 {
+			compatible = "samsung,exynos8855-cmu-hsi";
+			reg = <0x17000000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLKCMU_DOUT_HSI_NOC>,
+				 <&cmu_top CLKCMU_DOUT_HSI_UFS_EMBD>;
+			clock-names = "oscclk",
+				      "bus",
+				      "ufs_embd";
+		};
+
 		pinctrl_hsi_ufs: pinctrl@17040000 {
 			compatible = "samsung,exynos8855-pinctrl";
 			reg = <0x17040000 0x1000>;
-- 
2.34.1

[PATCH 11/13] dt-bindings: clock: exynos8855: add usb clock definitions

[raghav.s]

Add device tree clock binding definitions for CMU_USB

Signed-off-by: raghav.s <raghav.s@samsung.com>
---
 .../clock/samsung,exynos8855-clock.yaml       | 21 +++++++++++++++++++
 .../dt-bindings/clock/samsung,exynos8855.h    | 12 +++++++++++
 2 files changed, 33 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml
index e97b65f8be5f..736d3429bf4c 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml
@@ -32,6 +32,7 @@ properties:
       - samsung,exynos8855-cmu-peric
       - samsung,exynos8855-cmu-peris
       - samsung,exynos8855-cmu-top
+      - samsung,exynos8855-cmu-usb
 
   clocks:
     minItems: 1
@@ -126,6 +127,26 @@ allOf:
           items:
             - const: oscclk
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos8855-cmu-usb
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (76.8 MHz)
+            - description: CMU_USB NOC clock (from CMU_TOP)
+            - description: CMU_USB USB20DRD clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+            - const: usb20drd
+
 required:
   - compatible
   - "#clock-cells"
diff --git a/include/dt-bindings/clock/samsung,exynos8855.h b/include/dt-bindings/clock/samsung,exynos8855.h
index 44484a9d67f5..bf76464298d2 100644
--- a/include/dt-bindings/clock/samsung,exynos8855.h
+++ b/include/dt-bindings/clock/samsung,exynos8855.h
@@ -59,6 +59,10 @@
 #define CLKCMU_MOUT_HSI_UFS_EMBD           47
 #define CLKCMU_DOUT_HSI_NOC                48
 #define CLKCMU_DOUT_HSI_UFS_EMBD           49
+#define CLKCMU_MOUT_USB_NOC                50
+#define CLKCMU_MOUT_USB_USB20DRD           51
+#define CLKCMU_DOUT_USB_NOC                52
+#define CLKCMU_DOUT_USB_USB20DRD           53
 
 /* CMU_PERIC */
 #define CLK_MOUT_PERIC_IP_USER             1
@@ -105,4 +109,12 @@
 #define CLK_GOUT_CMU_HSI_IPCLKPORT_PCLK    3
 #define CLK_GOUT_SYSREG_HSI_IPCLKPORT_PCLK 4
 
+/* CMU_USB */
+#define CLK_MOUT_USB_NOC_USER              1
+#define CLK_MOUT_USB_USB20DRD              2
+#define CLK_MOUT_USB_USB20DRD_USER         3
+#define CLK_DOUT_USB_NOC_DIV3              4
+#define CLK_GOUT_CMU_USB_IPCLKPORT_PCLK    5
+#define CLK_GOUT_SYSREG_USB_IPCLKPORT_PCLK 6
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS8855_H */
-- 
2.34.1

[PATCH 12/13] clk: samsung: exynos8855: add block usb clock support

[raghav.s]

Register compatible and cmu_info data to support clocks.
CMU_USB, this provides clocks for USB

Signed-off-by: raghav.s <raghav.s@samsung.com>
---
 drivers/clk/samsung/clk-exynos8855.c | 102 ++++++++++++++++++++++++++-
 1 file changed, 101 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c
index 293f461f26cf..7865f38a0174 100644
--- a/drivers/clk/samsung/clk-exynos8855.c
+++ b/drivers/clk/samsung/clk-exynos8855.c
@@ -17,10 +17,11 @@
 #include "clk-exynos-arm64.h"
 
 /* NOTE: Must be equal to the last clock ID increased by one */
-#define CLKS_NR_TOP                     (CLKCMU_DOUT_HSI_UFS_EMBD + 1)
+#define CLKS_NR_TOP                     (CLKCMU_DOUT_USB_USB20DRD + 1)
 #define CLKS_NR_PERIC                   (CLK_GOUT_USI_PERIC_IPCLKPORT_PCLK + 1)
 #define CLKS_NR_PERIS                   (CLK_GOUT_WDT1_PERIS_IPCLKPORT_PCLK + 1)
 #define CLKS_NR_HSI                     (CLK_GOUT_SYSREG_HSI_IPCLKPORT_PCLK  + 1)
+#define CLKS_NR_USB                     (CLK_GOUT_SYSREG_USB_IPCLKPORT_PCLK + 1)
 
 /* ---- CMU_TOP --------------------------------------------------------- */
 
@@ -62,6 +63,10 @@
 #define CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_UFS_EMBD              0x1054
 #define CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_NOC                   0x1850
 #define CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD              0x1854
+#define CMU_TOP_CLK_CON_MUX_CLKCMU_USB_NOC                   0x1088
+#define CMU_TOP_CLK_CON_MUX_CLKCMU_USB_USB20DRD              0x108c
+#define CMU_TOP_CLK_CON_DIV_CLKCMU_USB_NOC                   0x1888
+#define CMU_TOP_CLK_CON_DIV_CLKCMU_USB_USB20DRD              0x188c
 
 static const unsigned long top_clk_regs[] __initconst = {
 	PLL_LOCKTIME_PLL_MMC,
@@ -96,6 +101,10 @@ static const unsigned long top_clk_regs[] __initconst = {
 	CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_UFS_EMBD,
 	CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_NOC,
 	CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD,
+	CMU_TOP_CLK_CON_MUX_CLKCMU_USB_NOC,
+	CMU_TOP_CLK_CON_MUX_CLKCMU_USB_USB20DRD,
+	CMU_TOP_CLK_CON_DIV_CLKCMU_USB_NOC,
+	CMU_TOP_CLK_CON_DIV_CLKCMU_USB_USB20DRD,
 };
 
 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
@@ -146,6 +155,14 @@ PNAME(mout_clkcmu_hsi_ufs_embd_p)            = { "dout_shared0_div2", "dout_shar
 						"dout_shared1_div2", "dout_shared1_div3",
 						"dout_shared2_div2", "dout_shared2_div3",
 						"dout_shared3_div2", "dout_shared3_div3"};
+PNAME(mout_clkcmu_usb_noc_p)            = { "dout_shared0_div2", "dout_shared0_div3",
+						"dout_shared0_div4", "dout_shared1_div3",
+						"dout_shared2_div2", "dout_shared2_div3",
+						"dout_shared3_div2", "dout_shared3_div3"};
+PNAME(mout_clkcmu_usb_usb20drd_p)            = { "dout_shared0_div2", "dout_shared0_div3",
+						"dout_shared0_div4", "dout_shared1_div3",
+						"dout_shared2_div2", "dout_shared2_div3",
+						"dout_shared3_div2", "dout_shared3_div3"};
 
 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
 	MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
@@ -174,6 +191,10 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
 	    mout_clkcmu_hsi_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_NOC, 0, 3),
 	MUX(CLKCMU_MOUT_HSI_UFS_EMBD, "mout_clkcmu_hsi_ufs_embd",
 	    mout_clkcmu_hsi_ufs_embd_p, CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_UFS_EMBD, 0, 3),
+	MUX(CLKCMU_MOUT_USB_NOC, "mout_clkcmu_usb_noc",
+	    mout_clkcmu_usb_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_USB_NOC, 0, 3),
+	MUX(CLKCMU_MOUT_USB_USB20DRD, "mout_clkcmu_usb_usb20drd",
+	    mout_clkcmu_usb_usb20drd_p, CMU_TOP_CLK_CON_MUX_CLKCMU_USB_USB20DRD, 0, 3),
 };
 
 static const struct samsung_div_clock top_div_clks[] __initconst = {
@@ -198,6 +219,12 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
 	DIV(CLKCMU_DOUT_HSI_UFS_EMBD, "dout_clkcmu_hsi_ufs_embd",
 	    "mout_clkcmu_hsi_ufs_embd", CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD,
 	    0, 4),
+	DIV(CLKCMU_DOUT_USB_NOC, "dout_clkcmu_usb_noc",
+	    "mout_clkcmu_usb_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_USB_NOC,
+	    0, 4),
+	DIV(CLKCMU_DOUT_USB_USB20DRD, "dout_clkcmu_usb_usb20drd",
+	    "mout_clkcmu_usb_usb20drd", CMU_TOP_CLK_CON_DIV_CLKCMU_USB_USB20DRD,
+	    0, 5),
 };
 
 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
@@ -249,6 +276,10 @@ static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initcon
 		"mout_mmc_pll", 1, 2, 0),
 };
 
+static const struct samsung_fixed_rate_clock top_fixed_rate_clks[] __initconst = {
+	FRATE(0, "oscclk_usb_link", NULL, 0, 19200000),
+};
+
 static const struct samsung_cmu_info top_cmu_info __initconst = {
 	.pll_clks		= top_pll_clks,
 	.nr_pll_clks		= ARRAY_SIZE(top_pll_clks),
@@ -258,6 +289,8 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
 	.nr_div_clks            = ARRAY_SIZE(top_div_clks),
 	.fixed_factor_clks	= top_fixed_factor_clks,
 	.nr_fixed_factor_clks	= ARRAY_SIZE(top_fixed_factor_clks),
+	.fixed_clks             = top_fixed_rate_clks,
+	.nr_fixed_clks          = ARRAY_SIZE(top_fixed_rate_clks),
 	.nr_clk_ids             = CLKS_NR_TOP,
 	.clk_regs               = top_clk_regs,
 	.nr_clk_regs            = ARRAY_SIZE(top_clk_regs),
@@ -566,6 +599,70 @@ static const struct samsung_cmu_info hsi_cmu_info __initconst = {
 	.clk_name               = "bus",
 };
 
+/* ---- CMU_USB --------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_USB (0x13000000) */
+#define CMU_USB_PLL_CON0_MUX_CLKCMU_USB_NOC_USER                   0x600
+#define CMU_USB_PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER              0x610
+#define CMU_USB_CLK_CON_MUX_CLK_USB_USB20DRD                       0x1000
+#define CMU_USB_CLK_CON_DIV_CLK_USB_NOC_DIV3                       0x1800
+#define CMU_USB_CLK_CON_GAT_BLK_USB_UID_CMU_USB_IPCLKPORT_PCLK     0x2000
+#define CMU_USB_CLK_CON_GAT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK  0x2030
+
+static const unsigned long usb_clk_regs[] __initconst = {
+	CMU_USB_PLL_CON0_MUX_CLKCMU_USB_NOC_USER,
+	CMU_USB_PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER,
+	CMU_USB_CLK_CON_MUX_CLK_USB_USB20DRD,
+	CMU_USB_CLK_CON_DIV_CLK_USB_NOC_DIV3,
+	CMU_USB_CLK_CON_GAT_BLK_USB_UID_CMU_USB_IPCLKPORT_PCLK,
+	CMU_USB_CLK_CON_GAT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK,
+};
+
+/* List of parent clocks for Muxes in CMU_USB */
+PNAME(mout_clkcmu_usb_noc_user_p) = { "oscclk", "dout_clkcmu_usb_noc" };
+PNAME(mout_clkcmu_usb_usb20drd_user_p) = { "oscclk", "dout_clkcmu_usb_usb20drd" };
+PNAME(mout_clk_usb_usb20drd_p) = { "oscclk_usb_link", "mout_clkcmu_usb_usb20drd_user" };
+
+static const struct samsung_mux_clock usb_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_USB_NOC_USER, "mout_clkcmu_usb_noc_user",
+	    mout_clkcmu_usb_noc_user_p, CMU_USB_PLL_CON0_MUX_CLKCMU_USB_NOC_USER, 4, 1),
+	MUX(CLK_MOUT_USB_USB20DRD_USER, "mout_clkcmu_usb_usb20drd_user",
+	    mout_clkcmu_usb_usb20drd_user_p, CMU_USB_PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER, 4, 1),
+	MUX(CLK_MOUT_USB_USB20DRD, "mout_clk_usb_usb20drd",
+	    mout_clk_usb_usb20drd_p, CMU_USB_CLK_CON_MUX_CLK_USB_USB20DRD, 0, 1),
+};
+
+static const struct samsung_div_clock usb_div_clks[] __initconst = {
+	DIV(CLK_DOUT_USB_NOC_DIV3, "dout_clkcmu_usb_noc_div3",
+	    "mout_clkcmu_usb_noc_user", CMU_USB_CLK_CON_DIV_CLK_USB_NOC_DIV3,
+	    0, 4),
+};
+
+static const struct samsung_gate_clock usb_gate_clks[] __initconst = {
+	/* System will hang if this critical clock is gated */
+	GATE(CLK_GOUT_CMU_USB_IPCLKPORT_PCLK, "gout_cmu_usb_ipclkport_pclk",
+	     "mout_clkcmu_usb_noc_user",
+	     CMU_USB_CLK_CON_GAT_BLK_USB_UID_CMU_USB_IPCLKPORT_PCLK,
+	     21, CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_SYSREG_USB_IPCLKPORT_PCLK, "gout_sysreg_usb_ipclkport_pclk",
+	     "mout_clkcmu_usb_noc_user",
+	     CMU_USB_CLK_CON_GAT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK,
+	     21, 0, 0),
+};
+
+static const struct samsung_cmu_info usb_cmu_info __initconst = {
+	.mux_clks               = usb_mux_clks,
+	.nr_mux_clks            = ARRAY_SIZE(usb_mux_clks),
+	.div_clks               = usb_div_clks,
+	.nr_div_clks            = ARRAY_SIZE(usb_div_clks),
+	.gate_clks              = usb_gate_clks,
+	.nr_gate_clks           = ARRAY_SIZE(usb_gate_clks),
+	.nr_clk_ids             = CLKS_NR_USB,
+	.clk_regs               = usb_clk_regs,
+	.nr_clk_regs            = ARRAY_SIZE(usb_clk_regs),
+	.clk_name               = "bus",
+};
+
 static int __init exynos8855_cmu_probe(struct platform_device *pdev)
 {
 	const struct samsung_cmu_info *info;
@@ -590,6 +687,9 @@ static const struct of_device_id exynos8855_cmu_of_match[] = {
 	}, {
 		.compatible = "samsung,exynos8855-cmu-top",
 		.data = &top_cmu_info,
+	}, {
+		.compatible = "samsung,exynos8855-cmu-usb",
+		.data = &usb_cmu_info,
 	},
 	{ }
 };
-- 
2.34.1

[PATCH 13/13] arm64: dts: exynos8855: add cmu_usb clock DT nodes

[raghav.s]

Add required dt node for cmu_usb block

Signed-off-by: raghav.s <raghav.s@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos8855.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
index ad66eda62e31..040ca9afe8e6 100644
--- a/arch/arm64/boot/dts/exynos/exynos8855.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
@@ -179,6 +179,19 @@ pinctrl_cmgp: pinctrl@12030000 {
 			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		cmu_usb: clock-controller@13000000 {
+			compatible = "samsung,exynos8855-cmu-usb";
+			reg = <0x13000000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLKCMU_DOUT_USB_NOC>,
+				 <&cmu_top CLKCMU_DOUT_USB_USB20DRD>;
+			clock-names = "oscclk",
+				      "bus",
+				      "usb20drd";
+		};
+
 		cmu_top: clock-controller@13900000 {
 			compatible = "samsung,exynos8855-cmu-top";
 			reg = <0x13900000 0x8000>;
-- 
2.34.1