[PATCH v3 0/2] EDAC/altera: two bug fixes

[PATCH v3 0/2] EDAC/altera: two bug fixes

[Matthew Gerlach]

This patch set contains two bug fixes for the Altera ECC manager.

Patch 1:
 - Fix bug testing the wrong structure member.

Patch 2:
 - Mask HW interrupts until handler registered.

Niravkumar L Rabara (2):
  EDAC/altera: fix cut and paste error
  EDAC/altera: Set DDR and SDMMC interrupt mask before registration

 drivers/edac/altera_edac.c | 9 +++++----
 drivers/edac/altera_edac.h | 2 ++
 2 files changed, 7 insertions(+), 4 deletions(-)

-- 
2.35.3

[PATCH v3 1/2] EDAC/altera: fix cut and paste error

[Matthew Gerlach]

From: Niravkumar L Rabara <niravkumar.l.rabara@altera.com>

Test correct structure member, ecc_cecnt_offset, before using it.

Fixes: 73bcc942f427 ("EDAC, altera: Add Arria10 EDAC support")
Cc: stable@kernel.org
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@altera.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
v3:
 - Use 12 digit HASH for Fixes: tag.

v2:
 - Improve commit message.
 - Add Fixes: and Cc: tags.
---
 drivers/edac/altera_edac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 3e971f902363..88d9d2f458ee 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -99,7 +99,7 @@ static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
 	if (status & priv->ecc_stat_ce_mask) {
 		regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
 			    &err_addr);
-		if (priv->ecc_uecnt_offset)
+		if (priv->ecc_cecnt_offset)
 			regmap_read(drvdata->mc_vbase,  priv->ecc_cecnt_offset,
 				    &err_count);
 		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
-- 
2.35.3

[PATCH v3 2/2] EDAC/altera: Set DDR and SDMMC interrupt mask before registration

[Matthew Gerlach]

From: Niravkumar L Rabara <niravkumar.l.rabara@altera.com>

Mask DDR and SDMMC in probe function to avoid spurious irq before
registration.  Removed invalid register write to system manager.

Fixes: 1166fde93d5b ("EDAC, altera: Add Arria10 ECC memory init functions")
Cc: stable@kernel.org
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@altera.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
v3:
 - Use 12 digit HASH for Fixes: tag.

v2:
 - Add Fixes: and Cc: tags.
---
 drivers/edac/altera_edac.c | 7 ++++---
 drivers/edac/altera_edac.h | 2 ++
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 88d9d2f458ee..dcd7008fe06b 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1005,9 +1005,6 @@ altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
 		}
 	}
 
-	/* Interrupt mode set to every SBERR */
-	regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
-		     ALTR_A10_ECC_INTMODE);
 	/* Enable ECC */
 	ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
 					ALTR_A10_ECC_CTRL_OFST));
@@ -2127,6 +2124,10 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
 		return PTR_ERR(edac->ecc_mgr_map);
 	}
 
+	/* Set irq mask for DDR SBE to avoid any pending irq before registration */
+	regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
+		     (A10_SYSMGR_ECC_INTMASK_SDMMCB | A10_SYSMGR_ECC_INTMASK_DDR0));
+
 	edac->irq_chip.name = pdev->dev.of_node->name;
 	edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
 	edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h
index 3727e72c8c2e..7248d24c4908 100644
--- a/drivers/edac/altera_edac.h
+++ b/drivers/edac/altera_edac.h
@@ -249,6 +249,8 @@ struct altr_sdram_mc_data {
 #define A10_SYSMGR_ECC_INTMASK_SET_OFST   0x94
 #define A10_SYSMGR_ECC_INTMASK_CLR_OFST   0x98
 #define A10_SYSMGR_ECC_INTMASK_OCRAM      BIT(1)
+#define A10_SYSMGR_ECC_INTMASK_SDMMCB     BIT(16)
+#define A10_SYSMGR_ECC_INTMASK_DDR0       BIT(17)
 
 #define A10_SYSMGR_ECC_INTSTAT_SERR_OFST  0x9C
 #define A10_SYSMGR_ECC_INTSTAT_DERR_OFST  0xA0
-- 
2.35.3

Re: [PATCH v3 1/2] EDAC/altera: fix cut and paste error

[Dinh Nguyen]

On 4/25/25 09:26, Matthew Gerlach wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@altera.com>
> 
> Test correct structure member, ecc_cecnt_offset, before using it.
> 
> Fixes: 73bcc942f427 ("EDAC, altera: Add Arria10 EDAC support")
> Cc: stable@kernel.org
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@altera.com>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
> ---
> v3:
>   - Use 12 digit HASH for Fixes: tag.
> 
> v2:
>   - Improve commit message.
>   - Add Fixes: and Cc: tags.
> ---

Acked-by: Dinh Nguyen <dinguyen@kernel.org>

Re: [PATCH v3 2/2] EDAC/altera: Set DDR and SDMMC interrupt mask before registration

[Dinh Nguyen]

On 4/25/25 09:26, Matthew Gerlach wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@altera.com>
> 
> Mask DDR and SDMMC in probe function to avoid spurious irq before
> registration.  Removed invalid register write to system manager.
> 
> Fixes: 1166fde93d5b ("EDAC, altera: Add Arria10 ECC memory init functions")
> Cc: stable@kernel.org
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@altera.com>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
> ---
> v3:
>   - Use 12 digit HASH for Fixes: tag.
> 
> v2:
>   - Add Fixes: and Cc: tags.

Acked-by: Dinh Nguyen <dinguyen@kernel.org>

Re: [PATCH v3 0/2] EDAC/altera: two bug fixes

[Borislav Petkov]

On Fri, Apr 25, 2025 at 07:26:38AM -0700, Matthew Gerlach wrote:
> This patch set contains two bug fixes for the Altera ECC manager.
> 
> Patch 1:
>  - Fix bug testing the wrong structure member.
> 
> Patch 2:
>  - Mask HW interrupts until handler registered.
> 
> Niravkumar L Rabara (2):
>   EDAC/altera: fix cut and paste error
>   EDAC/altera: Set DDR and SDMMC interrupt mask before registration
> 
>  drivers/edac/altera_edac.c | 9 +++++----
>  drivers/edac/altera_edac.h | 2 ++
>  2 files changed, 7 insertions(+), 4 deletions(-)

Applied, thanks.

-- 
Regards/Gruss,
    Boris.

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