From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: me@fromdisposition.org, Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Abel Vesa <abelvesa@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8350: Add CPU OPP tables with memory bandwidth
Date: Fri, 16 Oct 2026 10:45:59 +0200 [thread overview]
Message-ID: <0561f6b1-bb3d-4ce1-8034-46d36e320afc@oss.qualcomm.com> (raw)
In-Reply-To: <20261016-sm8350-cpu-bw-v1-2-044ac6dc9565@fromdisposition.org>
On 10/16/26 8:01 AM, Demeter Barna via B4 Relay wrote:
> From: Demeter Barna <me@fromdisposition.org>
>
> Without them nothing votes for the CPUs' memory paths and DDR stays at
> what other clients request. Vote for CPU-to-LLCC, LLCC-to-DDR and L3
> with the CPU frequency, as on SM8550 and SM8650.
>
> The frequencies are the cpufreq-hw LUT; the LLCC, DDR (LPDDR5) and L3
> levels follow the downstream memory latency tables.
>
> Assisted-by: LLM
> Signed-off-by: Demeter Barna <me@fromdisposition.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
prev parent reply other threads:[~2026-10-16 8:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-16 6:01 [PATCH 0/2] arm64: dts: qcom: sm8350: Scale L3 and memory bandwidth with the CPUs Demeter Barna via B4 Relay
2026-10-16 6:01 ` [PATCH 1/2] arm64: dts: qcom: sm8350: Add the EPSS L3 provider Demeter Barna via B4 Relay
2026-10-16 8:45 ` Konrad Dybcio
2026-10-16 6:01 ` [PATCH 2/2] arm64: dts: qcom: sm8350: Add CPU OPP tables with memory bandwidth Demeter Barna via B4 Relay
2026-10-16 8:45 ` Konrad Dybcio [this message]
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