* [PATCH v9 1/2] arm64: dts: qcom: Add Kalambo SoC
2026-10-16 10:30 [PATCH v9 0/2] arm64: dts: qcom: Add Kalambo SoC and CRD Gopikrishna Garmidi
@ 2026-10-16 10:30 ` Gopikrishna Garmidi
2026-10-16 10:30 ` [PATCH v9 2/2] arm64: dts: qcom: Add Kalambo CRD Gopikrishna Garmidi
2026-10-16 10:45 ` [PATCH v9 0/2] arm64: dts: qcom: Add Kalambo SoC and CRD Gopikrishna Garmidi
2 siblings, 0 replies; 4+ messages in thread
From: Gopikrishna Garmidi @ 2026-10-16 10:30 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, Pankaj Patil, Qiang Yu
Cc: Rajendra Nayak, linux-arm-msm, devicetree, linux-kernel,
Gopikrishna Garmidi, Konrad Dybcio, Abel Vesa
Introduce support for the Qualcomm Kalambo SoC. It is derived from Mahua
with CPU cluster 0 (cpu0-cpu5) removed, leaving only cluster 1
(cpu6-cpu11). The surviving cluster is re-added in the cpu-map as
cluster0, since the kernel stops scanning at the first missing clusterN
index. cpu6-cpu11 are reassigned to SCMI performance domain 0, as domain
1 is no longer present.
Kalambo uses PDP1 for SCMI transport. The tx shmem (lpri1) sits at
offset 0x200 within imem, pushing the tx region end to 0x380, so the
imem size is overridden accordingly. The rx shmem (lpri0) remains at
offset 0x0. The PDP mailbox registers are overridden to match the
Kalambo SCP firmware.
Kalambo's PDC input mux differs from Glymur. Pins 109 and 110 carry
tsens6 and tsens7 alarms, which are absent on Kalambo, and pins 134,
138, 156, 158, 172, 181 and 202 carry gp_irq_hvm inputs with nothing
wired to them instead of wakeup GPIOs. Override the PDC ranges to
leave those pins unmapped.
Add labels to the cpus and cpu-map nodes in glymur.dtsi to allow derived
SoCs to delete and redefine the cpu-map entirely.
Since Kalambo does not use CPU cluster0, disable bwmon_cluster0 to avoid
unnecessary traffic while retaining its shared cpu_bwmon_opp_table for
bwmon_cluster1.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 4 +-
arch/arm64/boot/dts/qcom/kalambo.dtsi | 123 ++++++++++++++++++++++++++++++++++
2 files changed, 125 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 65a398c0a992..c88215d0b265 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -35,7 +35,7 @@ / {
#address-cells = <2>;
#size-cells = <2>;
- cpus {
+ cpus: cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -273,7 +273,7 @@ cpu17: cpu@20500 {
#cooling-cells = <2>;
};
- cpu-map {
+ cpu_map: cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
diff --git a/arch/arm64/boot/dts/qcom/kalambo.dtsi b/arch/arm64/boot/dts/qcom/kalambo.dtsi
new file mode 100644
index 000000000000..868b924c4734
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/kalambo.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include "mahua.dtsi"
+
+/delete-node/ &cluster0_pd;
+/delete-node/ &cpu_map;
+/delete-node/ &cpu0;
+/delete-node/ &cpu1;
+/delete-node/ &cpu2;
+/delete-node/ &cpu3;
+/delete-node/ &cpu4;
+/delete-node/ &cpu5;
+/delete-node/ &cpu_pd0;
+/delete-node/ &cpu_pd1;
+/delete-node/ &cpu_pd2;
+/delete-node/ &cpu_pd3;
+/delete-node/ &cpu_pd4;
+/delete-node/ &cpu_pd5;
+/delete-node/ &cpu_scp_lpri1;
+
+&bwmon_cluster0 {
+ status = "disabled";
+};
+
+&cpu6 {
+ power-domains = <&cpu_pd6>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
+};
+
+&cpu7 {
+ power-domains = <&cpu_pd7>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
+};
+
+&cpu8 {
+ power-domains = <&cpu_pd8>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
+};
+
+&cpu9 {
+ power-domains = <&cpu_pd9>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
+};
+
+&cpu10 {
+ power-domains = <&cpu_pd10>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
+};
+
+&cpu11 {
+ power-domains = <&cpu_pd11>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
+};
+
+&cpus {
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+
+ core1 {
+ cpu = <&cpu7>;
+ };
+
+ core2 {
+ cpu = <&cpu8>;
+ };
+
+ core3 {
+ cpu = <&cpu9>;
+ };
+
+ core4 {
+ cpu = <&cpu10>;
+ };
+
+ core5 {
+ cpu = <&cpu11>;
+ };
+ };
+ };
+};
+
+&imem {
+ reg = <0x0 0x81e08600 0x0 0x380>;
+ ranges = <0x0 0x0 0x81e08600 0x380>;
+
+ cpu_scp_lpri1: scp-sram-section@200 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x200 0x180>;
+ };
+};
+
+&pdc {
+ qcom,pdc-ranges = <0 745 38>,
+ <40 785 11>,
+ <51 527 4>,
+ <57 533 10>,
+ <70 546 4>,
+ <75 551 18>,
+ <108 619 1>,
+ <111 622 19>,
+ <130 717 4>,
+ <135 722 3>,
+ <139 726 3>,
+ <142 251 5>,
+ <147 796 9>,
+ <157 806 1>,
+ <159 808 4>,
+ <171 4104 1>,
+ <173 4106 8>,
+ <182 4115 20>,
+ <203 4136 4>;
+};
+
+&pdp0_mbox {
+ reg = <0x0 0x17610000 0x0 0x8000>,
+ <0x0 0x1a980000 0x0 0x8000>;
+};
--
2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v9 2/2] arm64: dts: qcom: Add Kalambo CRD
2026-10-16 10:30 [PATCH v9 0/2] arm64: dts: qcom: Add Kalambo SoC and CRD Gopikrishna Garmidi
2026-10-16 10:30 ` [PATCH v9 1/2] arm64: dts: qcom: Add Kalambo SoC Gopikrishna Garmidi
@ 2026-10-16 10:30 ` Gopikrishna Garmidi
2026-10-16 10:45 ` [PATCH v9 0/2] arm64: dts: qcom: Add Kalambo SoC and CRD Gopikrishna Garmidi
2 siblings, 0 replies; 4+ messages in thread
From: Gopikrishna Garmidi @ 2026-10-16 10:30 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, Pankaj Patil, Qiang Yu
Cc: Rajendra Nayak, linux-arm-msm, devicetree, linux-kernel,
Gopikrishna Garmidi, Dmitry Baryshkov, Abel Vesa, Konrad Dybcio
Introduce support for the CRD based on the Qualcomm Kalambo SoC. Similar
to Mahua, it is pin-to-pin compatible with the Glymur CRD. It reuses the
common CRD board description and drops the PMIC nodes not present on this
design.
Kalambo uses the same QREF topology as Mahua through the qcom,mahua-tcsr
compatible TCSR block. Connect the QREF and refgen supply inputs to the
corresponding CRD LDOs so that the reference clocks for the PCIe and USB
PHYs can operate.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/kalambo-crd.dts | 37 ++++++++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 88230c4e00ea..b7f1e543a248 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -50,6 +50,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9650-rdp488.dtb
dtb-$(CONFIG_ARCH_QCOM) += kaanapali-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += kaanapali-qrd.dtb
+dtb-$(CONFIG_ARCH_QCOM) += kalambo-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb
lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo
diff --git a/arch/arm64/boot/dts/qcom/kalambo-crd.dts b/arch/arm64/boot/dts/qcom/kalambo-crd.dts
new file mode 100644
index 000000000000..9149cf6ad94b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/kalambo-crd.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include "kalambo.dtsi"
+#include "glymur-crd.dtsi"
+
+/delete-node/ &pmcx0102_d_e0;
+/delete-node/ &pmcx0102_d0_thermal;
+/delete-node/ &pmh0104_i_e0;
+/delete-node/ &pmh0104_i0_thermal;
+/delete-node/ &pmh0104_j_e0;
+/delete-node/ &pmh0104_j0_thermal;
+
+/ {
+ model = "Qualcomm Technologies, Inc. Kalambo CRD";
+ compatible = "qcom,kalambo-crd", "qcom,kalambo";
+};
+
+&tcsr {
+ vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1_0p83>;
+ vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1_0p83>;
+ vdda-qrefrpt2-0p9-supply = <&vreg_l2f_e1_0p83>;
+ vdda-qrefrpt3-0p9-supply = <&vreg_l1f_e1_0p82>;
+ vdda-qrefrpt4-0p9-supply = <&vreg_l2h_e0_0p72>;
+ vdda-qrefrpt5-0p9-supply = <&vreg_l2h_e0_0p72>;
+ vdda-qrefrx0-0p9-supply = <&vreg_l2f_e1_0p83>;
+ vdda-qrefrx1-0p9-supply = <&vreg_l2f_e1_0p83>;
+ vdda-qrefrx2-0p9-supply = <&vreg_l2f_e1_0p83>;
+ vdda-qrefrx3-0p9-supply = <&vreg_l2h_e0_0p72>;
+ vdda-qreftx1-0p9-supply = <&vreg_l1f_e1_0p82>;
+ vdda-refgen3-0p9-supply = <&vreg_l1f_e1_0p82>;
+ vdda-refgen3-1p2-supply = <&vreg_l4f_e1_1p08>;
+};
--
2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v9 0/2] arm64: dts: qcom: Add Kalambo SoC and CRD
2026-10-16 10:30 [PATCH v9 0/2] arm64: dts: qcom: Add Kalambo SoC and CRD Gopikrishna Garmidi
2026-10-16 10:30 ` [PATCH v9 1/2] arm64: dts: qcom: Add Kalambo SoC Gopikrishna Garmidi
2026-10-16 10:30 ` [PATCH v9 2/2] arm64: dts: qcom: Add Kalambo CRD Gopikrishna Garmidi
@ 2026-10-16 10:45 ` Gopikrishna Garmidi
2 siblings, 0 replies; 4+ messages in thread
From: Gopikrishna Garmidi @ 2026-10-16 10:45 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, Pankaj Patil, Qiang Yu
Cc: Rajendra Nayak, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio, Abel Vesa, Dmitry Baryshkov
On 10/16/2026 4:00 PM, Gopikrishna Garmidi wrote:
> Qualcomm Kalambo SoC is derived from Mahua SoC with CPU cluster 0
> removed, leaving only cluster 1 present.
>
> This series documents the board compatibles and adds the SoC and
> Compute Reference Device (CRD) device trees.
>
> ---
> Changes in v8:
> - Rebased on next-20261015.
> - Dropped the DT binding, SCM, and UBWC patches already landed in linux-next.
> - Retained the Kalambo SoC and CRD DTS patches.
> - Disabled the unused bwmon_cluster0 while keeping its shared OPP table for bwmon_cluster1.
> - Link to v7: https://patch.msgid.link/20260909-b4-kalambo-crd-v7-0-f5685804478a@oss.qualcomm.com
> [...]
Sorry, this series was mistakenly sent with a v9 prefix; it is intended
to be v8, so please disregard the v9 label.
Thanks,
Gopikrishna
^ permalink raw reply [flat|nested] 4+ messages in thread