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From: claudiu beznea <claudiu.beznea@tuxon.dev>
To: Robert Marko <robert.marko@sartura.hr>,
	ulfh@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, nicolas.ferre@microchip.com,
	alexandre.belloni@bootlin.com, adrian.hunter@intel.com,
	aubin.constans@microchip.com, ehristev@kernel.org,
	linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: luka.perkov@sartura.hr
Subject: Re: [PATCH v2 4/6] arm64: dts: microchip: lan969x: add SDMMC nodes
Date: Sat, 19 Sep 2026 17:14:18 +0300	[thread overview]
Message-ID: <09c057fe-bcaa-4e57-bedc-40dc1fcc770c@tuxon.dev> (raw)
In-Reply-To: <20260907132617.1198548-5-robert.marko@sartura.hr>

Hi, Roberto,

On 9/7/26 16:25, Robert Marko wrote:
> Add nodes for both SDMMC controllers. Connect their bus interface clock to
> the fabric clock and their core clock to the corresponding generated clock.
> 
> Configure SDMMC0 with a 100 MHz generated clock for 50 MHz eMMC DDR
> operation. Configure SDMMC1 with an exact 50 MHz generated clock so the
> integer base clock encoded in the SDHCI capabilities remains accurate and
> the identification clock does not exceed 400 kHz.
> 
> Keep both nodes ordered by unit address.
> 
> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
> ---
> Changes in v2:
> * Use the fabric clock for the SDMMC bus interface clock.
> * Configure SDMMC1 with an exact 50 MHz generated clock.
> * Move the SDMMC1 node to preserve unit-address ordering.
> * Explain the selected clock rates in the commit description.
> 
>   arch/arm64/boot/dts/microchip/lan9691.dtsi | 24 ++++++++++++++++++++++
>   1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/microchip/lan9691.dtsi b/arch/arm64/boot/dts/microchip/lan9691.dtsi
> index a8541c6a098d..5e330d5fab50 100644
> --- a/arch/arm64/boot/dts/microchip/lan9691.dtsi
> +++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi
> @@ -414,6 +414,18 @@ qspi0: spi@e0804000 {
>   			status = "disabled";
>   		};
>   
> +		sdmmc0: mmc@e0830000 {
> +			compatible = "microchip,lan9691-sdhci",
> +				     "microchip,sam9x60-sdhci";
> +			reg = <0xe0830000 0x00000300>;

s/0x00000300/0x300
> +			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&fabric_clk>, <&clks GCK_ID_SDMMC0>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&clks GCK_ID_SDMMC0>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +
>   		qspi2: spi@e0834000 {
>   			compatible = "microchip,lan9691-qspi";
>   			reg = <0xe0834000 0x00000100>,
> @@ -429,6 +441,18 @@ qspi2: spi@e0834000 {
>   			status = "disabled";
>   		};
>   
> +		sdmmc1: mmc@e0838000 {
> +			compatible = "microchip,lan9691-sdhci",
> +				     "microchip,sam9x60-sdhci";
> +			reg = <0xe0838000 0x00000300>;

Same here. I can adjust it while applying.

With that addressed:
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>


  parent reply	other threads:[~2026-09-19 14:14 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-07 13:25 [PATCH v2 0/6] mmc: sdhci-of-at91: add LAN969x support Robert Marko
2026-09-07 13:25 ` [PATCH v2 1/6] dt-bindings: mmc: atmel,sama5d2-sdhci: add LAN969x compatible Robert Marko
2026-09-07 13:25 ` [PATCH v2 2/6] mmc: sdhci-of-at91: add option to keep clocks enabled Robert Marko
2026-09-09 10:31   ` Adrian Hunter
2026-09-14 13:46   ` Aubin Constans
2026-09-15 11:31     ` Robert Marko
2026-09-18 16:02       ` Aubin Constans
2026-09-07 13:25 ` [PATCH v2 3/6] mmc: sdhci-of-at91: add LAN969x support Robert Marko
2026-09-09 10:36   ` Adrian Hunter
2026-09-07 13:25 ` [PATCH v2 4/6] arm64: dts: microchip: lan969x: add SDMMC nodes Robert Marko
2026-09-07 13:58   ` Aubin Constans
2026-09-19 14:14   ` claudiu beznea [this message]
2026-09-07 13:25 ` [PATCH v2 5/6] arm64: dts: microchip: ev23x71a: enable QSPI Robert Marko
2026-09-07 13:25 ` [PATCH v2 6/6] arm64: dts: microchip: ev23x71a: enable eMMC Robert Marko
2026-09-07 14:18   ` Aubin Constans
2026-09-19 14:18   ` claudiu beznea

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