[PATCH] bus: mhi: host: pci: Disable runtime PM for QDU100

[PATCH] bus: mhi: host: pci: Disable runtime PM for QDU100

[Vivek Pernamitta]

The QDU100 device does not support the MHI M3 state, necessitating the
disabling of runtime PM for this device. Since the PCIe core framework
enables runtime PM by default for all clients, it is essential to disable
runtime PM if the device does not support Low Power Mode (LPM).

Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
---
 drivers/bus/mhi/host/pci_generic.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c
index 03aa887952098661a488650053a357f883d1559b..a011fd2d48c57cf9d1aec74040153267a206d797 100644
--- a/drivers/bus/mhi/host/pci_generic.c
+++ b/drivers/bus/mhi/host/pci_generic.c
@@ -43,6 +43,7 @@
  * @mru_default: default MRU size for MBIM network packets
  * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead
  *		   of inband wake support (such as sdx24)
+ * @pm_disable: disables runtime PM (optional)
  */
 struct mhi_pci_dev_info {
 	const struct mhi_controller_config *config;
@@ -54,6 +55,7 @@ struct mhi_pci_dev_info {
 	unsigned int dma_data_width;
 	unsigned int mru_default;
 	bool sideband_wake;
+	bool pm_disable;
 };
 
 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \
@@ -295,6 +297,7 @@ static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = {
 	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
 	.dma_data_width = 32,
 	.sideband_wake = false,
+	.pm_disable = true,
 };
 
 static const struct mhi_channel_config mhi_qcom_sa8775p_channels[] = {
@@ -1270,6 +1273,13 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	/* start health check */
 	mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
 
+	/* Disable Runtime PM if device doesn't support MHI M3 state */
+	if (info->pm_disable) {
+		pm_runtime_disable(&pdev->dev);
+		pm_runtime_set_suspended(&pdev->dev);
+		return 0;
+	}
+
 	/* Only allow runtime-suspend if PME capable (for wakeup) */
 	if (pci_pme_capable(pdev, PCI_D3hot)) {
 		pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);

---
base-commit: 01c6df60d5d4ae00cd5c1648818744838bba7763
change-id: 20250414-vdev_next-20250411_pm_disable-53d5e1acd45e

Best regards,
-- 
Vivek Pernamitta <quic_vpernami@quicinc.com>

Re: [PATCH] bus: mhi: host: pci: Disable runtime PM for QDU100

[Manivannan Sadhasivam]

On Thu, Apr 17, 2025 at 10:00:38AM +0530, Veerabhadrarao Badiganti wrote:
> 
> On 4/14/2025 1:17 PM, Vivek Pernamitta wrote:
> > The QDU100 device does not support the MHI M3 state, necessitating the
> > disabling of runtime PM for this device. Since the PCIe core framework
> > enables runtime PM by default for all clients, it is essential to disable
> > runtime PM if the device does not support Low Power Mode (LPM).
> > 
> > Signed-off-by: Vivek Pernamitta<quic_vpernami@quicinc.com>
> > ---
> >   drivers/bus/mhi/host/pci_generic.c | 10 ++++++++++
> >   1 file changed, 10 insertions(+)
> > 
> > diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c
> > index 03aa887952098661a488650053a357f883d1559b..a011fd2d48c57cf9d1aec74040153267a206d797 100644
> > --- a/drivers/bus/mhi/host/pci_generic.c
> > +++ b/drivers/bus/mhi/host/pci_generic.c
> > @@ -43,6 +43,7 @@
> >    * @mru_default: default MRU size for MBIM network packets
> >    * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead
> >    *		   of inband wake support (such as sdx24)
> > + * @pm_disable: disables runtime PM (optional)
> >    */
> >   struct mhi_pci_dev_info {
> >   	const struct mhi_controller_config *config;
> > @@ -54,6 +55,7 @@ struct mhi_pci_dev_info {
> >   	unsigned int dma_data_width;
> >   	unsigned int mru_default;
> >   	bool sideband_wake;
> > +	bool pm_disable;
> >   };
> >   #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \
> > @@ -295,6 +297,7 @@ static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = {
> >   	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
> >   	.dma_data_width = 32,
> >   	.sideband_wake = false,
> > +	.pm_disable = true,
> 
> |no_m3|orno_|m3_support|would be more suitable than|pm_disable|

Yes!

But does the device not supporting M3 only or D3Hot also? If the former, then we
should prevent MHI host to enter/exit M3 state in mhi_pm_suspend/ mhi_pm_resume.
There is an incentive in allowing D3Hot if the device supports it.

Also, is there a way we could probe M3 support in the device so that we can
check it during runtime?

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH] bus: mhi: host: pci: Disable runtime PM for QDU100

[Vivek Pernamitta]

On 4/17/2025 11:37 AM, Manivannan Sadhasivam wrote:
> On Thu, Apr 17, 2025 at 10:00:38AM +0530, Veerabhadrarao Badiganti wrote:
>>
>> On 4/14/2025 1:17 PM, Vivek Pernamitta wrote:
>>> The QDU100 device does not support the MHI M3 state, necessitating the
>>> disabling of runtime PM for this device. Since the PCIe core framework
>>> enables runtime PM by default for all clients, it is essential to disable
>>> runtime PM if the device does not support Low Power Mode (LPM).
>>>
>>> Signed-off-by: Vivek Pernamitta<quic_vpernami@quicinc.com>
>>> ---
>>>    drivers/bus/mhi/host/pci_generic.c | 10 ++++++++++
>>>    1 file changed, 10 insertions(+)
>>>
>>> diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c
>>> index 03aa887952098661a488650053a357f883d1559b..a011fd2d48c57cf9d1aec74040153267a206d797 100644
>>> --- a/drivers/bus/mhi/host/pci_generic.c
>>> +++ b/drivers/bus/mhi/host/pci_generic.c
>>> @@ -43,6 +43,7 @@
>>>     * @mru_default: default MRU size for MBIM network packets
>>>     * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead
>>>     *		   of inband wake support (such as sdx24)
>>> + * @pm_disable: disables runtime PM (optional)
>>>     */
>>>    struct mhi_pci_dev_info {
>>>    	const struct mhi_controller_config *config;
>>> @@ -54,6 +55,7 @@ struct mhi_pci_dev_info {
>>>    	unsigned int dma_data_width;
>>>    	unsigned int mru_default;
>>>    	bool sideband_wake;
>>> +	bool pm_disable;
>>>    };
>>>    #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \
>>> @@ -295,6 +297,7 @@ static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = {
>>>    	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
>>>    	.dma_data_width = 32,
>>>    	.sideband_wake = false,
>>> +	.pm_disable = true,
>>
>> |no_m3|orno_|m3_support|would be more suitable than|pm_disable|
> 
> Yes!
> 
> But does the device not supporting M3 only or D3Hot also? If the former, then we
> should prevent MHI host to enter/exit M3 state in mhi_pm_suspend/ mhi_pm_resume.
> There is an incentive in allowing D3Hot if the device supports it.
> 
> Also, is there a way we could probe M3 support in the device so that we can
> check it during runtime?
> 
> - Mani
> 
In QDU100 device does not support M3 state, D3_hot will be supported. As 
QDU100 is an accelerator card which needs high-throughout, LPM needs to 
disabled here. So we are trying to disable runtime PM here, without M3 , 
D3_hot will not have effect in QDU100.
Also in MHI we don't have provision to check device M3 capability, so we 
are trying to disable runtime PM here.

Re: [PATCH] bus: mhi: host: pci: Disable runtime PM for QDU100

[Manivannan Sadhasivam]

On Fri, Apr 18, 2025 at 11:55:24AM +0530, Vivek Pernamitta wrote:
> 
> 
> On 4/17/2025 11:37 AM, Manivannan Sadhasivam wrote:
> > On Thu, Apr 17, 2025 at 10:00:38AM +0530, Veerabhadrarao Badiganti wrote:
> > > 
> > > On 4/14/2025 1:17 PM, Vivek Pernamitta wrote:
> > > > The QDU100 device does not support the MHI M3 state, necessitating the
> > > > disabling of runtime PM for this device. Since the PCIe core framework
> > > > enables runtime PM by default for all clients, it is essential to disable
> > > > runtime PM if the device does not support Low Power Mode (LPM).
> > > > 

Not true... See below.

> > > > Signed-off-by: Vivek Pernamitta<quic_vpernami@quicinc.com>
> > > > ---
> > > >    drivers/bus/mhi/host/pci_generic.c | 10 ++++++++++
> > > >    1 file changed, 10 insertions(+)
> > > > 
> > > > diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c
> > > > index 03aa887952098661a488650053a357f883d1559b..a011fd2d48c57cf9d1aec74040153267a206d797 100644
> > > > --- a/drivers/bus/mhi/host/pci_generic.c
> > > > +++ b/drivers/bus/mhi/host/pci_generic.c
> > > > @@ -43,6 +43,7 @@
> > > >     * @mru_default: default MRU size for MBIM network packets
> > > >     * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead
> > > >     *		   of inband wake support (such as sdx24)
> > > > + * @pm_disable: disables runtime PM (optional)
> > > >     */
> > > >    struct mhi_pci_dev_info {
> > > >    	const struct mhi_controller_config *config;
> > > > @@ -54,6 +55,7 @@ struct mhi_pci_dev_info {
> > > >    	unsigned int dma_data_width;
> > > >    	unsigned int mru_default;
> > > >    	bool sideband_wake;
> > > > +	bool pm_disable;
> > > >    };
> > > >    #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \
> > > > @@ -295,6 +297,7 @@ static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = {
> > > >    	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
> > > >    	.dma_data_width = 32,
> > > >    	.sideband_wake = false,
> > > > +	.pm_disable = true,
> > > 
> > > |no_m3|orno_|m3_support|would be more suitable than|pm_disable|
> > 
> > Yes!
> > 
> > But does the device not supporting M3 only or D3Hot also? If the former, then we
> > should prevent MHI host to enter/exit M3 state in mhi_pm_suspend/ mhi_pm_resume.
> > There is an incentive in allowing D3Hot if the device supports it.
> > 
> > Also, is there a way we could probe M3 support in the device so that we can
> > check it during runtime?
> > 
> > - Mani
> > 
> In QDU100 device does not support M3 state, D3_hot will be supported. As
> QDU100 is an accelerator card which needs high-throughout, LPM needs to
> disabled here. So we are trying to disable runtime PM here, without M3 ,
> D3_hot will not have effect in QDU100.
> Also in MHI we don't have provision to check device M3 capability, so we are
> trying to disable runtime PM here.
> 

Even though PCI core is enabling runtime PM for devices, it also prevents the
devices from getting suspended unless the drivers explicitly asks for it. So
this driver is using autosuspend feature to allow the devices to be suspended
if PME is supported from D3Hot.

If you want to prevent the device from getting runtime suspended, you should
just skip autosuspend.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH] bus: mhi: host: pci: Disable runtime PM for QDU100

[Vivek Pernamitta]

On 4/18/2025 2:06 PM, Manivannan Sadhasivam wrote:
> On Fri, Apr 18, 2025 at 11:55:24AM +0530, Vivek Pernamitta wrote:
>>
>>
>> On 4/17/2025 11:37 AM, Manivannan Sadhasivam wrote:
>>> On Thu, Apr 17, 2025 at 10:00:38AM +0530, Veerabhadrarao Badiganti wrote:
>>>>
>>>> On 4/14/2025 1:17 PM, Vivek Pernamitta wrote:
>>>>> The QDU100 device does not support the MHI M3 state, necessitating the
>>>>> disabling of runtime PM for this device. Since the PCIe core framework
>>>>> enables runtime PM by default for all clients, it is essential to disable
>>>>> runtime PM if the device does not support Low Power Mode (LPM).
>>>>>
> 
> Not true... See below.
> 
>>>>> Signed-off-by: Vivek Pernamitta<quic_vpernami@quicinc.com>
>>>>> ---
>>>>>     drivers/bus/mhi/host/pci_generic.c | 10 ++++++++++
>>>>>     1 file changed, 10 insertions(+)
>>>>>
>>>>> diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c
>>>>> index 03aa887952098661a488650053a357f883d1559b..a011fd2d48c57cf9d1aec74040153267a206d797 100644
>>>>> --- a/drivers/bus/mhi/host/pci_generic.c
>>>>> +++ b/drivers/bus/mhi/host/pci_generic.c
>>>>> @@ -43,6 +43,7 @@
>>>>>      * @mru_default: default MRU size for MBIM network packets
>>>>>      * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead
>>>>>      *		   of inband wake support (such as sdx24)
>>>>> + * @pm_disable: disables runtime PM (optional)
>>>>>      */
>>>>>     struct mhi_pci_dev_info {
>>>>>     	const struct mhi_controller_config *config;
>>>>> @@ -54,6 +55,7 @@ struct mhi_pci_dev_info {
>>>>>     	unsigned int dma_data_width;
>>>>>     	unsigned int mru_default;
>>>>>     	bool sideband_wake;
>>>>> +	bool pm_disable;
>>>>>     };
>>>>>     #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \
>>>>> @@ -295,6 +297,7 @@ static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = {
>>>>>     	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
>>>>>     	.dma_data_width = 32,
>>>>>     	.sideband_wake = false,
>>>>> +	.pm_disable = true,
>>>>
>>>> |no_m3|orno_|m3_support|would be more suitable than|pm_disable|
>>>
>>> Yes!
>>>
>>> But does the device not supporting M3 only or D3Hot also? If the former, then we
>>> should prevent MHI host to enter/exit M3 state in mhi_pm_suspend/ mhi_pm_resume.
>>> There is an incentive in allowing D3Hot if the device supports it.
>>>
>>> Also, is there a way we could probe M3 support in the device so that we can
>>> check it during runtime?
>>>
>>> - Mani
>>>
>> In QDU100 device does not support M3 state, D3_hot will be supported. As
>> QDU100 is an accelerator card which needs high-throughout, LPM needs to
>> disabled here. So we are trying to disable runtime PM here, without M3 ,
>> D3_hot will not have effect in QDU100.
>> Also in MHI we don't have provision to check device M3 capability, so we are
>> trying to disable runtime PM here.
>>
> 
> Even though PCI core is enabling runtime PM for devices, it also prevents the
> devices from getting suspended unless the drivers explicitly asks for it. So
> this driver is using autosuspend feature to allow the devices to be suspended
> if PME is supported from D3Hot.
> 
> If you want to prevent the device from getting runtime suspended, you should
> just skip autosuspend.
> 
> - Mani
> 
Thank you, I will upload new patchset accordingly.

Re: [PATCH] bus: mhi: host: pci: Disable runtime PM for QDU100

[Vivek Pernamitta]

On 4/18/2025 3:04 PM, Vivek Pernamitta wrote:
> 
> 
> On 4/18/2025 2:06 PM, Manivannan Sadhasivam wrote:
>> On Fri, Apr 18, 2025 at 11:55:24AM +0530, Vivek Pernamitta wrote:
>>>
>>>
>>> On 4/17/2025 11:37 AM, Manivannan Sadhasivam wrote:
>>>> On Thu, Apr 17, 2025 at 10:00:38AM +0530, Veerabhadrarao Badiganti 
>>>> wrote:
>>>>>
>>>>> On 4/14/2025 1:17 PM, Vivek Pernamitta wrote:
>>>>>> The QDU100 device does not support the MHI M3 state, necessitating 
>>>>>> the
>>>>>> disabling of runtime PM for this device. Since the PCIe core 
>>>>>> framework
>>>>>> enables runtime PM by default for all clients, it is essential to 
>>>>>> disable
>>>>>> runtime PM if the device does not support Low Power Mode (LPM).
>>>>>>
>>
>> Not true... See below.
>>
>>>>>> Signed-off-by: Vivek Pernamitta<quic_vpernami@quicinc.com>
>>>>>> ---
>>>>>>     drivers/bus/mhi/host/pci_generic.c | 10 ++++++++++
>>>>>>     1 file changed, 10 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/ 
>>>>>> host/pci_generic.c
>>>>>> index 
>>>>>> 03aa887952098661a488650053a357f883d1559b..a011fd2d48c57cf9d1aec74040153267a206d797 100644
>>>>>> --- a/drivers/bus/mhi/host/pci_generic.c
>>>>>> +++ b/drivers/bus/mhi/host/pci_generic.c
>>>>>> @@ -43,6 +43,7 @@
>>>>>>      * @mru_default: default MRU size for MBIM network packets
>>>>>>      * @sideband_wake: Devices using dedicated sideband GPIO for 
>>>>>> wakeup instead
>>>>>>      *           of inband wake support (such as sdx24)
>>>>>> + * @pm_disable: disables runtime PM (optional)
>>>>>>      */
>>>>>>     struct mhi_pci_dev_info {
>>>>>>         const struct mhi_controller_config *config;
>>>>>> @@ -54,6 +55,7 @@ struct mhi_pci_dev_info {
>>>>>>         unsigned int dma_data_width;
>>>>>>         unsigned int mru_default;
>>>>>>         bool sideband_wake;
>>>>>> +    bool pm_disable;
>>>>>>     };
>>>>>>     #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, 
>>>>>> ev_ring) \
>>>>>> @@ -295,6 +297,7 @@ static const struct mhi_pci_dev_info 
>>>>>> mhi_qcom_qdu100_info = {
>>>>>>         .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
>>>>>>         .dma_data_width = 32,
>>>>>>         .sideband_wake = false,
>>>>>> +    .pm_disable = true,
>>>>>
>>>>> |no_m3|orno_|m3_support|would be more suitable than|pm_disable|
>>>>
>>>> Yes!
>>>>
We named variable pm_disable because the M3 state is implicitly set 
during runtime PM suspend. Both are not needed and not fully supported 
for the QDU100 accelerator card, so we want to disable runtime suspend 
for it.
>>>> But does the device not supporting M3 only or D3Hot also? If the 
>>>> former, then we
>>>> should prevent MHI host to enter/exit M3 state in mhi_pm_suspend/ 
>>>> mhi_pm_resume.
>>>> There is an incentive in allowing D3Hot if the device supports it.
>>>>
>>>> Also, is there a way we could probe M3 support in the device so that 
>>>> we can
>>>> check it during runtime?
>>>>
>>>> - Mani
>>>>
>>> In QDU100 device does not support M3 state, D3_hot will be supported. As
>>> QDU100 is an accelerator card which needs high-throughout, LPM needs to
>>> disabled here. So we are trying to disable runtime PM here, without M3 ,
>>> D3_hot will not have effect in QDU100.
>>> Also in MHI we don't have provision to check device M3 capability, so 
>>> we are
>>> trying to disable runtime PM here.
>>>
>>
>> Even though PCI core is enabling runtime PM for devices, it also 
>> prevents the
>> devices from getting suspended unless the drivers explicitly asks for 
>> it. So
>> this driver is using autosuspend feature to allow the devices to be 
>> suspended
>> if PME is supported from D3Hot.
>>
>> If you want to prevent the device from getting runtime suspended, you 
>> should
>> just skip autosuspend.
>>
>> - Mani
>>
> Thank you, I will upload new patchset accordingly.
> 
> 

Re: [PATCH] bus: mhi: host: pci: Disable runtime PM for QDU100

[Manivannan Sadhasivam]

On Fri, Apr 18, 2025 at 03:40:48PM +0530, Vivek Pernamitta wrote:
> 
> 
> On 4/18/2025 3:04 PM, Vivek Pernamitta wrote:
> > 
> > 
> > On 4/18/2025 2:06 PM, Manivannan Sadhasivam wrote:
> > > On Fri, Apr 18, 2025 at 11:55:24AM +0530, Vivek Pernamitta wrote:
> > > > 
> > > > 
> > > > On 4/17/2025 11:37 AM, Manivannan Sadhasivam wrote:
> > > > > On Thu, Apr 17, 2025 at 10:00:38AM +0530, Veerabhadrarao
> > > > > Badiganti wrote:
> > > > > > 
> > > > > > On 4/14/2025 1:17 PM, Vivek Pernamitta wrote:
> > > > > > > The QDU100 device does not support the MHI M3 state,
> > > > > > > necessitating the
> > > > > > > disabling of runtime PM for this device. Since the
> > > > > > > PCIe core framework
> > > > > > > enables runtime PM by default for all clients, it is
> > > > > > > essential to disable
> > > > > > > runtime PM if the device does not support Low Power Mode (LPM).
> > > > > > > 
> > > 
> > > Not true... See below.
> > > 
> > > > > > > Signed-off-by: Vivek Pernamitta<quic_vpernami@quicinc.com>
> > > > > > > ---
> > > > > > >     drivers/bus/mhi/host/pci_generic.c | 10 ++++++++++
> > > > > > >     1 file changed, 10 insertions(+)
> > > > > > > 
> > > > > > > diff --git a/drivers/bus/mhi/host/pci_generic.c
> > > > > > > b/drivers/bus/mhi/ host/pci_generic.c
> > > > > > > index 03aa887952098661a488650053a357f883d1559b..a011fd2d48c57cf9d1aec74040153267a206d797
> > > > > > > 100644
> > > > > > > --- a/drivers/bus/mhi/host/pci_generic.c
> > > > > > > +++ b/drivers/bus/mhi/host/pci_generic.c
> > > > > > > @@ -43,6 +43,7 @@
> > > > > > >      * @mru_default: default MRU size for MBIM network packets
> > > > > > >      * @sideband_wake: Devices using dedicated
> > > > > > > sideband GPIO for wakeup instead
> > > > > > >      *           of inband wake support (such as sdx24)
> > > > > > > + * @pm_disable: disables runtime PM (optional)
> > > > > > >      */
> > > > > > >     struct mhi_pci_dev_info {
> > > > > > >         const struct mhi_controller_config *config;
> > > > > > > @@ -54,6 +55,7 @@ struct mhi_pci_dev_info {
> > > > > > >         unsigned int dma_data_width;
> > > > > > >         unsigned int mru_default;
> > > > > > >         bool sideband_wake;
> > > > > > > +    bool pm_disable;
> > > > > > >     };
> > > > > > >     #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name,
> > > > > > > el_count, ev_ring) \
> > > > > > > @@ -295,6 +297,7 @@ static const struct
> > > > > > > mhi_pci_dev_info mhi_qcom_qdu100_info = {
> > > > > > >         .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
> > > > > > >         .dma_data_width = 32,
> > > > > > >         .sideband_wake = false,
> > > > > > > +    .pm_disable = true,
> > > > > > 
> > > > > > |no_m3|orno_|m3_support|would be more suitable than|pm_disable|
> > > > > 
> > > > > Yes!
> > > > > 
> We named variable pm_disable because the M3 state is implicitly set during
> runtime PM suspend. Both are not needed and not fully supported for the
> QDU100 accelerator card, so we want to disable runtime suspend for it.

You are mixing terms here. Only M3 is not supported by the device. The fact that
you do not want to enable runtime PM for the device to avoid latency is a side
effect of that. So you need to name the variable as 'no_m3'.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH] bus: mhi: host: pci: Disable runtime PM for QDU100

[Vivek Pernamitta]

On 4/18/2025 6:15 PM, Manivannan Sadhasivam wrote:
> On Fri, Apr 18, 2025 at 03:40:48PM +0530, Vivek Pernamitta wrote:
>>
>>
>> On 4/18/2025 3:04 PM, Vivek Pernamitta wrote:
>>>
>>>
>>> On 4/18/2025 2:06 PM, Manivannan Sadhasivam wrote:
>>>> On Fri, Apr 18, 2025 at 11:55:24AM +0530, Vivek Pernamitta wrote:
>>>>>
>>>>>
>>>>> On 4/17/2025 11:37 AM, Manivannan Sadhasivam wrote:
>>>>>> On Thu, Apr 17, 2025 at 10:00:38AM +0530, Veerabhadrarao
>>>>>> Badiganti wrote:
>>>>>>>
>>>>>>> On 4/14/2025 1:17 PM, Vivek Pernamitta wrote:
>>>>>>>> The QDU100 device does not support the MHI M3 state,
>>>>>>>> necessitating the
>>>>>>>> disabling of runtime PM for this device. Since the
>>>>>>>> PCIe core framework
>>>>>>>> enables runtime PM by default for all clients, it is
>>>>>>>> essential to disable
>>>>>>>> runtime PM if the device does not support Low Power Mode (LPM).
>>>>>>>>
>>>>
>>>> Not true... See below.
>>>>
>>>>>>>> Signed-off-by: Vivek Pernamitta<quic_vpernami@quicinc.com>
>>>>>>>> ---
>>>>>>>>      drivers/bus/mhi/host/pci_generic.c | 10 ++++++++++
>>>>>>>>      1 file changed, 10 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/drivers/bus/mhi/host/pci_generic.c
>>>>>>>> b/drivers/bus/mhi/ host/pci_generic.c
>>>>>>>> index 03aa887952098661a488650053a357f883d1559b..a011fd2d48c57cf9d1aec74040153267a206d797
>>>>>>>> 100644
>>>>>>>> --- a/drivers/bus/mhi/host/pci_generic.c
>>>>>>>> +++ b/drivers/bus/mhi/host/pci_generic.c
>>>>>>>> @@ -43,6 +43,7 @@
>>>>>>>>       * @mru_default: default MRU size for MBIM network packets
>>>>>>>>       * @sideband_wake: Devices using dedicated
>>>>>>>> sideband GPIO for wakeup instead
>>>>>>>>       *           of inband wake support (such as sdx24)
>>>>>>>> + * @pm_disable: disables runtime PM (optional)
>>>>>>>>       */
>>>>>>>>      struct mhi_pci_dev_info {
>>>>>>>>          const struct mhi_controller_config *config;
>>>>>>>> @@ -54,6 +55,7 @@ struct mhi_pci_dev_info {
>>>>>>>>          unsigned int dma_data_width;
>>>>>>>>          unsigned int mru_default;
>>>>>>>>          bool sideband_wake;
>>>>>>>> +    bool pm_disable;
>>>>>>>>      };
>>>>>>>>      #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name,
>>>>>>>> el_count, ev_ring) \
>>>>>>>> @@ -295,6 +297,7 @@ static const struct
>>>>>>>> mhi_pci_dev_info mhi_qcom_qdu100_info = {
>>>>>>>>          .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
>>>>>>>>          .dma_data_width = 32,
>>>>>>>>          .sideband_wake = false,
>>>>>>>> +    .pm_disable = true,
>>>>>>>
>>>>>>> |no_m3|orno_|m3_support|would be more suitable than|pm_disable|
>>>>>>
>>>>>> Yes!
>>>>>>
>> We named variable pm_disable because the M3 state is implicitly set during
>> runtime PM suspend. Both are not needed and not fully supported for the
>> QDU100 accelerator card, so we want to disable runtime suspend for it.
> 
> You are mixing terms here. Only M3 is not supported by the device. The fact that
> you do not want to enable runtime PM for the device to avoid latency is a side
> effect of that. So you need to name the variable as 'no_m3'.
sure, I have posted an new patchset v3 with renaming the variable name 
to "no_m3".
> 
> - Mani
>