Re: [PATCH v4 5/7] perf/x86/amd/core: Add PerfMonV2 counter control

[Sandipan Das <sandipan.das@amd.com>]

On 5/9/2022 12:35 PM, Like Xu wrote:
> On 27/4/2022 7:31 pm, Sandipan Das wrote:
> 
>>   static void amd_pmu_add_event(struct perf_event *event)
>>   {
>>       if (needs_branch_stack(event))
>> @@ -1216,6 +1251,11 @@ static int __init amd_core_pmu_init(void)
>>           x86_pmu.num_counters = ebx.split.num_core_pmc;
>>             amd_pmu_global_cntr_mask = (1ULL << x86_pmu.num_counters) - 1;
>> +
>> +        /* Update PMC handling functions */
>> +        x86_pmu.enable_all = amd_pmu_v2_enable_all;
>> +        x86_pmu.disable_all = amd_pmu_v2_disable_all;
>> +        x86_pmu.enable = amd_pmu_v2_enable_event;
>>       }
> 
> Considering the below part of code also run on the PerfMonV2 host
> 
> whatever the guest PMU version, how about updating these two use cases as well in this patch ?
> 
> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
> index 262e39a85031..2f7c62e46314 100644
> --- a/arch/x86/events/amd/core.c
> +++ b/arch/x86/events/amd/core.c
> @@ -1469,8 +1469,8 @@ void amd_pmu_enable_virt(void)
>         cpuc->perf_ctr_virt_mask = 0;
> 
>         /* Reload all events */
> -       amd_pmu_disable_all();
> -       x86_pmu_enable_all(0);
> +       amd_pmu.disable_all();
> +       amd_pmu.enable_all(0);
>  }
>  EXPORT_SYMBOL_GPL(amd_pmu_enable_virt);
> 
> @@ -1487,7 +1487,7 @@ void amd_pmu_disable_virt(void)
>         cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
> 
>         /* Reload all events */
> -       amd_pmu_disable_all();
> -       x86_pmu_enable_all(0);
> +       amd_pmu.disable_all();
> +       amd_pmu.enable_all(0);
>  }
>  EXPORT_SYMBOL_GPL(amd_pmu_disable_virt);
> 

Good point. I had made these changes as a part of the guest PerfMonV2
enablement.


Peter,

Since these patches are now in perf/core, should I send out a separate
fix for this?


- Sandipan