Re: [PATCH v4 6/7] perf/x86/amd/core: Add PerfMonV2 overflow handling

[Sandipan Das <sandipan.das@amd.com>]

On 4/28/2022 7:10 PM, Like Xu wrote:
> On 27/4/2022 7:31 pm, Sandipan Das wrote:
>> +static inline void amd_pmu_ack_global_status(u64 status)
>> +{
>> +    /*
>> +     * PerfCntrGlobalStatus is read-only but an overflow acknowledgment
> 
> If wrmsrl PerfCntrGlobalStatus, remain silent or report #GP ?
> 

This is a read-only MSR and writes are silently ignored.

>> +     * mechanism exists; writing 1 to a bit in PerfCntrGlobalStatusClr
>> +     * clears the same bit in PerfCntrGlobalStatus
>> +     */
>> +
>> +    /* Only allow modifications to PerfCntrGlobalStatus.PerfCntrOvfl */
>> +    status &= amd_pmu_global_cntr_mask;
>> +    wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, status);
> 
> If rdmsrl PerfCntrGlobalStatusClr, does it return 0 or the value of PerfCntrGlobalStatus ?
> 

This is a write-only MSR and reads are undefined.

The "Field Access Type" section from the AMD Processor Programming
Reference (PPR) has these details.


- Sandipan