* [PATCH v3 0/2] arm64: errata: Share broken AMU constant-counter handling @ 2026-09-29 15:42 Beata Michalska 2026-09-29 15:42 ` [PATCH v3 1/2] arm64: errata: Factor out broken AMU const counter cap Beata Michalska 2026-09-29 15:42 ` [PATCH v3 2/2] arm64: errata: Add Cortex-A725 erratum 3821522 workaround Beata Michalska 0 siblings, 2 replies; 5+ messages in thread From: Beata Michalska @ 2026-09-29 15:42 UTC (permalink / raw) To: linux-arm-kernel Cc: Vladimir.Murzin, catalin.marinas, will, suzuki.poulose, James.Morse, xuewen.yan94, seanwang1, linux-kernel This series factors out the existing Cortex-A510 erratum 2457168 AMU constant counter workaround into a generic broken AMU constant-counter capability, then wires Cortex-A725 erratum 3821522 into the same handling. --- v3: - splitted the commit and droped changes for cpucap_is_possible --- Beata Michalska (2): arm64: errata: Factor out broken AMU const counter cap arm64: errata: Add Cortex-A725 erratum 3821522 workaround Documentation/arch/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 30 +++++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 29 +++++++++++++++----- arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kernel/topology.c | 16 ++++++----- arch/arm64/tools/cpucaps | 2 +- 6 files changed, 66 insertions(+), 15 deletions(-) -- 2.43.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 1/2] arm64: errata: Factor out broken AMU const counter cap 2026-09-29 15:42 [PATCH v3 0/2] arm64: errata: Share broken AMU constant-counter handling Beata Michalska @ 2026-09-29 15:42 ` Beata Michalska 2026-09-30 9:21 ` Vladimir Murzin 2026-09-29 15:42 ` [PATCH v3 2/2] arm64: errata: Add Cortex-A725 erratum 3821522 workaround Beata Michalska 1 sibling, 1 reply; 5+ messages in thread From: Beata Michalska @ 2026-09-29 15:42 UTC (permalink / raw) To: linux-arm-kernel Cc: Vladimir.Murzin, catalin.marinas, will, suzuki.poulose, James.Morse, xuewen.yan94, seanwang1, linux-kernel Move the workaround from the erratum 2457168-specific cpucap to a generic broken AMU constant-counter one. This keeps the existing Cortex-A510 handling unchanged while allowing other errata with similar AMU constant counter issue to share the capability bit and call sites. Cc: <stable@vger.kernel.org> Signed-off-by: Beata Michalska <beata.michalska@arm.com> --- arch/arm64/Kconfig | 8 ++++++++ arch/arm64/kernel/cpu_errata.c | 23 +++++++++++++++++------ arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kernel/topology.c | 7 ++++--- arch/arm64/tools/cpucaps | 2 +- 5 files changed, 31 insertions(+), 11 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b5a51b0ef9440..3b6c052d46a18 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1040,9 +1040,17 @@ config ARM64_ERRATUM_1902691 If unsure, say Y. +config ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT + bool + # Targeting errata affecting AMEVCNTR01, the AMU constant counter. + # On affected CPUs the counter may not increment at the expected rate, + # making it unreliable. As a result, AMU users should treat it as + # unavailable rather than relying on misleading counter values. + config ARM64_ERRATUM_2457168 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" depends on ARM64_AMU_EXTN + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT default y help This option adds the workaround for ARM Cortex-A510 erratum 2457168. diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 5db8f0619e4bc..f18683e56184b 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -381,6 +381,18 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { }; #endif +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT +static const struct arm64_cpu_capabilities arm64_repeat_amu_constcnt_list[] = { +#ifdef CONFIG_ARM64_ERRATUM_2457168 + { + /* Cortex-A510 r0p0-r1p1 */ + CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) + }, +#endif + {} +}; +#endif /* CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT */ + #ifdef CONFIG_CAVIUM_ERRATUM_23154 static const struct midr_range cavium_erratum_23154_cpus[] = { MIDR_ALL_VERSIONS(MIDR_THUNDERX), @@ -916,14 +928,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) }, #endif -#ifdef CONFIG_ARM64_ERRATUM_2457168 +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT { - .desc = "ARM erratum 2457168", - .capability = ARM64_WORKAROUND_2457168, + .desc = "Broken AMU AMEVCNTR01 (const counter)", + .capability = ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT, .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, - - /* Cortex-A510 r0p0-r1p1 */ - CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) + .matches = cpucap_multi_entry_cap_matches, + .match_list = arm64_repeat_amu_constcnt_list }, #endif #ifdef CONFIG_ARM64_ERRATUM_2038923 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 17b83a2518a8f..1569f84214763 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2064,7 +2064,7 @@ static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) cpumask_set_cpu(smp_processor_id(), &amu_cpus); /* 0 reference values signal broken/disabled counters */ - if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) + if (!this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT)) update_freq_counters_refs(); } } diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index d28438f8b83f1..64588554e7f76 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -402,7 +402,7 @@ static void cpu_read_constcnt(void *val) * the counter is disabled. A return value of 0 at counter read is * properly handled as an error case by the users of the counter. */ - *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_2457168) ? + *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT) ? 0UL : read_constcnt(); } @@ -463,8 +463,9 @@ static void amu_read_core_const_ctrs(void *val) /* * cpu_read_constcnt() incurs slight latency due to the - * ARM64_WORKAROUND_2457168 check. Read it first to minimize - * the sampling skew between the const and core counters. + * ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT check. + * Read it first to minimize the sampling skew between the const + * and core counters. */ cpu_read_constcnt(&ctrs->constcnt); cpu_read_corecnt(&ctrs->corecnt); diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 2775ba3359cfe..58b6c084f9f25 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -105,7 +105,6 @@ WORKAROUND_1902691 WORKAROUND_2038923 WORKAROUND_2064142 WORKAROUND_2077057 -WORKAROUND_2457168 WORKAROUND_2645198 WORKAROUND_2658417 WORKAROUND_4193714 @@ -132,3 +131,4 @@ WORKAROUND_REPEAT_TLBI_SYNC WORKAROUND_SPECULATIVE_AT WORKAROUND_SPECULATIVE_SSBS WORKAROUND_SPECULATIVE_UNPRIV_LOAD +WORKAROUND_BROKEN_AMU_CONSTCNT -- 2.43.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3 1/2] arm64: errata: Factor out broken AMU const counter cap 2026-09-29 15:42 ` [PATCH v3 1/2] arm64: errata: Factor out broken AMU const counter cap Beata Michalska @ 2026-09-30 9:21 ` Vladimir Murzin 0 siblings, 0 replies; 5+ messages in thread From: Vladimir Murzin @ 2026-09-30 9:21 UTC (permalink / raw) To: Beata Michalska, linux-arm-kernel Cc: catalin.marinas, will, suzuki.poulose, James.Morse, xuewen.yan94, seanwang1, linux-kernel Hi Beata, On 9/29/26 16:42, Beata Michalska wrote: > Move the workaround from the erratum 2457168-specific cpucap to a generic > broken AMU constant-counter one. This keeps the existing Cortex-A510 > handling unchanged while allowing other errata with similar AMU constant > counter issue to share the capability bit and call sites. > > Cc: <stable@vger.kernel.org> > Signed-off-by: Beata Michalska <beata.michalska@arm.com> > --- > arch/arm64/Kconfig | 8 ++++++++ > arch/arm64/kernel/cpu_errata.c | 23 +++++++++++++++++------ > arch/arm64/kernel/cpufeature.c | 2 +- > arch/arm64/kernel/topology.c | 7 ++++--- > arch/arm64/tools/cpucaps | 2 +- > 5 files changed, 31 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index b5a51b0ef9440..3b6c052d46a18 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -1040,9 +1040,17 @@ config ARM64_ERRATUM_1902691 > > If unsure, say Y. > > +config ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT > + bool > + # Targeting errata affecting AMEVCNTR01, the AMU constant counter. > + # On affected CPUs the counter may not increment at the expected rate, > + # making it unreliable. As a result, AMU users should treat it as > + # unavailable rather than relying on misleading counter values. > + > config ARM64_ERRATUM_2457168 > bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" > depends on ARM64_AMU_EXTN > + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT > default y > help > This option adds the workaround for ARM Cortex-A510 erratum 2457168. > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index 5db8f0619e4bc..f18683e56184b 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -381,6 +381,18 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { > }; > #endif > > +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT > +static const struct arm64_cpu_capabilities arm64_repeat_amu_constcnt_list[] = { ^^^^^^ There is nothing to repeat :) > +#ifdef CONFIG_ARM64_ERRATUM_2457168 > + { > + /* Cortex-A510 r0p0-r1p1 */ > + CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) > + }, > +#endif > + {} > +}; > +#endif /* CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT */ > + > #ifdef CONFIG_CAVIUM_ERRATUM_23154 > static const struct midr_range cavium_erratum_23154_cpus[] = { > MIDR_ALL_VERSIONS(MIDR_THUNDERX), > @@ -916,14 +928,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > }, > #endif > -#ifdef CONFIG_ARM64_ERRATUM_2457168 > +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT > { > - .desc = "ARM erratum 2457168", > - .capability = ARM64_WORKAROUND_2457168, > + .desc = "Broken AMU AMEVCNTR01 (const counter)", > + .capability = ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT, > .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, > - > - /* Cortex-A510 r0p0-r1p1 */ > - CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) I think it should be CAP_MIDR_RANGE_LIST(amu_broken_constcnt_cpus) where amu_broken_constcnt_cpus is static const struct midr_range amu_broken_constcnt_cpus[] = { #ifdef CONFIG_ARM64_ERRATUM_2457168 /* Cortex-A510 r0p0-r1p1 */ MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), #endif {} }; so in the next patch you would add new entry #ifdef CONFIG_ARM64_ERRATUM_3821522 /* Cortex-A725 r0p0 - r0p2 */ MIDR_RANGE(MIDR_CORTEX_A725, 0, 0, 0, 2), #endif Cheers Vladimir ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 2/2] arm64: errata: Add Cortex-A725 erratum 3821522 workaround 2026-09-29 15:42 [PATCH v3 0/2] arm64: errata: Share broken AMU constant-counter handling Beata Michalska 2026-09-29 15:42 ` [PATCH v3 1/2] arm64: errata: Factor out broken AMU const counter cap Beata Michalska @ 2026-09-29 15:42 ` Beata Michalska 2026-09-30 9:27 ` Vladimir Murzin 1 sibling, 1 reply; 5+ messages in thread From: Beata Michalska @ 2026-09-29 15:42 UTC (permalink / raw) To: linux-arm-kernel Cc: Vladimir.Murzin, catalin.marinas, will, suzuki.poulose, James.Morse, xuewen.yan94, seanwang1, linux-kernel Cortex-A725 erratum 3821522 affects the CNT_CYCLES event, which can incur a significant increment error when a CPU enters and subsequently exits WFE or WFI, and may no longer track the system counter frequency. The AMEVCNTR01_EL0 counter is used as the AMU constant counter for frequency invariance and CPPC FFH feedback counters. Wire the affected Cortex-A725 range into the shared broken AMU constant-counter capability so the affected counter is treated as unavailable by returning zero in the AMU counter paths. This prevents the broken counter from being used as a reference source. The erratum can also affect PMUv3 users of the CNT_CYCLES event, but this workaround intentionally does not change PMU event handling. Hiding or rejecting the PMU event from the erratum code would change the perf-visible PMU event interface, including raw event selection, and would need a separate PMU-specific approach rather than being folded into the AMU reference-counter workaround. Cc: <stable@vger.kernel.org> Signed-off-by: Beata Michalska <beata.michalska@arm.com> --- Documentation/arch/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 22 +++++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 6 ++++++ arch/arm64/kernel/topology.c | 9 +++++---- 4 files changed, 35 insertions(+), 4 deletions(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index ac3248b9f2f3b..99a1eb4b833dd 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -174,6 +174,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A725 | #3821522 | ARM64_ERRATUM_3821522 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #1502854 | N/A | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 3b6c052d46a18..cab741a695f52 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1081,6 +1081,28 @@ config ARM64_ERRATUM_2645198 If unsure, say Y. +config ARM64_ERRATUM_3821522 + bool "Cortex-A725: 3821522: workaround for possible CNT_CYCLES increment error due to WFE/WFI" + depends on ARM64_AMU_EXTN + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT + default y + help + This option adds the workaround for ARM Cortex-A725 erratum 3821522. + + On affected A725 cores, the CNT_CYCLES event may incur a significant + increment error when entering and subsequently exiting WFx. + As a result, the CNT_CYCLES may diverge from the system counter + frequency at which it is expected to increment. + This renders the AMU counter AMEVCNTR01, that implements CNT_CYCLES, + being unreliable and unsuitable for use. + + Since there is no hardware workaround, reads of the affected CNT_CYCLES + counter return 0 in the relevant paths. This causes users of the counter + to treat it as unavailable and is functionally equivalent to firmware + disabling the affected counter. + + If unsure, say Y. + config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD bool diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index f18683e56184b..42a6fff8c3f44 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -388,6 +388,12 @@ static const struct arm64_cpu_capabilities arm64_repeat_amu_constcnt_list[] = { /* Cortex-A510 r0p0-r1p1 */ CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) }, +#endif +#ifdef CONFIG_ARM64_ERRATUM_3821522 + { + /* Cortex-A725 r0p0 - r0p2 */ + CAP_MIDR_RANGE(MIDR_CORTEX_A725, 0, 0, 0, 2) + }, #endif {} }; diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 64588554e7f76..fc5d3abd12905 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -397,10 +397,11 @@ static void cpu_read_corecnt(void *val) static void cpu_read_constcnt(void *val) { /* - * Return 0 if the current CPU is affected by erratum 2457168. A value - * of 0 is also returned if the current CPU does not support AMUs or if - * the counter is disabled. A return value of 0 at counter read is - * properly handled as an error case by the users of the counter. + * Return 0 if the current CPU is affected by either erratum 2457168 + * or erratum 3821522. A value of 0 is also returned if the current + * CPU does not support AMUs or if the counter is disabled. A return + * value of 0 at counter read is properly handled as an error case + * by the users of the counter. */ *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT) ? 0UL : read_constcnt(); -- 2.43.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3 2/2] arm64: errata: Add Cortex-A725 erratum 3821522 workaround 2026-09-29 15:42 ` [PATCH v3 2/2] arm64: errata: Add Cortex-A725 erratum 3821522 workaround Beata Michalska @ 2026-09-30 9:27 ` Vladimir Murzin 0 siblings, 0 replies; 5+ messages in thread From: Vladimir Murzin @ 2026-09-30 9:27 UTC (permalink / raw) To: Beata Michalska, linux-arm-kernel Cc: catalin.marinas, will, suzuki.poulose, James.Morse, xuewen.yan94, seanwang1, linux-kernel Hi Beata, On 9/29/26 16:42, Beata Michalska wrote: > Cortex-A725 erratum 3821522 affects the CNT_CYCLES event, which can > incur a significant increment error when a CPU enters and subsequently > exits WFE or WFI, and may no longer track the system counter > frequency. > > The AMEVCNTR01_EL0 counter is used as the AMU constant counter for > frequency invariance and CPPC FFH feedback counters. Wire the affected > Cortex-A725 range into the shared broken AMU constant-counter capability > so the affected counter is treated as unavailable by returning zero in > the AMU counter paths. This prevents the broken counter from being used > as a reference source. > > The erratum can also affect PMUv3 users of the CNT_CYCLES event, > but this workaround intentionally does not change PMU event handling. > Hiding or rejecting the PMU event from the erratum code would change > the perf-visible PMU event interface, including raw event selection, > and would need a separate PMU-specific approach rather than being > folded into the AMU reference-counter workaround. > > Cc: <stable@vger.kernel.org> > Signed-off-by: Beata Michalska <beata.michalska@arm.com> > --- > Documentation/arch/arm64/silicon-errata.rst | 2 ++ > arch/arm64/Kconfig | 22 +++++++++++++++++++++ > arch/arm64/kernel/cpu_errata.c | 6 ++++++ > arch/arm64/kernel/topology.c | 9 +++++---- > 4 files changed, 35 insertions(+), 4 deletions(-) > > diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst > index ac3248b9f2f3b..99a1eb4b833dd 100644 > --- a/Documentation/arch/arm64/silicon-errata.rst > +++ b/Documentation/arch/arm64/silicon-errata.rst > @@ -174,6 +174,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A725 | #3821522 | ARM64_ERRATUM_3821522 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-X1 | #1502854 | N/A | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 | > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 3b6c052d46a18..cab741a695f52 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -1081,6 +1081,28 @@ config ARM64_ERRATUM_2645198 > > If unsure, say Y. > > +config ARM64_ERRATUM_3821522 > + bool "Cortex-A725: 3821522: workaround for possible CNT_CYCLES increment error due to WFE/WFI" > + depends on ARM64_AMU_EXTN > + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT > + default y > + help > + This option adds the workaround for ARM Cortex-A725 erratum 3821522. > + > + On affected A725 cores, the CNT_CYCLES event may incur a significant > + increment error when entering and subsequently exiting WFx. > + As a result, the CNT_CYCLES may diverge from the system counter > + frequency at which it is expected to increment. > + This renders the AMU counter AMEVCNTR01, that implements CNT_CYCLES, > + being unreliable and unsuitable for use. > + > + Since there is no hardware workaround, reads of the affected CNT_CYCLES > + counter return 0 in the relevant paths. This causes users of the counter > + to treat it as unavailable and is functionally equivalent to firmware > + disabling the affected counter. > + > + If unsure, say Y. > + > config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD > bool > > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index f18683e56184b..42a6fff8c3f44 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -388,6 +388,12 @@ static const struct arm64_cpu_capabilities arm64_repeat_amu_constcnt_list[] = { > /* Cortex-A510 r0p0-r1p1 */ > CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) > }, > +#endif > +#ifdef CONFIG_ARM64_ERRATUM_3821522 > + { > + /* Cortex-A725 r0p0 - r0p2 */ > + CAP_MIDR_RANGE(MIDR_CORTEX_A725, 0, 0, 0, 2) > + }, > #endif > {} > }; > diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c > index 64588554e7f76..fc5d3abd12905 100644 > --- a/arch/arm64/kernel/topology.c > +++ b/arch/arm64/kernel/topology.c > @@ -397,10 +397,11 @@ static void cpu_read_corecnt(void *val) > static void cpu_read_constcnt(void *val) > { > /* > - * Return 0 if the current CPU is affected by erratum 2457168. A value > - * of 0 is also returned if the current CPU does not support AMUs or if > - * the counter is disabled. A return value of 0 at counter read is > - * properly handled as an error case by the users of the counter. > + * Return 0 if the current CPU is affected by either erratum 2457168 > + * or erratum 3821522. A value of 0 is also returned if the current Perhaps wording it generically like: Return 0 if the current CPU is affected by a HW erratum. would save us from having to change the comment next time we encounter a broken AMU :) Thanks Vladimir ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-09-30 9:27 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2026-09-29 15:42 [PATCH v3 0/2] arm64: errata: Share broken AMU constant-counter handling Beata Michalska 2026-09-29 15:42 ` [PATCH v3 1/2] arm64: errata: Factor out broken AMU const counter cap Beata Michalska 2026-09-30 9:21 ` Vladimir Murzin 2026-09-29 15:42 ` [PATCH v3 2/2] arm64: errata: Add Cortex-A725 erratum 3821522 workaround Beata Michalska 2026-09-30 9:27 ` Vladimir Murzin
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