Re: [PATCH 3/3] clk: renesas: r9a07g043: Add MSTOP for RZ/G2UL

[Claudiu Beznea <claudiu.beznea@tuxon.dev>]

Hi, Geert,

On 04.08.2025 13:18, Geert Uytterhoeven wrote:
> Hi Claudiu,
> 
> On Fri, 4 Jul 2025 at 15:43, Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Add MSTOP configuration for all the module clocks on the RZ/G2UL
>> based SoCs (RZ/G2UL, RZ/V2L, RZ/Five).
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Thanks for your patch!
> 
>> --- a/drivers/clk/renesas/r9a07g043-cpg.c
>> +++ b/drivers/clk/renesas/r9a07g043-cpg.c
>>         DEF_MOD("canfd",        R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0,
>> -                               0x594, 0, 0),
>> +                               0x594, 0, MSTOP(BUS_MCPU2, BIT(9))),
>>         DEF_MOD("gpio",         R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,
>>                                 0x598, 0, 0),
> 
> MSTOP(BUS_PERI_CPU, BIT(6))?

Yes, this should be here. I'll add it in the next version.

Thank you for your review,
Claudiu

> 
>>         DEF_MOD("adc_adclk",    R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU,
>> -                               0x5a8, 0, 0),
>> +                               0x5a8, 0, MSTOP(BUS_MCPU2, BIT(14))),
> 
> The rest LGTM.
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
>