[PATCH] arm64: dts: qcom: sdm630: Add interconnect paths to the BLSP I2C and SPI controllers

[PATCH] arm64: dts: qcom: sdm630: Add interconnect paths to the BLSP I2C and SPI controllers

[Fabricio Akio via B4 Relay]

From: Fabricio Akio <fabricioakio@gmail.com>

The QUP I2C and SPI controllers move their data through the BLSP BAM
DMA engines, which reach DDR as the aggregation NoC masters BLSP_1 and
BLSP_2. No path is described for them, so nothing requests bandwidth for
those masters while a transfer runs.

Describe the path from each controller's BLSP master to DDR, as the
vendor kernel votes it. On a Motorola Moto X4 (SDM630), with the
boot-time interconnect votes released and system-level sleep enabled,
an I2C transfer running as the SoC entered that sleep hung the SoC
without these paths; with them, 5,000 transfers ran through about 3,000
sleep entries.

Signed-off-by: Fabricio Akio <fabricioakio@gmail.com>
---
Tested on a Motorola Moto X4 (SDM630), whose board file is not in
mainline yet, on the sdm660-mainline tree. System-level sleep there
comes from changes not yet posted. The UART nodes get no path: their
driver requests no bandwidth.
---
 arch/arm64/boot/dts/qcom/sdm630.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 3a1014804fb0..20225732e4a8 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1811,6 +1811,8 @@ blsp_i2c1: i2c@c175000 {
 			dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
 			dma-names = "tx", "rx";
 
+			interconnects = <&a2noc MASTER_BLSP_1 &bimc SLAVE_EBI>;
+
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&i2c1_default>;
 			pinctrl-1 = <&i2c1_sleep>;
@@ -1831,6 +1833,8 @@ blsp_i2c2: i2c@c176000 {
 			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
 			dma-names = "tx", "rx";
 
+			interconnects = <&a2noc MASTER_BLSP_1 &bimc SLAVE_EBI>;
+
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&i2c2_default>;
 			pinctrl-1 = <&i2c2_sleep>;
@@ -1851,6 +1855,8 @@ blsp_i2c3: i2c@c177000 {
 			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
 			dma-names = "tx", "rx";
 
+			interconnects = <&a2noc MASTER_BLSP_1 &bimc SLAVE_EBI>;
+
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&i2c3_default>;
 			pinctrl-1 = <&i2c3_sleep>;
@@ -1871,6 +1877,8 @@ blsp_i2c4: i2c@c178000 {
 			dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
 			dma-names = "tx", "rx";
 
+			interconnects = <&a2noc MASTER_BLSP_1 &bimc SLAVE_EBI>;
+
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&i2c4_default>;
 			pinctrl-1 = <&i2c4_sleep>;
@@ -1919,6 +1927,8 @@ blsp_i2c5: i2c@c1b5000 {
 			dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
 			dma-names = "tx", "rx";
 
+			interconnects = <&a2noc MASTER_BLSP_2 &bimc SLAVE_EBI>;
+
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&i2c5_default>;
 			pinctrl-1 = <&i2c5_sleep>;
@@ -1939,6 +1949,8 @@ blsp_i2c6: i2c@c1b6000 {
 			dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
 			dma-names = "tx", "rx";
 
+			interconnects = <&a2noc MASTER_BLSP_2 &bimc SLAVE_EBI>;
+
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&i2c6_default>;
 			pinctrl-1 = <&i2c6_sleep>;
@@ -1959,6 +1971,8 @@ blsp_i2c7: i2c@c1b7000 {
 			dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
 			dma-names = "tx", "rx";
 
+			interconnects = <&a2noc MASTER_BLSP_2 &bimc SLAVE_EBI>;
+
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&i2c7_default>;
 			pinctrl-1 = <&i2c7_sleep>;
@@ -1979,6 +1993,8 @@ blsp_spi7: spi@c1b7000 {
 			dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
 			dma-names = "tx", "rx";
 
+			interconnects = <&a2noc MASTER_BLSP_2 &bimc SLAVE_EBI>;
+
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&spi7_default>;
 			pinctrl-1 = <&spi7_sleep>;
@@ -1999,6 +2015,8 @@ blsp_i2c8: i2c@c1b8000 {
 			dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
 			dma-names = "tx", "rx";
 
+			interconnects = <&a2noc MASTER_BLSP_2 &bimc SLAVE_EBI>;
+
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&i2c8_default>;
 			pinctrl-1 = <&i2c8_sleep>;

---
base-commit: aac26bee2287c88af5be5a5ff96d783b19a28790
change-id: 20261009-sdm630-blsp-paths-bb3575c30032

Best regards,
--  
Fabricio Akio <fabricioakio@gmail.com>

Re: [PATCH] arm64: dts: qcom: sdm630: Add interconnect paths to the BLSP I2C and SPI controllers

[Dmitry Baryshkov]

On Fri, Oct 09, 2026 at 05:49:30PM -0300, Fabricio Akio via B4 Relay wrote:
> From: Fabricio Akio <fabricioakio@gmail.com>
> 
> The QUP I2C and SPI controllers move their data through the BLSP BAM
> DMA engines, which reach DDR as the aggregation NoC masters BLSP_1 and
> BLSP_2. No path is described for them, so nothing requests bandwidth for
> those masters while a transfer runs.
> 
> Describe the path from each controller's BLSP master to DDR, as the
> vendor kernel votes it. On a Motorola Moto X4 (SDM630), with the
> boot-time interconnect votes released and system-level sleep enabled,
> an I2C transfer running as the SoC entered that sleep hung the SoC
> without these paths; with them, 5,000 transfers ran through about 3,000
> sleep entries.
> 
> Signed-off-by: Fabricio Akio <fabricioakio@gmail.com>
> ---
> Tested on a Motorola Moto X4 (SDM630), whose board file is not in
> mainline yet, on the sdm660-mainline tree. System-level sleep there
> comes from changes not yet posted. The UART nodes get no path: their
> driver requests no bandwidth.
> ---
>  arch/arm64/boot/dts/qcom/sdm630.dtsi | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH] arm64: dts: qcom: sdm630: Add interconnect paths to the BLSP I2C and SPI controllers

[Konrad Dybcio]

On 10/9/26 10:49 PM, Fabricio Akio via B4 Relay wrote:
> From: Fabricio Akio <fabricioakio@gmail.com>
> 
> The QUP I2C and SPI controllers move their data through the BLSP BAM
> DMA engines, which reach DDR as the aggregation NoC masters BLSP_1 and
> BLSP_2. No path is described for them, so nothing requests bandwidth for
> those masters while a transfer runs.
> 
> Describe the path from each controller's BLSP master to DDR, as the
> vendor kernel votes it. On a Motorola Moto X4 (SDM630), with the
> boot-time interconnect votes released and system-level sleep enabled,
> an I2C transfer running as the SoC entered that sleep hung the SoC
> without these paths; with them, 5,000 transfers ran through about 3,000
> sleep entries.
> 
> Signed-off-by: Fabricio Akio <fabricioakio@gmail.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad