Re: [PATCH v5 13/27] clk: at91: sam9x7: add sam9x7 pmc driver

[claudiu beznea <claudiu.beznea@tuxon.dev>]

Hi, Varshini,

On 15.07.2024 09:46, Varshini.Rajendran@microchip.com wrote:
> Hi Claudiu,
> 
> On 14/07/24 7:25 pm, claudiu beznea wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Hi, Varshini,
>>
>> On 03.07.2024 13:28, Varshini Rajendran wrote:
>>> Add a driver for the PMC clocks of sam9x7 Soc family.
>>>
>>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>>> ---
>>>   drivers/clk/at91/Makefile |   1 +
>>>   drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++
>>>   2 files changed, 947 insertions(+)
>>>   create mode 100644 drivers/clk/at91/sam9x7.c
>>>

...

>>> +     for (i = 0; i < PLL_ID_MAX; i++) {
>>> +             for (j = 0; j < 3; j++) {
>>
>> I now realize that we are alocating more than needed memory for each PLL in
>> sam9x7_plls[][]. The number of columns for the 2d array is PLL_ID_MAX and
>> it should be 3. I can adjust it when applying but I need you to run a
>> simple boot test with it.
>>
> Yes. It boots and works perfectly with the change suggested. I am 
> pasting the snippet below just to be on the same page.
> 
> --- a/drivers/clk/at91/sam9x7.c
> +++ b/drivers/clk/at91/sam9x7.c
> @@ -198,7 +198,7 @@ static const struct {
>          const struct clk_pll_characteristics *c;
>          unsigned long f;
>          u8 eid;
> -} sam9x7_plls[][PLL_ID_MAX] = {
> +} sam9x7_plls[][3] = {

Great! Thank you!