From: "Sandipan Das (AMD)" <sandipandas1990@gmail.com>
To: Breno Leitao <leitao@debian.org>, Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
Sandipan Das <sandipan.das@amd.com>,
leit@fb.com, dcostantino@meta.com,
"open list:PERFORMANCE EVENTS SUBSYSTEM"
<linux-perf-users@vger.kernel.org>,
"open list:PERFORMANCE EVENTS SUBSYSTEM"
<linux-kernel@vger.kernel.org>,
ananth.narayan@amd.com
Subject: Re: [PATCH] perf/x86/amd: Do not WARN on every IRQ
Date: Fri, 16 Jun 2023 20:13:22 +0530 [thread overview]
Message-ID: <100041d0-f2fe-331b-13a7-ad09082aeb7d@gmail.com> (raw)
In-Reply-To: <ZIxrxpYtffT0FtEx@gmail.com>
On 16/06/23 7:33 pm, Breno Leitao wrote:
> On Fri, Jun 16, 2023 at 03:29:54PM +0200, Peter Zijlstra wrote:
>> On Fri, Jun 16, 2023 at 04:53:15AM -0700, Breno Leitao wrote:
>>> On some systems, the Performance Counter Global Status Register is
>>> coming with reserved bits set, which causes the system to be unusable
>>> if a simple `perf top` runs. The system hits the WARN() thousands times
>>> while perf runs.
>>>
>>> WARNING: CPU: 18 PID: 20608 at arch/x86/events/amd/core.c:944 amd_pmu_v2_handle_irq+0x1be/0x2b0
>>>
>>> This happens because the "Performance Counter Global Status Register"
>>> (PerfCntGlobalStatus) MSR has bit 7 set. Bit 7 should be reserved according
>>> to the documentation (Figure 13-12 from "AMD64 Architecture Programmer’s
>>> Manual, Volume 2: System Programming, 24593"[1]
>>
>> Would it then not make more sense to mask out bit7 before:
>
> It is more than bit 7. This is the register structure according to the document
> above:
>
> Bits Mnemonic Description Access type
> 63:60 Reserved RO
> 59 PMCF Performance Counter Freeze RO
> 58 LBRSF Last Branch Record Stack Freeze RO
> 57:6 Reserved RO
> 5:0 CNT_OF Counter overflow for PerfCnt[5:0] RO
>
> In the code, bit GLOBAL_STATUS_LBRS_FROZEN is handled and cleared before
> we reach my changes
>
> That said, your approach is almost similar to what I did, and I will be happy
> to change in order to make the code clearer.
>
>> + status &= ~AMD_PMU_V2_GLOBAL_STATUS_RESERVED;
>> if (!status)
>> goto done;
>>
>> ?
>>
>> Aside from being reserved, why are these bits magically set all of a
>> sudden?
>
> That is probably a question to AMD.
>
The reserved bits should never be set. The purpose of the WARN_ON() is to catch such anomalies.
I am working out the details with Breno and will report back with a resolution.
- Sandipan
[sending from my personal email as I currently don't have access to my work laptop]
next prev parent reply other threads:[~2023-06-16 14:43 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-16 11:53 Breno Leitao
2023-06-16 13:29 ` Peter Zijlstra
2023-06-16 14:03 ` Breno Leitao
2023-06-16 14:43 ` Sandipan Das (AMD) [this message]
2023-06-16 15:32 ` Peter Zijlstra
2023-09-13 14:30 ` Jirka Hladky
2023-09-13 15:03 ` Breno Leitao
2023-09-13 15:23 ` Jirka Hladky
2023-09-13 16:18 ` Sandipan Das
2023-09-14 8:44 ` Jirka Hladky
[not found] ` <CAE4VaGAcWk0PYygNGcguRA2V2qK03entkv6BUsnxhS-ftdfywg@mail.gmail.com>
2023-09-14 8:49 ` Sandipan Das
2023-09-13 16:24 ` Breno Leitao
2023-09-14 8:45 ` Jirka Hladky
2023-09-14 8:55 ` Sandipan Das
2023-09-14 9:12 ` Peter Zijlstra
2023-09-14 9:14 ` Sandipan Das
2023-09-14 9:30 ` Breno Leitao
2023-09-14 11:18 ` Peter Zijlstra
2023-09-14 11:22 ` Sandipan Das
2023-09-14 11:27 ` Peter Zijlstra
2023-09-14 12:21 ` Breno Leitao
2023-09-14 13:50 ` Jirka Hladky
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