From: Robert Love <rml@ufl.edu>
To: Tony Hagale <tony@hagale.net>
Cc: Bulent Abali <abali@us.ibm.com>, linux-kernel@vger.kernel.org
Subject: Re: Pentium SSE prefetcht0 instruction... How do you make it work
Date: 27 Sep 2001 15:55:35 -0400 [thread overview]
Message-ID: <1001620540.4649.25.camel@phantasy> (raw)
In-Reply-To: <Pine.LNX.4.21.0109271335550.4511-100000@hagale.net>
In-Reply-To: <Pine.LNX.4.21.0109271335550.4511-100000@hagale.net>
On Thu, 2001-09-27 at 14:43, Tony Hagale wrote:
> Intel's p3/4 prefetch instructions are hints only. They are only executed
> asynchronously, and depend heavily on the other load on the processor at
> the time. They are not required to prefetch, *and* they are not required
> to be executed when you think they should in the flow of the program. You
> can serialize them by using an MFENCE instruction, but they still aren't
> guaranteed to run.
>
> Check the p4 manuals. In fact, I'm not sure prefetch was implemented in
> p3. I could be wrong, check the manual.
prefetch is in P3 and P4.
there are prefetcht0, prefetcht1, prefetcht2, and prefetchnta
instructions, Intel's programming docs have references on these all
online.
--
Robert M. Love
rml at ufl.edu
rml at tech9.net
next prev parent reply other threads:[~2001-09-27 19:55 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-09-27 18:40 Bulent Abali
2001-09-27 18:43 ` Tony Hagale
2001-09-27 19:55 ` Robert Love [this message]
2001-09-27 19:54 ` Robert Love
2001-09-27 20:09 Bulent Abali
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