From: "Bulent Abali" <abali@us.ibm.com>
To: Tony Hagale <tony@hagale.net>
Cc: linux-kernel@vger.kernel.org
Subject: Re: Pentium SSE prefetcht0 instruction... How do you make it work
Date: Thu, 27 Sep 2001 16:09:43 -0400 [thread overview]
Message-ID: <OF1BD9092B.AC76CE4D-ON85256AD4.006E6555@pok.ibm.com> (raw)
>Intel's p3/4 prefetch instructions are hints only. They are only executed
>asynchronously, and depend heavily on the other load on the processor at
>the time. They are not required to prefetch, *and* they are not required
>to be executed when you think they should in the flow of the program. You
>can serialize them by using an MFENCE instruction, but they still aren't
>guaranteed to run.
>
>Check the p4 manuals. In fact, I'm not sure prefetch was implemented in
>p3. I could be wrong, check the manual.
>
>--Tony
PREFETCHx are in P3. I am aware that processor executes them optionally.
MFENCE may be a good idea. If load/store queues are full the processor
may just drop the prefetch instruction. I should try this.
Thanks for the suggestion. /bulent
next reply other threads:[~2001-09-27 20:09 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-09-27 20:09 Bulent Abali [this message]
-- strict thread matches above, loose matches on Subject: below --
2001-09-27 18:40 Bulent Abali
2001-09-27 18:43 ` Tony Hagale
2001-09-27 19:55 ` Robert Love
2001-09-27 19:54 ` Robert Love
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