From: Justin Carlson <justinca@ri.cmu.edu>
To: Dave Engebretsen <engebret@vnet.ibm.com>
Cc: justincarlson@cmu.edu, Alan Cox <alan@lxorguk.ukuu.org.uk>,
linux-kernel@vger.kernel.org
Subject: Re: Memory Barrier Definitions
Date: 08 May 2002 09:54:24 -0400 [thread overview]
Message-ID: <1020866064.1667.3.camel@xyzzy.stargate.net> (raw)
In-Reply-To: <3CD89247.8ECB01A4@vnet.ibm.com>
On Tue, 2002-05-07 at 22:49, Dave Engebretsen wrote:
> PPC also guarantees every ordering when using the 'sync' instruction, so
> that will give correctness at the price of a 1000 cycles or so. You
> refer to different rules for cached vs uncached on other implementations
> -- that is the essence of our problem. Are there different barrier
> instructions in MIPS which provide different levels of performance for
> different ordering enforcements?
>
> Dave.
No, there aren't. The implementation details can affect which
primitives need to explicitly sync, though.
For instance, the BRCM1250 makes some guarantees about visibility of
uncached writes that aren't strictly required by the architecture spec.
-Justin
next prev parent reply other threads:[~2002-05-08 13:54 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-05-07 19:07 Dave Engebretsen
2002-05-07 19:49 ` Alan Cox
2002-05-07 19:53 ` Dave Engebretsen
2002-05-07 20:27 ` Alan Cox
2002-05-07 21:23 ` Dave Engebretsen
2002-05-07 22:15 ` justincarlson
2002-05-08 2:49 ` Dave Engebretsen
2002-05-08 13:54 ` Justin Carlson [this message]
2002-05-08 15:27 ` Dave Engebretsen
2002-05-08 15:49 ` Andi Kleen
2002-05-08 17:07 ` David Mosberger
2002-05-09 7:36 ` Rusty Russell
2002-05-09 8:01 ` Keith Owens
2002-05-09 15:00 ` David Mosberger
2002-05-13 3:26 ` Rusty Russell
2002-05-13 16:36 ` David Mosberger
2002-05-13 16:50 ` Linus Torvalds
2002-05-13 17:53 ` David Mosberger
2002-05-13 23:28 ` Rusty Russell
2002-05-07 22:57 ` Anton Blanchard
2002-05-13 18:16 ` Jesse Barnes
2002-05-09 11:33 Manfred Spraul
2002-05-09 19:38 ` Dave Engebretsen
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