Re: can TSC tick with different speeds on SMP?

[john stultz <johnstul@us.ibm.com>]

On Mon, 2004-06-21 at 12:02, =?koi8-r?Q?=22?=Kirill
Korotaev=?koi8-r?Q?=22=20?= wrote:
> I've got some stupid question to SMP gurus and would be very thankful
> for the details. I suddenly faced an SMP system where different P4
> cpus were installed (with different steppings). This resulted in
> different CPU clock speeds and different speeds of time stamp counters
> on these CPUs. I faced the problem during some timings I measured in
> the kernel.
> So the question is "is such system compliant with SMP specification?".

Linux doesn't really support this configuration at the moment.
Historically Intel hasn't supported different stepping cpus in the same
system, much less different frequency cpus. I know the TSC time source
code won't handle it properly, and there are other users of rdtsc that
might cause problems. Other concerns would be users of cpu_khz
(scheduler?) and cpufreq code. 

I've heard that AMD has introduced this as a possible configuration, and
Intel may have changed their support story as well, so this may need to
be addressed. 

> In old kernels there was a code to syncronize TSCs and to detect if
> they were screwed up. Current kernels do not have such code. Is it
> intentional? I suppose there is some code in kernel which won't work
> find on such systems (real-time threads timing accounting and so on).

The TSC syncing code is still there, but it runs only once at boot. Thus
it will sync the cpus, but then won't account for the TSC drift between
them.

The only way to get around this is to use an alternate time source, such
as the ACPI-PM time source (clock=pmtmr), or even the PIT (clock=pit).
ACPI-PM still uses the TSC for delay() so it may still have issues, so
be warned.

thanks
-john