Re: can TSC tick with different speeds on SMP?

[Pasi Savolainen <psavo@iki.fi>]

* Kirill Korotaev <kksx@mail.ru>:
> Hello,
>
> I've got some stupid question to SMP gurus and would be very thankful
> for the details. I suddenly faced an SMP system where different P4 cpus
> were installed (with different steppings). This resulted in different
> CPU clock speeds and different speeds of time stamp counters on these
> CPUs. I faced the problem during some timings I measured in the kernel.
>   
> So the question is "is such system compliant with SMP specification?".

Well, I can't tell if it's SMP-compliant, but I can tell that it's
certainly not rare to have such a situation.

For example on AMD K7-SMP system when using powersaving mode which
basically 'turns CPU off' for a while, TSC's become desynchronized. At
the moment 2.6 -kernels handle this very well. (I haven't got problems
with it for more than half a year).

Now, I don't know what will happen if the become desynchronized because
of totally different _length_ of single tick. Is this what you
experience?

FWIW, this is what I get for timer in dmesg:
- -
 ...
Using pmtmr for high-res timesource
 ...
Using local APIC timer interrupts.
calibrating APIC timer ...
..... CPU clock speed is 1545.0689 MHz.
..... host bus clock speed is 268.0815 MHz.
checking TSC synchronization across 2 CPUs: passed.
 ...
- -


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   Psi -- <http://www.iki.fi/pasi.savolainen>