[PATCH 0/5] mm: flotsam

[PATCH 0/5] mm: flotsam

[Hugh Dickins]

Salvage a few damp pieces from the wreckage of my previous mm batch.
Against 2.6.15-rc2, shouldn't clash with other work.

Hugh

 arch/powerpc/mm/4xx_mmu.c     |    4 ---
 arch/powerpc/mm/hugetlbpage.c |    4 ---
 arch/powerpc/mm/mem.c         |    2 -
 arch/powerpc/mm/tlb_32.c      |    6 ++++
 arch/powerpc/mm/tlb_64.c      |    4 +--
 include/asm-alpha/atomic.h    |    7 ++++-
 include/asm-sparc64/atomic.h  |    1 
 include/asm-x86_64/atomic.h   |   51 +++++++++++++++++++++++++++++++-----------
 kernel/futex.c                |   15 ------------
 mm/Kconfig                    |    6 +---
 10 files changed, 56 insertions(+), 44 deletions(-)

[PATCH 1/5] mm: update split ptlock Kconfig

[Hugh Dickins]

Closer attention to the arithmetic shows that neither ppc64 nor sparc
really uses one page for multiple page tables: how on earth could they,
while pte_alloc_one returns just a struct page pointer, with no offset?

Well, arm26 manages it by returning a pte_t pointer cast to a struct
page pointer, harumph, then compensating in its pmd_populate.  But
arm26 is never SMP, so it's not a problem for split ptlock either.

And the PA-RISC situation has been recently improved: CONFIG_PA20 works
without the 16-byte alignment which inflated its spinlock_t.  But the
current union of spinlock_t with private does make the 7xxx struct page
significantly larger, even without debug, so disable its split ptlock.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
---

 mm/Kconfig |    6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)

--- 2.6.15-rc2/mm/Kconfig	2005-11-20 19:44:23.000000000 +0000
+++ linux/mm/Kconfig	2005-11-21 18:49:53.000000000 +0000
@@ -125,12 +125,10 @@ comment "Memory hotplug is currently inc
 # space can be handled with less contention: split it at this NR_CPUS.
 # Default to 4 for wider testing, though 8 might be more appropriate.
 # ARM's adjust_pte (unused if VIPT) depends on mm-wide page_table_lock.
-# PA-RISC's debug spinlock_t is too large for the 32-bit struct page.
-# ARM26 and SPARC32 and PPC64 may use one page for multiple page tables.
+# PA-RISC 7xxx's spinlock_t would enlarge struct page from 32 to 44 bytes.
 #
 config SPLIT_PTLOCK_CPUS
 	int
 	default "4096" if ARM && !CPU_CACHE_VIPT
-	default "4096" if PARISC && DEBUG_SPINLOCK && !64BIT
-	default "4096" if ARM26 || SPARC32 || PPC64
+	default "4096" if PARISC && !PA20
 	default "4"

[PATCH 2/5] mm: unbloat get_futex_key

[Hugh Dickins]

The follow_page changes in get_futex_key have left it with two almost
identical blocks, when handling the rare case of a futex in a nonlinear
vma.  get_user_pages will itself do that follow_page, and its additional
find_extend_vma is hardly any overhead since the vma is already cached.
Let's just delete the follow_page block and let get_user_pages do it.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
---

 kernel/futex.c |   15 ---------------
 1 files changed, 15 deletions(-)

--- 2.6.15-rc2/kernel/futex.c	2005-11-20 19:44:23.000000000 +0000
+++ linux/kernel/futex.c	2005-11-21 18:50:20.000000000 +0000
@@ -201,21 +201,6 @@ static int get_futex_key(unsigned long u
 	 * from swap.  But that's a lot of code to duplicate here
 	 * for a rare case, so we simply fetch the page.
 	 */
-
-	/*
-	 * Do a quick atomic lookup first - this is the fastpath.
-	 */
-	page = follow_page(mm, uaddr, FOLL_TOUCH|FOLL_GET);
-	if (likely(page != NULL)) {
-		key->shared.pgoff =
-			page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
-		put_page(page);
-		return 0;
-	}
-
-	/*
-	 * Do it the general way.
-	 */
 	err = get_user_pages(current, mm, uaddr, 1, 0, 0, &page, NULL);
 	if (err >= 0) {
 		key->shared.pgoff =

[PATCH 3/5] mm: powerpc ptlock comments

[Hugh Dickins]

Update comments (only) on page_table_lock and mmap_sem in arch/powerpc.
Removed the comment on page_table_lock from hash_huge_page: since it's
no longer taking page_table_lock itself, it's irrelevant whether others
are; but how it is safe (even against huge file truncation?) I can't say.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
---

 arch/powerpc/mm/hugetlbpage.c |    4 +---
 arch/powerpc/mm/mem.c         |    2 +-
 arch/powerpc/mm/tlb_32.c      |    6 ++++++
 arch/powerpc/mm/tlb_64.c      |    4 ++--
 4 files changed, 10 insertions(+), 6 deletions(-)

--- 2.6.15-rc2/arch/powerpc/mm/hugetlbpage.c	2005-11-20 19:43:31.000000000 +0000
+++ linux/arch/powerpc/mm/hugetlbpage.c	2005-11-21 18:50:46.000000000 +0000
@@ -754,9 +754,7 @@ repeat:
 	}
 
 	/*
-	 * No need to use ldarx/stdcx here because all who
-	 * might be updating the pte will hold the
-	 * page_table_lock
+	 * No need to use ldarx/stdcx here
 	 */
 	*ptep = __pte(new_pte & ~_PAGE_BUSY);
 
--- 2.6.15-rc2/arch/powerpc/mm/mem.c	2005-11-20 19:43:32.000000000 +0000
+++ linux/arch/powerpc/mm/mem.c	2005-11-21 18:50:46.000000000 +0000
@@ -495,7 +495,7 @@ EXPORT_SYMBOL(flush_icache_user_range);
  * We use it to preload an HPTE into the hash table corresponding to
  * the updated linux PTE.
  * 
- * This must always be called with the mm->page_table_lock held
+ * This must always be called with the pte lock held.
  */
 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
 		      pte_t pte)
--- 2.6.15-rc2/arch/powerpc/mm/tlb_32.c	2005-11-20 19:43:32.000000000 +0000
+++ linux/arch/powerpc/mm/tlb_32.c	2005-11-21 18:50:46.000000000 +0000
@@ -149,6 +149,12 @@ void flush_tlb_mm(struct mm_struct *mm)
 		return;
 	}
 
+	/*
+	 * It is safe to go down the mm's list of vmas when called
+	 * from dup_mmap, holding mmap_sem.  It would also be safe from
+	 * unmap_region or exit_mmap, but not from vmtruncate on SMP -
+	 * but it seems dup_mmap is the only SMP case which gets here.
+	 */
 	for (mp = mm->mmap; mp != NULL; mp = mp->vm_next)
 		flush_range(mp->vm_mm, mp->vm_start, mp->vm_end);
 	FINISH_FLUSH;
--- 2.6.15-rc2/arch/powerpc/mm/tlb_64.c	2005-11-20 19:43:32.000000000 +0000
+++ linux/arch/powerpc/mm/tlb_64.c	2005-11-21 18:50:46.000000000 +0000
@@ -95,7 +95,7 @@ static void pte_free_submit(struct pte_f
 
 void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf)
 {
-	/* This is safe as we are holding page_table_lock */
+	/* This is safe since tlb_gather_mmu has disabled preemption */
         cpumask_t local_cpumask = cpumask_of_cpu(smp_processor_id());
 	struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
 
@@ -206,7 +206,7 @@ void __flush_tlb_pending(struct ppc64_tl
 
 void pte_free_finish(void)
 {
-	/* This is safe as we are holding page_table_lock */
+	/* This is safe since tlb_gather_mmu has disabled preemption */
 	struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
 
 	if (*batchp == NULL)

Re: [PATCH 3/5] mm: powerpc ptlock comments

[Paul Mackerras]

Hugh Dickins writes:

> Update comments (only) on page_table_lock and mmap_sem in arch/powerpc.

[snip]

>  	/*
> -	 * No need to use ldarx/stdcx here because all who
> -	 * might be updating the pte will hold the
> -	 * page_table_lock
> +	 * No need to use ldarx/stdcx here
>  	 */

If you're going to remove the because clause you might as well remove
the whole comment.  What you have left is either redundant or
mystifying (according to the depth of knowledge of the reader).  And
in fact I don't think I could now say why we don't need an atomic
update sequence there, so I would appreciate something that updates
the "because" part.

Paul.

Re: [PATCH 3/5] mm: powerpc ptlock comments

[Hugh Dickins]

On Tue, 22 Nov 2005, Paul Mackerras wrote:
> 
> > Update comments (only) on page_table_lock and mmap_sem in arch/powerpc.
> 
> [snip]
> 
> >  	/*
> > -	 * No need to use ldarx/stdcx here because all who
> > -	 * might be updating the pte will hold the
> > -	 * page_table_lock
> > +	 * No need to use ldarx/stdcx here
> >  	 */
> 
> If you're going to remove the because clause you might as well remove
> the whole comment.  What you have left is either redundant or
> mystifying (according to the depth of knowledge of the reader).  And
> in fact I don't think I could now say why we don't need an atomic
> update sequence there, so I would appreciate something that updates
> the "because" part.

All I'm doing here is tidying up by removing the no-longer-appropriate
reference to page_table_lock.  As my snipped patch comment said:

> Update comments (only) on page_table_lock and mmap_sem in arch/powerpc.
> Removed the comment on page_table_lock from hash_huge_page: since it's
> no longer taking page_table_lock itself, it's irrelevant whether others
> are; but how it is safe (even against huge file truncation?) I can't say.

I'd appreciate something that updates the "because" part too, but don't
know the answer.  That other patch will need to come from your end - Ben?

Hugh

Re: [PATCH 3/5] mm: powerpc ptlock comments

[Benjamin Herrenschmidt]

On Tue, 2005-11-22 at 07:12 +0000, Hugh Dickins wrote:

> I'd appreciate something that updates the "because" part too, but don't
> know the answer.  That other patch will need to come from your end - Ben?

Hrm... same reason as __hash_page(), the code now locks the PTE using
the _PAGE_BUSY bit. The last store does the update and unlock and
doesn't need to be atomic. However, now that I look at it, it might need
an lwsync. Paul ?

Ben.

[PATCH 4/5] mm: powerpc init_mm without ptlock

[Hugh Dickins]

Restore an earlier mod which went missing in the powerpc reshuffle:
the 4xx mmu_mapin_ram does not need to take init_mm.page_table_lock.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
---

 arch/powerpc/mm/4xx_mmu.c |    4 ----
 1 files changed, 4 deletions(-)

--- 2.6.15-rc2/arch/powerpc/mm/4xx_mmu.c	2005-11-20 19:43:31.000000000 +0000
+++ linux/arch/powerpc/mm/4xx_mmu.c	2005-11-21 18:51:25.000000000 +0000
@@ -110,13 +110,11 @@ unsigned long __init mmu_mapin_ram(void)
 		pmd_t *pmdp;
 		unsigned long val = p | _PMD_SIZE_16M | _PAGE_HWEXEC | _PAGE_HWWRITE;
 
-		spin_lock(&init_mm.page_table_lock);
 		pmdp = pmd_offset(pgd_offset_k(v), v);
 		pmd_val(*pmdp++) = val;
 		pmd_val(*pmdp++) = val;
 		pmd_val(*pmdp++) = val;
 		pmd_val(*pmdp++) = val;
-		spin_unlock(&init_mm.page_table_lock);
 
 		v += LARGE_PAGE_SIZE_16M;
 		p += LARGE_PAGE_SIZE_16M;
@@ -127,10 +125,8 @@ unsigned long __init mmu_mapin_ram(void)
 		pmd_t *pmdp;
 		unsigned long val = p | _PMD_SIZE_4M | _PAGE_HWEXEC | _PAGE_HWWRITE;
 
-		spin_lock(&init_mm.page_table_lock);
 		pmdp = pmd_offset(pgd_offset_k(v), v);
 		pmd_val(*pmdp) = val;
-		spin_unlock(&init_mm.page_table_lock);
 
 		v += LARGE_PAGE_SIZE_4M;
 		p += LARGE_PAGE_SIZE_4M;

[PATCH 5/5] mm: fill arch atomic64 gaps

[Hugh Dickins]

alpha, sparc64, x86_64 are each missing some primitives from their
atomic64 support: fill in the gaps I've noticed by extrapolating asm,
follow the groupings in each file.  But powerpc and parisc still lack
atomic64.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
---

 include/asm-alpha/atomic.h   |    7 ++++-
 include/asm-sparc64/atomic.h |    1 
 include/asm-x86_64/atomic.h  |   51 ++++++++++++++++++++++++++++++++-----------
 3 files changed, 44 insertions(+), 15 deletions(-)

--- 2.6.15-rc2/include/asm-alpha/atomic.h	2005-11-20 19:44:12.000000000 +0000
+++ linux/include/asm-alpha/atomic.h	2005-11-21 18:52:03.000000000 +0000
@@ -118,8 +118,6 @@ static __inline__ long atomic_add_return
 	return result;
 }
 
-#define atomic_add_negative(a, v)	(atomic_add_return((a), (v)) < 0)
-
 static __inline__ long atomic64_add_return(long i, atomic64_t * v)
 {
 	long temp, result;
@@ -189,6 +187,9 @@ static __inline__ long atomic64_sub_retu
 })
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 
+#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
+#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
+
 #define atomic_dec_return(v) atomic_sub_return(1,(v))
 #define atomic64_dec_return(v) atomic64_sub_return(1,(v))
 
@@ -199,6 +200,8 @@ static __inline__ long atomic64_sub_retu
 #define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0)
 
 #define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
+#define atomic64_inc_and_test(v) (atomic64_add_return(1, (v)) == 0)
+
 #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
 #define atomic64_dec_and_test(v) (atomic64_sub_return(1, (v)) == 0)
 
--- 2.6.15-rc2/include/asm-sparc64/atomic.h	2005-11-20 19:44:19.000000000 +0000
+++ linux/include/asm-sparc64/atomic.h	2005-11-21 18:52:03.000000000 +0000
@@ -54,6 +54,7 @@ extern int atomic64_sub_ret(int, atomic6
  * other cases.
  */
 #define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
 
 #define atomic_sub_and_test(i, v) (atomic_sub_ret(i, v) == 0)
 #define atomic64_sub_and_test(i, v) (atomic64_sub_ret(i, v) == 0)
--- 2.6.15-rc2/include/asm-x86_64/atomic.h	2005-11-20 19:44:20.000000000 +0000
+++ linux/include/asm-x86_64/atomic.h	2005-11-21 18:52:03.000000000 +0000
@@ -160,8 +160,8 @@ static __inline__ int atomic_inc_and_tes
 
 /**
  * atomic_add_negative - add and test if negative
- * @v: pointer of type atomic_t
  * @i: integer value to add
+ * @v: pointer of type atomic_t
  * 
  * Atomically adds @i to @v and returns true
  * if the result is negative, or false when
@@ -178,6 +178,31 @@ static __inline__ int atomic_add_negativ
 	return c;
 }
 
+/**
+ * atomic_add_return - add and return
+ * @i: integer value to add
+ * @v: pointer of type atomic_t
+ *
+ * Atomically adds @i to @v and returns @i + @v
+ */
+static __inline__ int atomic_add_return(int i, atomic_t *v)
+{
+	int __i = i;
+	__asm__ __volatile__(
+		LOCK "xaddl %0, %1;"
+		:"=r"(i)
+		:"m"(v->counter), "0"(i));
+	return i + __i;
+}
+
+static __inline__ int atomic_sub_return(int i, atomic_t *v)
+{
+	return atomic_add_return(-i,v);
+}
+
+#define atomic_inc_return(v)  (atomic_add_return(1,v))
+#define atomic_dec_return(v)  (atomic_sub_return(1,v))
+
 /* An 64bit atomic type */
 
 typedef struct { volatile long counter; } atomic64_t;
@@ -320,14 +345,14 @@ static __inline__ int atomic64_inc_and_t
 
 /**
  * atomic64_add_negative - add and test if negative
- * @v: pointer to atomic64_t
  * @i: integer value to add
+ * @v: pointer to type atomic64_t
  *
  * Atomically adds @i to @v and returns true
  * if the result is negative, or false when
  * result is greater than or equal to zero.
  */
-static __inline__ long atomic64_add_negative(long i, atomic64_t *v)
+static __inline__ int atomic64_add_negative(long i, atomic64_t *v)
 {
 	unsigned char c;
 
@@ -339,27 +364,30 @@ static __inline__ long atomic64_add_nega
 }
 
 /**
- * atomic_add_return - add and return
- * @v: pointer of type atomic_t
+ * atomic64_add_return - add and return
  * @i: integer value to add
+ * @v: pointer to type atomic64_t
  *
  * Atomically adds @i to @v and returns @i + @v
  */
-static __inline__ int atomic_add_return(int i, atomic_t *v)
+static __inline__ long atomic64_add_return(long i, atomic64_t *v)
 {
-	int __i = i;
+	long __i = i;
 	__asm__ __volatile__(
-		LOCK "xaddl %0, %1;"
+		LOCK "xaddq %0, %1;"
 		:"=r"(i)
 		:"m"(v->counter), "0"(i));
 	return i + __i;
 }
 
-static __inline__ int atomic_sub_return(int i, atomic_t *v)
+static __inline__ long atomic64_sub_return(long i, atomic64_t *v)
 {
-	return atomic_add_return(-i,v);
+	return atomic64_add_return(-i,v);
 }
 
+#define atomic64_inc_return(v)  (atomic64_add_return(1,v))
+#define atomic64_dec_return(v)  (atomic64_sub_return(1,v))
+
 #define atomic_cmpxchg(v, old, new) ((int)cmpxchg(&((v)->counter), old, new))
 
 /**
@@ -381,9 +409,6 @@ static __inline__ int atomic_sub_return(
 })
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 
-#define atomic_inc_return(v)  (atomic_add_return(1,v))
-#define atomic_dec_return(v)  (atomic_sub_return(1,v))
-
 /* These are x86-specific, used by some header files */
 #define atomic_clear_mask(mask, addr) \
 __asm__ __volatile__(LOCK "andl %0,%1" \