From: Dmitry Osipenko <digetx@gmail.com>
To: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Rob Herring <robh+dt@kernel.org>,
linux-tegra@vger.kernel.org, devel@driverdev.osuosl.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 1/2] staging: Introduce NVIDIA Tegra20 video decoder driver
Date: Tue, 26 Sep 2017 15:02:44 +0300 [thread overview]
Message-ID: <113675da-6b85-ef2f-03a9-84e5cb93c31b@gmail.com> (raw)
In-Reply-To: <52f5c05f-7060-4d0f-355f-6da372c9ded0@wwwdotorg.org>
On 26.09.2017 08:11, Stephen Warren wrote:
> On 09/25/2017 05:45 PM, Dmitry Osipenko wrote:
>> On 26.09.2017 02:01, Stephen Warren wrote:
>>> On 09/25/2017 04:15 PM, Dmitry Osipenko wrote:
>>>> Video decoder, found on NVIDIA Tegra20 SoC, supports a standard set of
>>>> video formats like H.264 / MPEG-4 / WMV / VC1. Currently driver supports
>>>> decoding of CAVLC H.264 only.
>>>
>>> Note: I don't know anything much about video decoding on Tegra (just NV desktop
>>> GPUs, and that was a while ago), but I had a couple small comments on the DT
>>> binding:
>>>
>>>> diff --git
>>>> a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-vde.txt
>>>> b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-vde.txt
>>>
>>>> +NVIDIA Tegra Video Decoder Engine
>>>> +
>>>> +Required properties:
>>>> +- compatible : "nvidia,tegra20-vde"
>>>> +- reg : Must contain 2 register ranges: registers and IRAM area.
>>>> +- reg-names : Must include the following entries:
>>>> + - regs
>>>> + - iram
>>>
>>> I think the IRAM region needs more explanation: What is the region used for and
>>> by what? Can it be moved, and if so does the move need to be co-ordinated with
>>> any other piece of SW?
>>
>> IRAM region is used by Video Decoder HW for internal use and some of decoding
>> parameters are supplied via IRAM, like frames order list. AFAIK IRAM addresses
>> are hardwired in HW and aren't movable, it is not 100% but I'm pretty sure.
>> Should it be explained in the binding?
>
> I think this should be briefly mentioned, yes. Otherwise at least people
> who don't know the VDE HW well (like me) will wonder why on earth VDE
> interacts with IRAM at all. I would have assumed all parameters were
> supplied via registers or via descriptors in DRAM.
>
> Thanks.
>
I also forgot to mention that VDE scrubs that IRAM region on HW reset. So yeah,
it's definitely a part of HW definition. I'll add a brief explanation to the
binding.
--
Dmitry
next prev parent reply other threads:[~2017-09-26 12:02 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-25 22:15 [PATCH v1 0/2] " Dmitry Osipenko
2017-09-25 22:15 ` [PATCH v1 1/2] staging: Introduce " Dmitry Osipenko
2017-09-25 23:01 ` Stephen Warren
2017-09-25 23:45 ` Dmitry Osipenko
2017-09-26 5:11 ` Stephen Warren
2017-09-26 12:02 ` Dmitry Osipenko [this message]
2017-09-27 9:45 ` Dan Carpenter
2017-09-27 23:28 ` Dmitry Osipenko
2017-09-28 7:23 ` Dan Carpenter
2017-09-28 11:37 ` Dmitry Osipenko
2017-09-27 23:31 ` Dmitry Osipenko
2017-09-25 22:15 ` [PATCH v1 2/2] ARM: dts: tegra20: Add video decoder node Dmitry Osipenko
2017-09-26 6:54 ` [PATCH v1 0/2] NVIDIA Tegra20 video decoder driver Greg Kroah-Hartman
2017-09-26 12:32 ` Dmitry Osipenko
2017-09-26 21:35 ` Greg Kroah-Hartman
2017-09-26 22:17 ` Dmitry Osipenko
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