memory barriers and dma_sync_single_for_*

memory barriers and dma_sync_single_for_*

[Stefan Richter]

Hi all,

I have a memory area which is written by the CPU and concurrently read 
by a DMA capable device, multiple times.

Among else there are two fields in the memory area, both are 32 bits 
wide. Whenever the CPU updates the fields, I have to make sure that the 
device does not get to see a new value in field B before I updated field 
A. Conversely, it is safe to update field A anytime before field B. The 
driver has no way to know when the device is going to read any of the 
fields.

My question: Do I need wmb() within the following code?

	dma_sync_single_for_cpu(..., DMA_TO_DEVICE);
	area->a = new_val_a;
	wmb();  /* necessary? */
	area->b = new_val_b;
	dma_sync_single_for_device(..., DMA_TO_DEVICE);

Or are all changes to the area hidden from the device between 
dma_sync_single_for_cpu and _for_device, thereby making the write order 
a non-issue? Thanks,
-- 
Stefan Richter
-=====-=-==- -=== -=--=
http://arcgraph.de/sr/

Re: memory barriers and dma_sync_single_for_*

[Alan Cox]

Ar Sul, 2006-07-09 am 16:53 +0200, ysgrifennodd Stefan Richter:
> My question: Do I need wmb() within the following code?
> 
> 	dma_sync_single_for_cpu(..., DMA_TO_DEVICE);
> 	area->a = new_val_a;
> 	wmb();  /* necessary? */
> 	area->b = new_val_b;

Yes. Otherwise on some processors the I/O may be re-ordered

> 	dma_sync_single_for_device(..., DMA_TO_DEVICE);
> 
> Or are all changes to the area hidden from the device between 
> dma_sync_single_for_cpu and _for_device, thereby making the write order 
> a non-issue? Thanks,

Depends on the processor and setup. On x86-32 for example dma_sync_.. is
generally a NOP. In other environments nothing will be visible until the
sync.

Alan