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From: Andrew Cooper <Andrew.Cooper3@citrix.com>
To: Suraj Jitindar Singh <surajjs@amazon.com>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>
Cc: "sjitindarsingh@gmail.com" <sjitindarsingh@gmail.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"x86@kernel.org" <x86@kernel.org>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"mingo@redhat.com" <mingo@redhat.com>, "bp@suse.de" <bp@suse.de>,
	"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
	"seanjc@google.com" <seanjc@google.com>,
	"pbonzini@redhat.com" <pbonzini@redhat.com>,
	"peterz@infradead.org" <peterz@infradead.org>,
	"jpoimboe@kernel.org" <jpoimboe@kernel.org>,
	"daniel.sneddon@linux.intel.com" <daniel.sneddon@linux.intel.com>,
	"pawan.kumar.gupta@linux.intel.com" 
	<pawan.kumar.gupta@linux.intel.com>,
	"benh@kernel.crashing.org" <benh@kernel.crashing.org>,
	"stable@vger.kernel.org" <stable@vger.kernel.org>,
	Andrew Cooper <Andrew.Cooper3@citrix.com>
Subject: Re: [PATCH] x86/speculation: Mitigate eIBRS PBRSB predictions with WRMSR
Date: Thu, 6 Oct 2022 02:42:10 +0000	[thread overview]
Message-ID: <11ebe489-0734-28af-07a4-f658709cfd9e@citrix.com> (raw)
In-Reply-To: <20221005220227.1959-1-surajjs@amazon.com>

On 05/10/2022 23:02, Suraj Jitindar Singh wrote:
> tl;dr: The existing mitigation for eIBRS PBRSB predictions uses an INT3 to
> ensure a call instruction retires before a following unbalanced RET.

No it doesn't.  The INT3 is transient.  The existing mitigation uses an
LFENCE.

> Replace this with a WRMSR serialising instruction which has a lower performance
> penalty.

What is "this"?  The INT3^W LFENCE?

WRMSR is not lower overhead than an LFENCE.

> == Solution ==
>
> The WRMSR instruction can be used as a speculation barrier and a serialising
> instruction. Use this on the VM exit path instead to ensure that a CALL
> instruction (in this case the call to vmx_spec_ctrl_restore_host) has retired
> before the prediction of a following unbalanced RET.

While both of these sentences are true statements, you've missed the
necessary safety property.

One CALL has to retire before *any* RET can execute.

There are several ways the frontend can end up eventually consuming the
bad RSB entry; they all stem from an execute (not prediction) of the
next RET instruction.

As to the change, ...

> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index c9b49a09e6b5..fdcd8e10c2ab 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -7049,8 +7049,13 @@ void noinstr vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx,

... out of context above this hunk is:

    if (!cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL))
        return;

meaning that there is a return instruction which is programmatically
reachable ahead of the WRMSR.

Whether it is speculatively reachable depends on whether the frontend
can see through the _static_cpu_has(), as well as
X86_FEATURE_MSR_SPEC_CTRL never becoming compile time evaluable.

There is also a second latent bug, to do with the code generation for
this_cpu_read(x86_spec_ctrl_current).


It's worth saying that, in principle, this optimisation is safe, but
pretty much all the discussion about it is wrong.  Here is one I
prepared earlier:
https://lore.kernel.org/xen-devel/20220809170016.25148-3-andrew.cooper3@citrix.com/


OTOH, below the hunk in question, there's a barrier_nospec() which is
giving you the actual projection you need (subject to latent and/or code
layout bugs), irrespective of the extra WRMSR.

~Andrew

  parent reply	other threads:[~2022-10-06  2:45 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-05 22:02 Suraj Jitindar Singh
2022-10-05 22:29 ` Jim Mattson
2022-10-06  8:25   ` David Laight
2022-10-06 20:27     ` pawan.kumar.gupta
2022-10-05 23:24 ` Jim Mattson
2022-10-05 23:45   ` Pawan Gupta
2022-10-05 23:46 ` Jim Mattson
2022-10-06  0:26   ` Daniel Sneddon
2022-10-06  1:28     ` Jim Mattson
2022-10-06  8:18   ` Peter Zijlstra
2022-10-06  2:42 ` Andrew Cooper [this message]
2022-10-07  1:44   ` pawan.kumar.gupta
2022-10-07  1:54 ` Pawan Gupta

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