Mapping PCI BAR through /sys/devices/pci* sets cache-disable and write-through

[Keith Packard <keithp@keithp.com>]

[-- Attachment #1: Type: text/plain, Size: 831 bytes --]

The X server recently (within the last year) switched from mapping the
frame buffer from /dev/mem to using /sys/devices/pci*. This caused a
significant memory bandwidth reduction for writes, similar to the effect
caused when the associated MTRR is set to UC instead of WC.

Looking at the code path, we find, in i386:pci_mmap_page_range:

        prot = pgprot_val(vma->vm_page_prot);
        if (boot_cpu_data.x86 > 3)
                prot |= _PAGE_PCD | _PAGE_PWT;
        vma->vm_page_prot = __pgprot(prot);

Which is to say, on any CPU which supports it, force the cache-disable
and write-through bits on.

Is there some reason this is there? Surely applications should be
expected to set these attributes correctly, currently using MTRR and in
the future, using PAT directly.

-- 
keith.packard@intel.com

[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]