From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: "Pallipadi, Venkatesh" <venkatesh.pallipadi@intel.com>
Cc: "Keith Packard" <keithp@keithp.com>,
"linux-kernel" <linux-kernel@vger.kernel.org>,
"Siddha, Suresh B" <suresh.b.siddha@intel.com>
Subject: Re: Mapping PCI BAR through /sys/devices/pci* sets cache-disableandwrite-through
Date: Thu, 17 Apr 2008 10:07:17 -0700 [thread overview]
Message-ID: <200804171007.17898.jbarnes@virtuousgeek.org> (raw)
In-Reply-To: <924EFEDD5F540B4284297C4DC59F3DEEE5D0C7@orsmsx423.amr.corp.intel.com>
On Thursday, April 17, 2008 6:14 am Pallipadi, Venkatesh wrote:
> >Jesse Barnes suggested using the fact that the BAR was prefetchable to
> >guess that this region should not be mapped UC. I don't know of any
> >other information available at this API that would help make a better
> >choice; there are no ioctls on /sys files that we could use to
> >manipulate the mapping.
>
> Yes. But, the API being there for some time may mean that there is some
> user who always wants UC behavior with or without PREFETCHABLE flag.
> With PAT changes we thought of ioctl and then settled on new interface.
Yeah, we can't really know. There *probably* aren't any users here that would
break, but you never know, and it's best not to change the behavior of an
existing API...
> >Yeah, we'll do that when it becomes available. Would it make sense in
> >the pre-PAT world to use Jesse's guess?
>
> Yes. Easiest way to do that will be to use UC_MINUS (Just set PCD bit
> and not PWT bit) until PAT changes.
> Ioremap() uses UC_MINUS, it should not have any side effects to other
> users who expect this mapping to be UC without any MTRR setting.
We could probably do that unconditionally though, rather than dependent on the
prefetchable bit like my patch does.
> >In any case, we'll continue to use the fact that mprotect is
> >also broken
> >to get our WC mapping working (using mprotect PROT_NONE followed by
> >mprotect PROT_READ|PROT_WRITE causes the CD and WT bits to get
> >cleared).
> >We're fortunate in this case that we've found a bug to exploit that
> >gives us the desired behaviour.
>
> Noo.. Now we have one more thing in PAT to do list :-(. To go and plug
> those mprotect APIs to prevent users from doing things like this.
I think it's just a long standing bug... mprotect really shouldn't be
clobbering PTE bits regardless of PAT (though with PAT the bug becomes more
serious).
Jesse
prev parent reply other threads:[~2008-04-17 17:07 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-04-16 17:40 Mapping PCI BAR through /sys/devices/pci* sets cache-disable and write-through Keith Packard
2008-04-16 22:23 ` Mapping PCI BAR through /sys/devices/pci* sets cache-disable andwrite-through Pallipadi, Venkatesh
2008-04-17 5:20 ` Keith Packard
2008-04-17 13:14 ` Mapping PCI BAR through /sys/devices/pci* sets cache-disableandwrite-through Pallipadi, Venkatesh
2008-04-17 17:07 ` Jesse Barnes [this message]
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