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From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Borislav Petkov <bp@alien8.de>,
	x86@kernel.org, linux-kernel@vger.kernel.org, leo.duran@amd.com,
	yazen.ghannam@amd.com, Peter Zijlstra <peterz@infradead.org>
Subject: Re: [PATCH 1/2] x86/CPU/AMD: Present package as die instead of socket
Date: Tue, 27 Jun 2017 22:55:52 +0700	[thread overview]
Message-ID: <122fd136-e3a1-1d59-87c8-a24de6b078c1@amd.com> (raw)
In-Reply-To: <alpine.DEB.2.20.1706271604550.1798@nanos>

On 6/27/17 21:21, Thomas Gleixner wrote:
> On Tue, 27 Jun 2017, Suravee Suthikulpanit wrote:
>> On 6/27/17 17:48, Borislav Petkov wrote:
>>> On Tue, Jun 27, 2017 at 01:40:52AM -0500, Suravee Suthikulpanit wrote:
>>>> However, this is not the case on AMD family17h multi-die processor
>>>> platforms, which can have up to 4 dies per socket as shown in the
>>>> following system topology.
>>>
>>> So what exactly does that mean? A die is a package on ZN and you can have up
>>> to 4 packages on a physical socket?
>>
>> Yes. 4 packages (or 4 dies, or 4 NUMA nodes) in a socket.
>
> And why is this relevant at all?
>
> The kernel does not care about sockets. Sockets are electromechanical
> components and completely irrelevant.
>
> The kernel cares about :
>
>     Threads	 - Single scheduling unit
>
>     Cores	 - Contains one or more threads
>
>     Packages	 - Contains one or more cores. The cores share L3.
>
>     NUMA Node	 - Contains one or more Packages which share a memory
>     	 	   controller.
>
> 		   I'm not aware of x86 systems which have several Packages
> 		   sharing a memory controller, so Package == NUMA Node
> 		   (but I might be wrong here).

According to the definition of Packages above, x86_has_numa_in_package does not 
map to the topology we are trying to present here since we have 2 L3 caches 
(packages) in a NUMA node. So, I am not sure if x86_has_numa_in_package make 
sense here.

>     Platform	 - Contains one or more Numa Nodes
>
> All the kernel is interested in is the above and the NUMA Node distance so
> it knows about memory access latencies. No sockets, no MCMs, that's all
> completely useless for the scheduler.

Agree to your point here that we do not care about socket, MCMs, and anything 
that has to do with the physical grouping of the cores here. It does not really 
mean anything as long as we can correctly describe the NUMA node topology.

The reason we are trying to present "package == NUMA node (die)" here is because 
the topology.txt defines package to contain a number of cores plus shared 
resources (e.g. DRAM controller, shared caches, etc). Since the 
cpuinfo_x86.phys_proc_id is also defined as the physical ID of the package, and 
it is used in the arch/x86/kernel/smpboot.c: match_die(), we think it would make 
sense to represent package == NUMA node (die) here instead of a socket.

> So if the current CPUID stuff gives you the same phycial package ID for all
> packages in a MCM, then this needs to be fixed at the CPUID/ACPI/BIOS level
> and not hacked around in the kernel.

Unfortunately, the information from CPUID (since the older families) has been 
representing the whole physical package topology, which is why we need fix-up in 
the AMD specific code (in arch/x86/kernel/cpu/amd.c) to correctly derive 
topology information as defined in the topology.txt.

Thanks,
Suravee

  parent reply	other threads:[~2017-06-27 15:56 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-27  6:40 [PATCH 0/2] x86/CPU/AMD: Fix multi-die processor topology info Suravee Suthikulpanit
2017-06-27  6:40 ` [PATCH 1/2] x86/CPU/AMD: Present package as die instead of socket Suravee Suthikulpanit
2017-06-27 10:48   ` Borislav Petkov
2017-06-27 13:07     ` Suravee Suthikulpanit
2017-06-27 13:42       ` Borislav Petkov
2017-06-27 16:54         ` Suravee Suthikulpanit
2017-06-27 17:44           ` Borislav Petkov
2017-06-27 18:32             ` Ghannam, Yazen
2017-06-27 18:44               ` Borislav Petkov
2017-06-27 20:26             ` Suravee Suthikulpanit
2017-06-28  9:12               ` Borislav Petkov
2017-06-27 14:21       ` Thomas Gleixner
2017-06-27 14:54         ` Brice Goglin
2017-06-27 15:48         ` Duran, Leo
2017-06-27 16:11           ` Borislav Petkov
2017-06-27 16:23             ` Duran, Leo
2017-06-27 16:31               ` Borislav Petkov
2017-06-27 16:42                 ` Duran, Leo
2017-06-27 16:45                   ` Borislav Petkov
2017-06-27 17:04                     ` Duran, Leo
2017-06-27 16:19           ` Thomas Gleixner
2017-06-27 16:34             ` Duran, Leo
2017-06-27 15:55         ` Suravee Suthikulpanit [this message]
2017-06-27 16:16           ` Borislav Petkov
2017-07-05 15:50       ` Peter Zijlstra
2017-06-27  6:40 ` [PATCH 2/2] x86/CPU/AMD: Use L3 Cache info from CPUID to determine LLC ID Suravee Suthikulpanit

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