From: Borislav Petkov <bp@alien8.de>
To: "Duran, Leo" <leo.duran@amd.com>
Cc: "'Thomas Gleixner'" <tglx@linutronix.de>,
"Suthikulpanit, Suravee" <Suravee.Suthikulpanit@amd.com>,
"x86@kernel.org" <x86@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Ghannam, Yazen" <Yazen.Ghannam@amd.com>,
Peter Zijlstra <peterz@infradead.org>
Subject: Re: [PATCH 1/2] x86/CPU/AMD: Present package as die instead of socket
Date: Tue, 27 Jun 2017 18:11:56 +0200 [thread overview]
Message-ID: <20170627161156.yim2pxtyg7efrbef@pd.tnic> (raw)
In-Reply-To: <DM5PR12MB12439895F6D748B8AC1A7997F9DC0@DM5PR12MB1243.namprd12.prod.outlook.com>
On Tue, Jun 27, 2017 at 03:48:55PM +0000, Duran, Leo wrote:
> Basically, in our case a Package may contain more than one L3 (i.e.,
> in hardware terms, there may more than one 'Core complex' in a 'Die').
> The important point is that all logical processors (threads) that
> share an L3 have a common "cpu_llc_id".
All that means nothing if it doesn't have any effect on scheduling.
If moving the working set between L3s within the package, as you call
it, is not measureable, i.e., task migration, then we don't care. The
whole exercise is not about modelling the hardware topology accurately
but for presenting sufficient detailed topology to the scheduler so that
it works optimally on Zen.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
next prev parent reply other threads:[~2017-06-27 16:12 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-27 6:40 [PATCH 0/2] x86/CPU/AMD: Fix multi-die processor topology info Suravee Suthikulpanit
2017-06-27 6:40 ` [PATCH 1/2] x86/CPU/AMD: Present package as die instead of socket Suravee Suthikulpanit
2017-06-27 10:48 ` Borislav Petkov
2017-06-27 13:07 ` Suravee Suthikulpanit
2017-06-27 13:42 ` Borislav Petkov
2017-06-27 16:54 ` Suravee Suthikulpanit
2017-06-27 17:44 ` Borislav Petkov
2017-06-27 18:32 ` Ghannam, Yazen
2017-06-27 18:44 ` Borislav Petkov
2017-06-27 20:26 ` Suravee Suthikulpanit
2017-06-28 9:12 ` Borislav Petkov
2017-06-27 14:21 ` Thomas Gleixner
2017-06-27 14:54 ` Brice Goglin
2017-06-27 15:48 ` Duran, Leo
2017-06-27 16:11 ` Borislav Petkov [this message]
2017-06-27 16:23 ` Duran, Leo
2017-06-27 16:31 ` Borislav Petkov
2017-06-27 16:42 ` Duran, Leo
2017-06-27 16:45 ` Borislav Petkov
2017-06-27 17:04 ` Duran, Leo
2017-06-27 16:19 ` Thomas Gleixner
2017-06-27 16:34 ` Duran, Leo
2017-06-27 15:55 ` Suravee Suthikulpanit
2017-06-27 16:16 ` Borislav Petkov
2017-07-05 15:50 ` Peter Zijlstra
2017-06-27 6:40 ` [PATCH 2/2] x86/CPU/AMD: Use L3 Cache info from CPUID to determine LLC ID Suravee Suthikulpanit
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