Re: [PATCH] PCI: Always set prefetchable base/limit upper32 registers

[Alex Williamson <alex.williamson@hp.com>]

On Mon, 2009-11-30 at 22:35 -0800, Yinghai Lu wrote:
> Alex Williamson wrote:
> > 
> > The upper32 base register works as advertised, that's not where we clear
> > the MEM_64 flag.  I tracked that down to pbus_size_mem().  So, we have a
> > MEM_64 capable prefetchable base, but we want to use it to map a 32bit
> > resource behind the bridge (a ROM in this case), so we drop the MEM_64
> > flag, causing us to hit pci_setup_bridge() with the flag clear and thus
> > not touching UPPER32.  I think your second patch would also solve this
> > since it separates the desired resource size from the register size.
> > However, it seems much more simple to unconditionally write the upper32
> > registers as was done for all 2.6 kernels up to 2.6.30.  Thanks,
> 
> if the bridge self does not support 64bit pref mmio, we should not touch
> upper32 reg.

Does touching it actually cause any problems?  The spec states:
        
        If the Prefetchable Memory Base and Prefetchable Memory Limit
        registers indicate support for 32-bit addressing, then the
        Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32
        Bits registers are both implemented as read-only registers that
        return zero when read.
        
So even if the bridge only supports 32bit prefetchable, the upper32
registers are still present and writes will be dropped.  This is the way
the code worked for a long, long time.  I'm wondering why we need to
make it more complicated.

Alex