From: Robert Richter <robert.richter@amd.com>
To: Ingo Molnar <mingo@elte.hu>
Cc: Peter Zijlstra <peterz@infradead.org>,
LKML <linux-kernel@vger.kernel.org>,
oprofile-list <oprofile-list@lists.sourceforge.net>,
Robert Richter <robert.richter@amd.com>
Subject: [PATCH 1/9] perf, x86: reduce number of CONFIG_X86_LOCAL_APIC macros
Date: Thu, 4 Mar 2010 16:22:03 +0100 [thread overview]
Message-ID: <1267716131-17908-2-git-send-email-robert.richter@amd.com> (raw)
In-Reply-To: <1267716131-17908-1-git-send-email-robert.richter@amd.com>
The function reserve_pmc_hardware() and release_pmc_hardware() were
hard to read. This patch improves readablity of the code by removing
most of the CONFIG_X86_LOCAL_APIC macros.
Signed-off-by: Robert Richter <robert.richter@amd.com>
---
arch/x86/kernel/cpu/perf_event.c | 15 +++++++++------
1 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 6531b4b..96b3a98 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -234,9 +234,10 @@ again:
static atomic_t active_events;
static DEFINE_MUTEX(pmc_reserve_mutex);
+#ifdef CONFIG_X86_LOCAL_APIC
+
static bool reserve_pmc_hardware(void)
{
-#ifdef CONFIG_X86_LOCAL_APIC
int i;
if (nmi_watchdog == NMI_LOCAL_APIC)
@@ -251,11 +252,9 @@ static bool reserve_pmc_hardware(void)
if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
goto eventsel_fail;
}
-#endif
return true;
-#ifdef CONFIG_X86_LOCAL_APIC
eventsel_fail:
for (i--; i >= 0; i--)
release_evntsel_nmi(x86_pmu.eventsel + i);
@@ -270,12 +269,10 @@ perfctr_fail:
enable_lapic_nmi_watchdog();
return false;
-#endif
}
static void release_pmc_hardware(void)
{
-#ifdef CONFIG_X86_LOCAL_APIC
int i;
for (i = 0; i < x86_pmu.num_events; i++) {
@@ -285,9 +282,15 @@ static void release_pmc_hardware(void)
if (nmi_watchdog == NMI_LOCAL_APIC)
enable_lapic_nmi_watchdog();
-#endif
}
+#else
+
+static bool reserve_pmc_hardware(void) { return true; }
+static void release_pmc_hardware(void) {}
+
+#endif
+
static inline bool bts_available(void)
{
return x86_pmu.enable_bts != NULL;
--
1.7.0
next prev parent reply other threads:[~2010-03-04 16:51 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-03-04 15:22 [PATCH 0/9] oprofile, perf, x86: introduce new functions to reserve perfctrs Robert Richter
2010-03-04 15:22 ` Robert Richter [this message]
2010-03-04 15:22 ` [PATCH 2/9] oprofile, perf, x86: do not allocate evntsel counter msr Robert Richter
2010-03-04 15:22 ` [PATCH 3/9] oprofile, perf, x86: introduce new functions to reserve perfctrs by index Robert Richter
2010-03-20 5:45 ` Andi Kleen
2010-03-25 15:52 ` Robert Richter
2010-03-25 19:33 ` Andi Kleen
2010-03-04 15:22 ` [PATCH 4/9] tsc, x86: use new perfctr reservation functions in tsc code Robert Richter
2010-03-04 15:22 ` [PATCH 5/9] perf, x86: use new perfctr reservation functions in perf code Robert Richter
2010-03-04 15:22 ` [PATCH 6/9] oprofile/x86: rework error handler in nmi_setup() Robert Richter
2010-03-04 15:22 ` [PATCH 7/9] oprofile/x86: return -EBUSY if counters are already reserved Robert Richter
2010-03-04 15:22 ` [PATCH 8/9] oprofile/x86: group IBS code Robert Richter
2010-03-04 15:22 ` [PATCH 9/9] oprofile/x86: implement perfctr reservation for IBS Robert Richter
2010-03-04 17:59 ` [PATCH 0/9] oprofile, perf, x86: introduce new functions to reserve perfctrs Peter Zijlstra
2010-03-11 11:48 ` Peter Zijlstra
2010-03-11 12:47 ` Ingo Molnar
2010-03-11 15:45 ` Robert Richter
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