From: Robert Richter <robert.richter@amd.com>
To: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Ingo Molnar <mingo@elte.hu>,
Stephane Eranian <eranian@google.com>,
LKML <linux-kernel@vger.kernel.org>,
Robert Richter <robert.richter@amd.com>
Subject: [PATCH 04/12] perf: introduce flag for model specific events
Date: Tue, 13 Apr 2010 22:23:13 +0200 [thread overview]
Message-ID: <1271190201-25705-5-git-send-email-robert.richter@amd.com> (raw)
In-Reply-To: <1271190201-25705-1-git-send-email-robert.richter@amd.com>
This patch introduces a flag to mark events as model specific. The
flag can be used to setup hardware events other than generic
performance counters by passing special config data to the pmu. The
data can be interpreted different from generic events and can be used
for other purposes.
The concept of PMU model-specific arguments was practiced already in
Perfmon2. Perfmon2 provides an interface to pass model specific config
values to the pmu and receive event specific samples back. The
implementation of the model specific flag extends the perf_event i/f
by this feature too.
The userland program must be aware of the cpu model to create
model specific events. This could be done for example by checking the
cpu and family.
The model_spec flag can be arbitrarily reused on other models or
architectures. For backward compatibility all architectures must
return an error, if model_spec events are not supported and the bit is
set.
E.g., this flag is used to setup IBS on an AMD cpu. IBS is not common
to pmu features from other vendors or architectures. The pmu must be
setup with a special config value. Sample data is returned in a
certain format back to the userland. An IBS event is passed in the
config field of the event attributes and with model_spec and raw event
flag enabled. The samples are then passed back in a raw sample.
Signed-off-by: Robert Richter <robert.richter@amd.com>
---
arch/powerpc/kernel/perf_event.c | 3 +++
arch/sh/kernel/perf_event.c | 3 +++
arch/sparc/kernel/perf_event.c | 3 +++
arch/x86/kernel/cpu/perf_event.c | 3 +++
include/linux/perf_event.h | 3 ++-
5 files changed, 14 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c
index 08460a2..8e68e15 100644
--- a/arch/powerpc/kernel/perf_event.c
+++ b/arch/powerpc/kernel/perf_event.c
@@ -1037,6 +1037,9 @@ const struct pmu *hw_perf_event_init(struct perf_event *event)
event->hw.config_base = ev;
event->hw.idx = 0;
+ if (attr->model_spec)
+ return ERR_PTR(-EOPNOTSUPP);
+
/*
* If we are not running on a hypervisor, force the
* exclude_hv bit to 0 so that we don't care what
diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c
index 81b6de4..eef545a 100644
--- a/arch/sh/kernel/perf_event.c
+++ b/arch/sh/kernel/perf_event.c
@@ -109,6 +109,9 @@ static int __hw_perf_event_init(struct perf_event *event)
if (!sh_pmu_initialized())
return -ENODEV;
+ if (attr->model_spec)
+ return -EOPNOTSUPP;
+
/*
* All of the on-chip counters are "limited", in that they have
* no interrupts, and are therefore unable to do sampling without
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index e277193..5c1d2a4 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -1083,6 +1083,9 @@ static int __hw_perf_event_init(struct perf_event *event)
} else
return -EOPNOTSUPP;
+ if (attr->model_spec)
+ return -EOPNOTSUPP;
+
/* We save the enable bits in the config_base. */
hwc->config_base = sparc_pmu->irq_bit;
if (!attr->exclude_user)
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 5945128..9eeffad 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -432,6 +432,9 @@ static int x86_setup_perfctr(struct perf_event *event)
struct hw_perf_event *hwc = &event->hw;
u64 config;
+ if (attr->model_spec)
+ return -EOPNOTSUPP;
+
if (!hwc->sample_period) {
hwc->sample_period = x86_pmu.max_period;
hwc->last_period = hwc->sample_period;
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 6e96cc8..e90ba6e 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -204,8 +204,9 @@ struct perf_event_attr {
task : 1, /* trace fork/exit */
watermark : 1, /* wakeup_watermark */
precise : 1, /* OoO invariant counter */
+ model_spec : 1, /* model specific hw event */
- __reserved_1 : 48;
+ __reserved_1 : 47;
union {
__u32 wakeup_events; /* wakeup every n events */
--
1.7.0.3
next prev parent reply other threads:[~2010-04-13 20:29 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-04-13 20:23 [PATCH 00/12] perf: introduce model specific events and AMD IBS Robert Richter
2010-04-13 20:23 ` [PATCH 01/12] perf, x86: move perfctr init code to x86_setup_perfctr() Robert Richter
2010-05-07 18:42 ` [tip:perf/core] perf, x86: Move " tip-bot for Robert Richter
2010-04-13 20:23 ` [PATCH 02/12] perf, x86: moving x86_setup_perfctr() Robert Richter
2010-05-07 18:42 ` [tip:perf/core] perf, x86: Move x86_setup_perfctr() tip-bot for Robert Richter
2010-04-13 20:23 ` [PATCH 03/12] perf, x86: call x86_setup_perfctr() from .hw_config() Robert Richter
2010-05-07 18:42 ` [tip:perf/core] perf, x86: Call " tip-bot for Robert Richter
2010-04-13 20:23 ` Robert Richter [this message]
2010-04-13 20:23 ` [PATCH 05/12] perf, x86: pass enable bit mask to __x86_pmu_enable_event() Robert Richter
2010-05-07 18:43 ` [tip:perf/core] perf, x86: Pass " tip-bot for Robert Richter
2010-04-13 20:23 ` [PATCH 06/12] perf, x86: use weight instead of cmask in for_each_event_constraint() Robert Richter
2010-05-07 18:43 ` [tip:perf/core] perf, x86: Use " tip-bot for Robert Richter
2010-04-13 20:23 ` [PATCH 07/12] perf, x86: introduce bit range for special pmu events Robert Richter
2010-04-13 20:23 ` [PATCH 08/12] perf, x86: modify some code to allow the introduction of ibs events Robert Richter
2010-04-13 20:23 ` [PATCH 09/12] perf, x86: implement IBS feature detection Robert Richter
2010-04-13 20:23 ` [PATCH 10/12] perf, x86: setup NMI handler for IBS Robert Richter
2010-04-15 12:57 ` Peter Zijlstra
2010-04-15 13:11 ` Robert Richter
2010-04-19 16:04 ` Robert Richter
2010-04-13 20:23 ` [PATCH 11/12] perf, x86: implement AMD IBS event configuration Robert Richter
2010-04-19 13:46 ` Stephane Eranian
2010-04-20 10:31 ` Robert Richter
2010-04-20 16:05 ` Robert Richter
2010-04-21 8:47 ` Robert Richter
2010-04-21 9:02 ` Stephane Eranian
2010-04-21 9:21 ` Robert Richter
2010-04-21 10:54 ` Robert Richter
2010-04-21 11:37 ` Stephane Eranian
2010-04-21 16:58 ` Robert Richter
2010-04-22 17:32 ` Stephane Eranian
2010-05-11 13:57 ` Robert Richter
2010-04-13 20:23 ` [PATCH 12/12] perf, x86: implement the ibs interrupt handler Robert Richter
2010-04-19 12:19 ` Stephane Eranian
2010-04-20 13:10 ` Robert Richter
2010-04-22 14:45 ` Robert Richter
2010-05-07 15:28 ` [PATCH] perf: fix raw sample size if no sampling data is attached Robert Richter
2010-05-07 15:41 ` Peter Zijlstra
2010-05-07 19:48 ` Robert Richter
2010-05-18 15:12 ` [RFC PATCH] perf: align raw sample data on 64-bit boundaries Robert Richter
2010-05-19 7:39 ` Frederic Weisbecker
2010-05-19 9:31 ` Robert Richter
2010-05-24 21:25 ` Frederic Weisbecker
2010-05-28 17:35 ` Robert Richter
2010-04-13 20:45 ` [osrc-patches] [PATCH 00/12] perf: introduce model specific events and AMD IBS Robert Richter
2010-04-14 12:31 ` Robert Richter
2010-04-15 7:41 ` Peter Zijlstra
2010-04-15 7:44 ` Peter Zijlstra
2010-04-15 15:16 ` Robert Richter
2010-04-21 12:11 ` Peter Zijlstra
2010-04-21 13:21 ` Stephane Eranian
2010-04-21 18:26 ` Robert Richter
2010-04-21 18:40 ` Stephane Eranian
2010-04-21 16:28 ` Robert Richter
2010-04-28 16:16 ` [osrc-patches] " Robert Richter
2010-05-04 14:18 ` Peter Zijlstra
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