* [PATCH -v3 0/2] x86, MCE, FIX MSR_IA32_MCI_CTL2_CMCI threshold setup
@ 2010-05-18 5:36 Huang Ying
2010-05-18 5:36 ` [PATCH -v3 2/2] x86, MCE, fix MSR_IA32_MCI_CTL2 CMCI " Huang Ying
2010-05-18 5:36 ` [PATCH -v3 1/2] x86, MCE, rename MSR_IA32_MCx_CTL2 value Huang Ying
0 siblings, 2 replies; 4+ messages in thread
From: Huang Ying @ 2010-05-18 5:36 UTC (permalink / raw)
To: Ingo Molnar, H. Peter Anvin
Cc: linux-kernel, ying.huang, andi, Hidetoshi Seto
Changelog:
v3:
- Separate patch into 2 patches, one for renaming, the other for threshold
setup fixing.
v2:
- Rename CMCI_EN to MCI_CTL2_CMCI_EN and CMCI_THRESHOLD_MASK to
MCI_CTL2_CMCI_THRESHOLD_MASK to make naming consistent.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH -v3 2/2] x86, MCE, fix MSR_IA32_MCI_CTL2 CMCI threshold setup
2010-05-18 5:36 [PATCH -v3 0/2] x86, MCE, FIX MSR_IA32_MCI_CTL2_CMCI threshold setup Huang Ying
@ 2010-05-18 5:36 ` Huang Ying
2010-05-18 5:36 ` [PATCH -v3 1/2] x86, MCE, rename MSR_IA32_MCx_CTL2 value Huang Ying
1 sibling, 0 replies; 4+ messages in thread
From: Huang Ying @ 2010-05-18 5:36 UTC (permalink / raw)
To: Ingo Molnar, H. Peter Anvin
Cc: linux-kernel, ying.huang, andi, Hidetoshi Seto
It is reported that CMCI is not raised when number of corrected error
reaches preset threshold. After inspection, it is found that
MSR_IA32_MCI_CTL2 threshold field is not setup properly. This patch
fixed it.
Value of MCI_CTL2_CMCI_THRESHOLD_MASK is fixed according to x86_64
Software Developer's Manual too.
Reported-by: Shaohui Zheng <shaohui.zheng@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
---
arch/x86/include/asm/mce.h | 2 +-
arch/x86/kernel/cpu/mcheck/mce_intel.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -40,7 +40,7 @@
/* CTL2 register defines */
#define MCI_CTL2_CMCI_EN (1ULL << 30)
-#define MCI_CTL2_CMCI_THRESHOLD_MASK 0xffffULL
+#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
#define MCJ_CTX_MASK 3
#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -102,6 +102,7 @@ static void cmci_discover(int banks, int
continue;
}
+ val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
val |= MCI_CTL2_CMCI_EN | CMCI_THRESHOLD;
wrmsrl(MSR_IA32_MCx_CTL2(i), val);
rdmsrl(MSR_IA32_MCx_CTL2(i), val);
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH -v3 1/2] x86, MCE, rename MSR_IA32_MCx_CTL2 value
2010-05-18 5:36 [PATCH -v3 0/2] x86, MCE, FIX MSR_IA32_MCI_CTL2_CMCI threshold setup Huang Ying
2010-05-18 5:36 ` [PATCH -v3 2/2] x86, MCE, fix MSR_IA32_MCI_CTL2 CMCI " Huang Ying
@ 2010-05-18 5:36 ` Huang Ying
1 sibling, 0 replies; 4+ messages in thread
From: Huang Ying @ 2010-05-18 5:36 UTC (permalink / raw)
To: Ingo Molnar, H. Peter Anvin
Cc: linux-kernel, ying.huang, andi, Hidetoshi Seto
Rename CMCI_EN to MCI_CTL2_CMCI_EN and CMCI_THRESHOLD_MASK to
MCI_CTL2_CMCI_THRESHOLD_MASK to make naming consistent.
Signed-off-by: Huang Ying <ying.huang@intel.com>
---
arch/x86/include/asm/mce.h | 4 ++++
arch/x86/include/asm/msr-index.h | 3 ---
arch/x86/kernel/cpu/mcheck/mce_intel.c | 8 ++++----
3 files changed, 8 insertions(+), 7 deletions(-)
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -38,6 +38,10 @@
#define MCM_ADDR_MEM 3 /* memory address */
#define MCM_ADDR_GENERIC 7 /* generic */
+/* CTL2 register defines */
+#define MCI_CTL2_CMCI_EN (1ULL << 30)
+#define MCI_CTL2_CMCI_THRESHOLD_MASK 0xffffULL
+
#define MCJ_CTX_MASK 3
#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
#define MCJ_CTX_RANDOM 0 /* inject context: random */
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -91,9 +91,6 @@
#define MSR_IA32_MC0_CTL2 0x00000280
#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
-#define CMCI_EN (1ULL << 30)
-#define CMCI_THRESHOLD_MASK 0xffffULL
-
#define MSR_P6_PERFCTR0 0x000000c1
#define MSR_P6_PERFCTR1 0x000000c2
#define MSR_P6_EVNTSEL0 0x00000186
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -95,19 +95,19 @@ static void cmci_discover(int banks, int
rdmsrl(MSR_IA32_MCx_CTL2(i), val);
/* Already owned by someone else? */
- if (val & CMCI_EN) {
+ if (val & MCI_CTL2_CMCI_EN) {
if (test_and_clear_bit(i, owned) && !boot)
print_update("SHD", &hdr, i);
__clear_bit(i, __get_cpu_var(mce_poll_banks));
continue;
}
- val |= CMCI_EN | CMCI_THRESHOLD;
+ val |= MCI_CTL2_CMCI_EN | CMCI_THRESHOLD;
wrmsrl(MSR_IA32_MCx_CTL2(i), val);
rdmsrl(MSR_IA32_MCx_CTL2(i), val);
/* Did the enable bit stick? -- the bank supports CMCI */
- if (val & CMCI_EN) {
+ if (val & MCI_CTL2_CMCI_EN) {
if (!test_and_set_bit(i, owned) && !boot)
print_update("CMCI", &hdr, i);
__clear_bit(i, __get_cpu_var(mce_poll_banks));
@@ -155,7 +155,7 @@ void cmci_clear(void)
continue;
/* Disable CMCI */
rdmsrl(MSR_IA32_MCx_CTL2(i), val);
- val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK);
+ val &= ~(MCI_CTL2_CMCI_EN|MCI_CTL2_CMCI_THRESHOLD_MASK);
wrmsrl(MSR_IA32_MCx_CTL2(i), val);
__clear_bit(i, __get_cpu_var(mce_banks_owned));
}
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH -v3 1/2] x86, MCE, rename MSR_IA32_MCx_CTL2 value
@ 2010-06-08 6:09 Huang Ying
0 siblings, 0 replies; 4+ messages in thread
From: Huang Ying @ 2010-06-08 6:09 UTC (permalink / raw)
To: Ingo Molnar, H. Peter Anvin; +Cc: LKML, Andi Kleen, Hidetoshi Seto
Rename CMCI_EN to MCI_CTL2_CMCI_EN and CMCI_THRESHOLD_MASK to
MCI_CTL2_CMCI_THRESHOLD_MASK to make naming consistent.
Signed-off-by: Huang Ying <ying.huang@intel.com>
---
arch/x86/include/asm/mce.h | 4 ++++
arch/x86/include/asm/msr-index.h | 3 ---
arch/x86/kernel/cpu/mcheck/mce_intel.c | 8 ++++----
3 files changed, 8 insertions(+), 7 deletions(-)
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -38,6 +38,10 @@
#define MCM_ADDR_MEM 3 /* memory address */
#define MCM_ADDR_GENERIC 7 /* generic */
+/* CTL2 register defines */
+#define MCI_CTL2_CMCI_EN (1ULL << 30)
+#define MCI_CTL2_CMCI_THRESHOLD_MASK 0xffffULL
+
#define MCJ_CTX_MASK 3
#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
#define MCJ_CTX_RANDOM 0 /* inject context: random */
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -94,9 +94,6 @@
#define MSR_IA32_MC0_CTL2 0x00000280
#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
-#define CMCI_EN (1ULL << 30)
-#define CMCI_THRESHOLD_MASK 0xffffULL
-
#define MSR_P6_PERFCTR0 0x000000c1
#define MSR_P6_PERFCTR1 0x000000c2
#define MSR_P6_EVNTSEL0 0x00000186
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -95,19 +95,19 @@ static void cmci_discover(int banks, int
rdmsrl(MSR_IA32_MCx_CTL2(i), val);
/* Already owned by someone else? */
- if (val & CMCI_EN) {
+ if (val & MCI_CTL2_CMCI_EN) {
if (test_and_clear_bit(i, owned) && !boot)
print_update("SHD", &hdr, i);
__clear_bit(i, __get_cpu_var(mce_poll_banks));
continue;
}
- val |= CMCI_EN | CMCI_THRESHOLD;
+ val |= MCI_CTL2_CMCI_EN | CMCI_THRESHOLD;
wrmsrl(MSR_IA32_MCx_CTL2(i), val);
rdmsrl(MSR_IA32_MCx_CTL2(i), val);
/* Did the enable bit stick? -- the bank supports CMCI */
- if (val & CMCI_EN) {
+ if (val & MCI_CTL2_CMCI_EN) {
if (!test_and_set_bit(i, owned) && !boot)
print_update("CMCI", &hdr, i);
__clear_bit(i, __get_cpu_var(mce_poll_banks));
@@ -155,7 +155,7 @@ void cmci_clear(void)
continue;
/* Disable CMCI */
rdmsrl(MSR_IA32_MCx_CTL2(i), val);
- val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK);
+ val &= ~(MCI_CTL2_CMCI_EN|MCI_CTL2_CMCI_THRESHOLD_MASK);
wrmsrl(MSR_IA32_MCx_CTL2(i), val);
__clear_bit(i, __get_cpu_var(mce_banks_owned));
}
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2010-06-08 6:09 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-05-18 5:36 [PATCH -v3 0/2] x86, MCE, FIX MSR_IA32_MCI_CTL2_CMCI threshold setup Huang Ying
2010-05-18 5:36 ` [PATCH -v3 2/2] x86, MCE, fix MSR_IA32_MCI_CTL2 CMCI " Huang Ying
2010-05-18 5:36 ` [PATCH -v3 1/2] x86, MCE, rename MSR_IA32_MCx_CTL2 value Huang Ying
2010-06-08 6:09 Huang Ying
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®