* [PATCH -v3 2/2] x86, MCE, fix MSR_IA32_MCI_CTL2 CMCI threshold setup
@ 2010-06-08 6:09 Huang Ying
2010-06-11 6:04 ` [tip:x86/mce] x86, mce: Fix " tip-bot for Huang Ying
0 siblings, 1 reply; 3+ messages in thread
From: Huang Ying @ 2010-06-08 6:09 UTC (permalink / raw)
To: Ingo Molnar, H. Peter Anvin; +Cc: LKML, Andi Kleen, Hidetoshi Seto
It is reported that CMCI is not raised when number of corrected error
reaches preset threshold. After inspection, it is found that
MSR_IA32_MCI_CTL2 threshold field is not setup properly. This patch
fixed it.
Value of MCI_CTL2_CMCI_THRESHOLD_MASK is fixed according to x86_64
Software Developer's Manual too.
Reported-by: Shaohui Zheng <shaohui.zheng@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
---
arch/x86/include/asm/mce.h | 2 +-
arch/x86/kernel/cpu/mcheck/mce_intel.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -40,7 +40,7 @@
/* CTL2 register defines */
#define MCI_CTL2_CMCI_EN (1ULL << 30)
-#define MCI_CTL2_CMCI_THRESHOLD_MASK 0xffffULL
+#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
#define MCJ_CTX_MASK 3
#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -102,6 +102,7 @@ static void cmci_discover(int banks, int
continue;
}
+ val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
val |= MCI_CTL2_CMCI_EN | CMCI_THRESHOLD;
wrmsrl(MSR_IA32_MCx_CTL2(i), val);
rdmsrl(MSR_IA32_MCx_CTL2(i), val);
^ permalink raw reply [flat|nested] 3+ messages in thread
* [tip:x86/mce] x86, mce: Fix MSR_IA32_MCI_CTL2 CMCI threshold setup
2010-06-08 6:09 [PATCH -v3 2/2] x86, MCE, fix MSR_IA32_MCI_CTL2 CMCI threshold setup Huang Ying
@ 2010-06-11 6:04 ` tip-bot for Huang Ying
0 siblings, 0 replies; 3+ messages in thread
From: tip-bot for Huang Ying @ 2010-06-11 6:04 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-kernel, ying.huang, hpa, mingo, seto.hidetoshi, tglx,
shaohui.zheng
Commit-ID: 3c417588603e5411f29d22a40f3b5ff71529a4f0
Gitweb: http://git.kernel.org/tip/3c417588603e5411f29d22a40f3b5ff71529a4f0
Author: Huang Ying <ying.huang@intel.com>
AuthorDate: Tue, 8 Jun 2010 14:09:10 +0800
Committer: H. Peter Anvin <hpa@zytor.com>
CommitDate: Thu, 10 Jun 2010 21:27:36 -0700
x86, mce: Fix MSR_IA32_MCI_CTL2 CMCI threshold setup
It is reported that CMCI is not raised when number of corrected error
reaches preset threshold. After inspection, it is found that
MSR_IA32_MCI_CTL2 threshold field is not setup properly. This patch
fixed it.
Value of MCI_CTL2_CMCI_THRESHOLD_MASK is fixed according to x86_64
Software Developer's Manual too.
Reported-by: Shaohui Zheng <shaohui.zheng@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
LKML-Reference: <1275977350.3444.660.camel@yhuang-dev.sh.intel.com>
Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
---
arch/x86/include/asm/mce.h | 2 +-
arch/x86/kernel/cpu/mcheck/mce_intel.c | 1 +
2 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 82db1d8..c62c13c 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -40,7 +40,7 @@
/* CTL2 register defines */
#define MCI_CTL2_CMCI_EN (1ULL << 30)
-#define MCI_CTL2_CMCI_THRESHOLD_MASK 0xffffULL
+#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
#define MCJ_CTX_MASK 3
#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index faf7b29..6fcd093 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -102,6 +102,7 @@ static void cmci_discover(int banks, int boot)
continue;
}
+ val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
val |= MCI_CTL2_CMCI_EN | CMCI_THRESHOLD;
wrmsrl(MSR_IA32_MCx_CTL2(i), val);
rdmsrl(MSR_IA32_MCx_CTL2(i), val);
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH -v3 2/2] x86, MCE, fix MSR_IA32_MCI_CTL2 CMCI threshold setup
2010-05-18 5:36 [PATCH -v3 0/2] x86, MCE, FIX MSR_IA32_MCI_CTL2_CMCI " Huang Ying
@ 2010-05-18 5:36 ` Huang Ying
0 siblings, 0 replies; 3+ messages in thread
From: Huang Ying @ 2010-05-18 5:36 UTC (permalink / raw)
To: Ingo Molnar, H. Peter Anvin
Cc: linux-kernel, ying.huang, andi, Hidetoshi Seto
It is reported that CMCI is not raised when number of corrected error
reaches preset threshold. After inspection, it is found that
MSR_IA32_MCI_CTL2 threshold field is not setup properly. This patch
fixed it.
Value of MCI_CTL2_CMCI_THRESHOLD_MASK is fixed according to x86_64
Software Developer's Manual too.
Reported-by: Shaohui Zheng <shaohui.zheng@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
---
arch/x86/include/asm/mce.h | 2 +-
arch/x86/kernel/cpu/mcheck/mce_intel.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -40,7 +40,7 @@
/* CTL2 register defines */
#define MCI_CTL2_CMCI_EN (1ULL << 30)
-#define MCI_CTL2_CMCI_THRESHOLD_MASK 0xffffULL
+#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
#define MCJ_CTX_MASK 3
#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -102,6 +102,7 @@ static void cmci_discover(int banks, int
continue;
}
+ val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
val |= MCI_CTL2_CMCI_EN | CMCI_THRESHOLD;
wrmsrl(MSR_IA32_MCx_CTL2(i), val);
rdmsrl(MSR_IA32_MCx_CTL2(i), val);
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2010-06-11 6:04 UTC | newest]
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2010-06-08 6:09 [PATCH -v3 2/2] x86, MCE, fix MSR_IA32_MCI_CTL2 CMCI threshold setup Huang Ying
2010-06-11 6:04 ` [tip:x86/mce] x86, mce: Fix " tip-bot for Huang Ying
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2010-05-18 5:36 [PATCH -v3 0/2] x86, MCE, FIX MSR_IA32_MCI_CTL2_CMCI " Huang Ying
2010-05-18 5:36 ` [PATCH -v3 2/2] x86, MCE, fix MSR_IA32_MCI_CTL2 CMCI " Huang Ying
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