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From: Peter Zijlstra <peterz@infradead.org>
To: eranian@google.com
Cc: linux-kernel@vger.kernel.org, mingo@elte.hu, paulus@samba.org,
	davem@davemloft.net, fweisbec@gmail.com,
	perfmon2-devel@lists.sf.net, eranian@gmail.com,
	robert.richter@amd.com
Subject: Re: [PATCH] perf_events: fix bogus AMD64 generic TLB events
Date: Fri, 15 Oct 2010 15:54:34 +0200	[thread overview]
Message-ID: <1287150874.29097.1515.camel@twins> (raw)
In-Reply-To: <4cb85478.41e9d80a.44e2.3f00@mx.google.com>

On Fri, 2010-10-15 at 15:15 +0200, Stephane Eranian wrote:
> PERF_COUNT_HW_CACHE_DTLB:READ:MISS had a bogus umask value of 0 which
> counts nothing. Needed to be 0x7 (to count all possibilities).
> 
> PERF_COUNT_HW_CACHE_ITLB:READ:MISS had a bogus umask value of 0 which
> counts nothing. Needed to be 0x3 (to count all possibilities).
> 
> Signed-off-by: Stephane Eranian <eranian@google.com>

Thanks! tagged it for -stable as well.

  reply	other threads:[~2010-10-15 13:54 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-10-15 13:15 Stephane Eranian
2010-10-15 13:54 ` Peter Zijlstra [this message]
2010-10-18 19:18 ` [tip:perf/core] perf_events: Fix " tip-bot for Stephane Eranian

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