From: tip-bot for Stephane Eranian <eranian@google.com>
To: linux-tip-commits@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, eranian@google.com, hpa@zytor.com,
mingo@redhat.com, robert.richter@amd.com, a.p.zijlstra@chello.nl,
tglx@linutronix.de, mingo@elte.hu
Subject: [tip:perf/core] perf_events: Fix bogus AMD64 generic TLB events
Date: Mon, 18 Oct 2010 19:18:20 GMT [thread overview]
Message-ID: <tip-ba0cef3d149ce4db293c572bf36ed352b11ce7b9@git.kernel.org> (raw)
In-Reply-To: <4cb85478.41e9d80a.44e2.3f00@mx.google.com>
Commit-ID: ba0cef3d149ce4db293c572bf36ed352b11ce7b9
Gitweb: http://git.kernel.org/tip/ba0cef3d149ce4db293c572bf36ed352b11ce7b9
Author: Stephane Eranian <eranian@google.com>
AuthorDate: Fri, 15 Oct 2010 15:15:01 +0200
Committer: Ingo Molnar <mingo@elte.hu>
CommitDate: Mon, 18 Oct 2010 19:58:48 +0200
perf_events: Fix bogus AMD64 generic TLB events
PERF_COUNT_HW_CACHE_DTLB:READ:MISS had a bogus umask value of 0 which
counts nothing. Needed to be 0x7 (to count all possibilities).
PERF_COUNT_HW_CACHE_ITLB:READ:MISS had a bogus umask value of 0 which
counts nothing. Needed to be 0x3 (to count all possibilities).
Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Robert Richter <robert.richter@amd.com>
Cc: <stable@kernel.org> # as far back as it applies
LKML-Reference: <4cb85478.41e9d80a.44e2.3f00@mx.google.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/cpu/perf_event_amd.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index c2897b7..46d5844 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -52,7 +52,7 @@ static __initconst const u64 amd_hw_cache_event_ids
[ C(DTLB) ] = {
[ C(OP_READ) ] = {
[ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
- [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */
+ [ C(RESULT_MISS) ] = 0x0746, /* L1_DTLB_AND_L2_DLTB_MISS.ALL */
},
[ C(OP_WRITE) ] = {
[ C(RESULT_ACCESS) ] = 0,
@@ -66,7 +66,7 @@ static __initconst const u64 amd_hw_cache_event_ids
[ C(ITLB) ] = {
[ C(OP_READ) ] = {
[ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
- [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */
+ [ C(RESULT_MISS) ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */
},
[ C(OP_WRITE) ] = {
[ C(RESULT_ACCESS) ] = -1,
prev parent reply other threads:[~2010-10-18 19:18 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-10-15 13:15 [PATCH] perf_events: fix " Stephane Eranian
2010-10-15 13:54 ` Peter Zijlstra
2010-10-18 19:18 ` tip-bot for Stephane Eranian [this message]
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