Re: G400 behavior different, 2.2.18->2.4.0

Re: G400 behavior different, 2.2.18->2.4.0

[Chad Miller]

On Tue, Jan 16, 2001 at 10:40:51PM +0000, Petr Vandrovec wrote:
> [X] Output under 2.2.x is correct: '/25' for 32MB range. I have no idea
> why X complains about region D6000000-D7FFFFFF - can you look at
> '... regions behind bridge' when you boot 2.2.x (they are on 0:01.0
> device, AFAIK) ? Under 2.4.x you showed that prefetchable region is 
> D6000000-D8FFFFFF, which correctly covers 2.2.x framebuffer address
> (although it is not power of 2, but who knows...).

Here's the full 2.2 output of 'lspci -v':

#00:00.0 Host bridge: VIA Technologies, Inc. VT8371 [KX133] (rev 02)
#	Flags: bus master, medium devsel, latency 0
#	Memory at d0000000 (32-bit, prefetchable)
#	Capabilities: [a0] AGP version 2.0
#
#00:01.0 PCI bridge: VIA Technologies, Inc. VT8371 [KX133 AGP]  (prog-if \
#00 [Normal decode])
#	Flags: bus master, 66Mhz, medium devsel, latency 0
#	Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
#	Memory behind bridge: d4000000-d6ffffff
#	Prefetchable memory behind bridge: d7000000-d8ffffff
#	Capabilities: [80] Power Management version 2
#
#00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South] \
#(rev 22)
#	Subsystem: VIA Technologies, Inc. VT82C686/A PCI to ISA Bridge
#	Flags: bus master, stepping, medium devsel, latency 0
#
#00:07.1 IDE interface: VIA Technologies, Inc. Bus Master IDE (rev 10) \
#(prog-if 8a [Master SecP PriP])
#	Flags: bus master, medium devsel, latency 32
#	I/O ports at e000
#	Capabilities: [c0] Power Management version 2
#
#00:07.4 Host bridge: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] \
#(rev 30)
#	Flags: medium devsel
#	Capabilities: [68] Power Management version 2
#
#00:09.0 Ethernet controller: Intel Corporation 82557 [Ethernet Pro 100] \
#(rev 08)
#	Subsystem: Intel Corporation EtherExpress PRO/100+ Management Adapter
#	Flags: bus master, medium devsel, latency 32, IRQ 11
#	Memory at da100000 (32-bit, non-prefetchable)
#	I/O ports at ec00
#	Memory at da000000 (32-bit, non-prefetchable)
#	Capabilities: [dc] Power Management version 2
#
#01:00.0 VGA compatible controller: Matrox Graphics, Inc. MGA G400 AGP \
#(rev 05) (prog-if 00 [VGA])
#	Subsystem: Matrox Graphics, Inc. Millennium G400 MAX/Dual Head 32Mb
#	Flags: bus master, VGA palette snoop, medium devsel, latency 32, IRQ 10
#	Memory at d6000000 (32-bit, prefetchable)
#	Memory at d4000000 (32-bit, non-prefetchable)
#	Memory at d5000000 (32-bit, non-prefetchable)
#	Capabilities: [dc] Power Management version 2
#	Capabilities: [f0] AGP version 2.0


The diff from above 2.2.18 to 2.4.0:
3,4c3,4
< 	Memory at d0000000 (32-bit, prefetchable)
< 	Capabilities: [a0] AGP version 2.0
---
> 	Memory at d0000000 (32-bit, prefetchable) [size=64M]
> 	Capabilities: <available only to root>
11c11
< 	Capabilities: [80] Power Management version 2
---
> 	Capabilities: <available only to root>
19,20c19,20
< 	I/O ports at e000
< 	Capabilities: [c0] Power Management version 2
---
> 	I/O ports at e000 [size=16]
> 	Capabilities: <available only to root>
24c24
< 	Capabilities: [68] Power Management version 2
---
> 	Capabilities: <available only to root>
29,32c29,33
< 	Memory at da100000 (32-bit, non-prefetchable)
< 	I/O ports at ec00
< 	Memory at da000000 (32-bit, non-prefetchable)
< 	Capabilities: [dc] Power Management version 2
---
> 	Memory at da100000 (32-bit, non-prefetchable) [size=4K]
> 	I/O ports at ec00 [size=64]
> 	Memory at da000000 (32-bit, non-prefetchable) [size=1M]
> 	Expansion ROM at <unassigned> [disabled] [size=1M]
> 	Capabilities: <available only to root>
36,41c37,42
< 	Flags: bus master, VGA palette snoop, medium devsel, latency 32, IRQ 10
< 	Memory at d6000000 (32-bit, prefetchable)
< 	Memory at d4000000 (32-bit, non-prefetchable)
< 	Memory at d5000000 (32-bit, non-prefetchable)
< 	Capabilities: [dc] Power Management version 2
< 	Capabilities: [f0] AGP version 2.0
---
> 	Flags: bus master, VGA palette snoop, medium devsel, latency 64, IRQ 10
> 	Memory at d8000000 (32-bit, prefetchable) [size=16M]
> 	Memory at d4000000 (32-bit, non-prefetchable) [size=16K]
> 	Memory at d5000000 (32-bit, non-prefetchable) [size=8M]
> 	Expansion ROM at <unassigned> [disabled] [size=64K]
> 	Capabilities: <available only to root>
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Re: G400 behavior different, 2.2.18->2.4.0 (was: matroxfb o

[Petr Vandrovec]

On 16 Jan 01 at 15:55, Chad Miller wrote:
> (CC'd to lkml)
> 
> On Tue, Jan 16, 2001 at 07:31:33PM +0000, Petr Vandrovec wrote:
> > There is something wrong with your hardware. First region for G400 should
> > be 32MB, not 16MB (even if you have 16MB G400, which I doubt).
> 
> Ooo!  Here's an edited diff of 'lspci -v' under 2.2.18 versus 2.4.0:
> 
> 36,41c37,42
> <   Flags: bus master, VGA palette snoop, medium devsel, latency 32, IRQ 10
> <   Memory at d6000000 (32-bit, prefetchable)
> ---
> >   Flags: bus master, VGA palette snoop, medium devsel, latency 64, IRQ 10
> >   Memory at d8000000 (32-bit, prefetchable) [size=16M]

> Do you think any configuration parameters could affect this?  (I haven't
> paid as much attention to the evolution from 2.2 to 2.4 as I should've.)
> 
> Here's the diff of X' output, from 2.2.18 to 2.4.0:
> 
> 43c43
> < (--) PCI:*(1:0:0) Matrox MGA G400 AGP rev 5, Mem @ 0xd6000000/25, 0xd4000000/14, 0xd5000000/23
> ---
> > (--) PCI:*(1:0:0) Matrox MGA G400 AGP rev 5, Mem @ 0xd6000000/24, 0xd4000000/14, 0xd5000000/23
> 72,73d71
> < (WW) ****INVALID MEM ALLOCATION**** b: 0xd6000000 e: 0xd7ffffff correcting\a
> < (EE) Cannot find a replacement memory range

Output under 2.2.x is correct: '/25' for 32MB range. I have no idea
why X complains about region D6000000-D7FFFFFF - can you look at
'... regions behind bridge' when you boot 2.2.x (they are on 0:01.0
device, AFAIK) ? Under 2.4.x you showed that prefetchable region is 
D6000000-D8FFFFFF, which correctly covers 2.2.x framebuffer address
(although it is not power of 2, but who knows...).

You should see D4000000-D5FFFFFF as non-prefetchable memory behind bridge,
and D6000000-D7FFFFFF as prefetchable memory behind bridge.
                                        Best regards,
                                                Petr Vandrovec
                                                vandrove@vc.cvut.cz
                                                
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