* [PATCH v3 0/5] pinctrl: samsung: exynos9 cleanups and fixes [not found] <CGME20251202093024epcas2p1567dddf09e3599867e9dc14a9a234d38@epcas2p1.samsung.com> @ 2025-12-02 9:36 ` Youngmin Nam [not found] ` <CGME20251202093026epcas2p28ddfd32305695df996841fd73b231b6b@epcas2p2.samsung.com> ` (4 more replies) 0 siblings, 5 replies; 19+ messages in thread From: Youngmin Nam @ 2025-12-02 9:36 UTC (permalink / raw) To: krzk, s.nawrocki, alim.akhtar, linus.walleij, peter.griffin, semen.protsenko, ivo.ivanov.ivanov1 Cc: ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel, Youngmin Nam Several SoCs carried near-duplicate pin bank macro families, making tables verbose and hard to share when only the bank type (alive/off) differs. GS101 had its own helpers even though the newer EXYNOS9_* helpers cover the same semantics, including per-bank filter control (FLTCON) offsets. Some pin-bank tables didn't match the SoC TRMs (bank type, EINT class, or bank names), and FLTCON wasn't always at a contiguous offset from EINT. This series does - Consolidate on EXYNOS9_* pin-bank macros. Pass bank_type explicitly. - Fix table errors on Exynos2200/7885/8890/8895 per TRM. - Add explicit per-bank FLTCON offsets and update affected tables. - Drop GS101-specific macros in favor of EXYNOS9_*. - Rename gs101_pinctrl_{suspend,resume} -> exynos9_pinctrl_{suspend,resume}. This series was based on the pinctrl/samsung tree [1]. I tested on Exynos850 through boot and verified the pin values as follows: $:/sys/kernel/debug/pinctrl/139b0000.pinctrl-samsung-pinctrl# cat pins registered pins: 42 pin 0 (gpg0-0) 0:gpg0 CON(0x0) DAT(0x0) PUD(0x1) DRV(0x2) CON_PDN(0x2) PUD_PDN(0x1) pin 1 (gpg0-1) 1:gpg0 CON(0x0) DAT(0x0) PUD(0x1) DRV(0x2) CON_PDN(0x2) PUD_PDN(0x1) ... Additional testing on the affected Exynos9-era platforms would be appreciated. [1] https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git Changes in v2: - Added base tree for this series (pinctrl/samsung). - Renamed the macro parameter from 'types' to 'bank_type' for clarity (struct member remains 'type'). - Reflowed commit messages (wrap at ~72 cols). - Replaced non-ASCII characters with ASCII equivalents. - Collected tags: Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Tested-by: Sam Protsenko <semen.protsenko@linaro.org> - Normalized hex literals to lowercase and removed double spaces. - Aligned backslashes in macro definitions to form a vertical column for readability. - Added missing mailing lists (including linux-kernel) to Cc per scripts/get_maintainer.pl. Changes in v3: - Collected tags: Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> (tested on Pixel6/gs101) Youngmin Nam (5): pinctrl: samsung: Consolidate pin-bank macros under EXYNOS9_* and pass bank_type explicitly pinctrl: samsung: fix incorrect pin-bank entries on Exynos2200/7885/8890/8895 pinctrl: samsung: add per-bank FLTCON offset to EXYNOS9_PIN_BANK_* and fix tables pinctrl: samsung: fold GS101 pin-bank macros into EXYNOS9_* pinctrl: samsung: rename gs101_pinctrl_* to exynos9_pinctrl_* .../pinctrl/samsung/pinctrl-exynos-arm64.c | 1069 ++++++++--------- drivers/pinctrl/samsung/pinctrl-exynos.c | 4 +- drivers/pinctrl/samsung/pinctrl-exynos.h | 97 +- drivers/pinctrl/samsung/pinctrl-samsung.h | 4 +- 4 files changed, 562 insertions(+), 612 deletions(-) -- 2.52.0 ^ permalink raw reply [flat|nested] 19+ messages in thread
[parent not found: <CGME20251202093026epcas2p28ddfd32305695df996841fd73b231b6b@epcas2p2.samsung.com>]
* [PATCH v3 1/5] pinctrl: samsung: Consolidate pin-bank macros under EXYNOS9_* and pass bank_type explicitly [not found] ` <CGME20251202093026epcas2p28ddfd32305695df996841fd73b231b6b@epcas2p2.samsung.com> @ 2025-12-02 9:36 ` Youngmin Nam 2025-12-17 4:28 ` Alim Akhtar 2025-12-28 11:40 ` Krzysztof Kozlowski 0 siblings, 2 replies; 19+ messages in thread From: Youngmin Nam @ 2025-12-02 9:36 UTC (permalink / raw) To: krzk, s.nawrocki, alim.akhtar, linus.walleij, peter.griffin, semen.protsenko, ivo.ivanov.ivanov1 Cc: ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel, Youngmin Nam Modern Exynos platforms have several near-duplicate pin-bank macro families (EXYNOS850_*, EXYNOS8895_*, EXYNOS7870_*), which makes tables verbose and harder to share across SoCs that differ only by bank_type (alive/off) layout. This patch unifies them into one EXYNOS9_* macro family and makes the bank_type an explicit argument. The common 850-era bank types are also renamed to 'exynos9_bank_type_{alive,off}' to reflect their reuse on later Exynos 9xxx-generation parts. Naming rationale: - Use of the EXYNOS9_* prefix indicates that these macros target current Exynos generations sharing the same register layout and EINT wiring model. Compared to SoC-specific prefixes (EXYNOS850_*, EXYNOS8895_*), EXYNOS9_* is clearer and more future-proof for modern parts. Key changes: - Introduce: - 'EXYNOS9_PIN_BANK_EINTN(bank_type, pins, reg, id)' - 'EXYNOS9_PIN_BANK_EINTG(bank_type, pins, reg, id, offs)' - 'EXYNOS9_PIN_BANK_EINTW(bank_type, pins, reg, id, offs)' - Rename: - 'exynos850_bank_type_alive'-> 'exynos9_bank_type_alive' - 'exynos850_bank_type_off' -> 'exynos9_bank_type_off' - Convert pin-bank tables for: - Exynos2200, 7870, 7885, 850, 990, 9810, 8890, 8895, AutoV9, AutoV920, FSD - Update GS101/EXYNOSV920 helpers to reference 'exynos9_bank_type_*' instead of the old exynos850 names. - Standardize on EXYNOS9_* macros while keeping SoC-specific '*_bank_type_*' when layouts differ (e.g., 7870/8895). No functional change intended. Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Tested-by: Sam Protsenko <semen.protsenko@linaro.org> --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 785 +++++++++--------- drivers/pinctrl/samsung/pinctrl-exynos.h | 49 +- 2 files changed, 402 insertions(+), 432 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 627dca504d7a..d11b2d4ca913 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -53,7 +53,7 @@ static const struct samsung_pin_bank_type exynos7870_bank_type_alive = { * Bank type for non-alive type. Bit fields: * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 */ -static const struct samsung_pin_bank_type exynos850_bank_type_off = { +static const struct samsung_pin_bank_type exynos9_bank_type_off = { .fld_width = { 4, 1, 4, 4, 2, 4, }, .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, }; @@ -62,7 +62,7 @@ static const struct samsung_pin_bank_type exynos850_bank_type_off = { * Bank type for alive type. Bit fields: * CON: 4, DAT: 1, PUD: 4, DRV: 4 */ -static const struct samsung_pin_bank_type exynos850_bank_type_alive = { +static const struct samsung_pin_bank_type exynos9_bank_type_alive = { .fld_width = { 4, 1, 4, 4, }, .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, }; @@ -90,11 +90,11 @@ static atomic_t exynos_shared_retention_refcnt; /* pin banks of exynos2200 pin-controller - ALIVE */ static const struct samsung_pin_bank_data exynos2200_pin_banks0[] __initconst = { - EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00), - EXYNOS850_PIN_BANK_EINTW(8, 0x20, "gpa1", 0x04), - EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa2", 0x08), - EXYNOS850_PIN_BANK_EINTW(8, 0x60, "gpa3", 0x0c), - EXYNOS850_PIN_BANK_EINTW(2, 0x80, "gpa4", 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x0, "gpa0", 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x20, "gpa1", 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x40, "gpa2", 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x60, "gpa3", 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x80, "gpa4", 0x10), EXYNOS_PIN_BANK_EINTN(4, 0xa0, "gpq0"), EXYNOS_PIN_BANK_EINTN(2, 0xc0, "gpq1"), EXYNOS_PIN_BANK_EINTN(2, 0xe0, "gpq2"), @@ -102,90 +102,90 @@ static const struct samsung_pin_bank_data exynos2200_pin_banks0[] __initconst = /* pin banks of exynos2200 pin-controller - CMGP */ static const struct samsung_pin_bank_data exynos2200_pin_banks1[] __initconst = { - EXYNOS850_PIN_BANK_EINTW(2, 0x0, "gpm0", 0x00), - EXYNOS850_PIN_BANK_EINTW(2, 0x20, "gpm1", 0x04), - EXYNOS850_PIN_BANK_EINTW(2, 0x40, "gpm2", 0x08), - EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpm3", 0x0c), - EXYNOS850_PIN_BANK_EINTW(2, 0x80, "gpm4", 0x10), - EXYNOS850_PIN_BANK_EINTW(2, 0xa0, "gpm5", 0x14), - EXYNOS850_PIN_BANK_EINTW(2, 0xc0, "gpm6", 0x18), - EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpm7", 0x1c), - EXYNOS850_PIN_BANK_EINTW(2, 0x100, "gpm8", 0x20), - EXYNOS850_PIN_BANK_EINTW(2, 0x120, "gpm9", 0x24), - EXYNOS850_PIN_BANK_EINTW(2, 0x140, "gpm10", 0x28), - EXYNOS850_PIN_BANK_EINTW(2, 0x160, "gpm11", 0x2c), - EXYNOS850_PIN_BANK_EINTW(2, 0x180, "gpm12", 0x30), - EXYNOS850_PIN_BANK_EINTW(2, 0x1a0, "gpm13", 0x34), - EXYNOS850_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38), - EXYNOS850_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c), - EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40), - EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44), - EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm20", 0x48), - EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm21", 0x4c), - EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm22", 0x50), - EXYNOS850_PIN_BANK_EINTW(1, 0x2a0, "gpm23", 0x54), - EXYNOS850_PIN_BANK_EINTW(1, 0x2c0, "gpm24", 0x58), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x0, "gpm0", 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x20, "gpm1", 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x40, "gpm2", 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x60, "gpm3", 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x80, "gpm4", 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0xa0, "gpm5", 0x14), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0xc0, "gpm6", 0x18), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0xe0, "gpm7", 0x1c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x100, "gpm8", 0x20), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x120, "gpm9", 0x24), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x140, "gpm10", 0x28), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x160, "gpm11", 0x2c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x180, "gpm12", 0x30), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x1a0, "gpm13", 0x34), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1c0, "gpm14", 0x38), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1e0, "gpm15", 0x3c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x200, "gpm16", 0x40), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x220, "gpm17", 0x44), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x240, "gpm20", 0x48), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x260, "gpm21", 0x4c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x280, "gpm22", 0x50), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x2a0, "gpm23", 0x54), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x2c0, "gpm24", 0x58), }; /* pin banks of exynos2200 pin-controller - HSI1 */ static const struct samsung_pin_bank_data exynos2200_pin_banks2[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpf0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0, "gpf0", 0x00), }; /* pin banks of exynos2200 pin-controller - UFS */ static const struct samsung_pin_bank_data exynos2200_pin_banks3[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpf1", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x0, "gpf1", 0x00), }; /* pin banks of exynos2200 pin-controller - HSI1UFS */ static const struct samsung_pin_bank_data exynos2200_pin_banks4[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gpf2", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x0, "gpf2", 0x00), }; /* pin banks of exynos2200 pin-controller - PERIC0 */ static const struct samsung_pin_bank_data exynos2200_pin_banks5[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpb0", 0x00), - EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpb1", 0x04), - EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpb2", 0x08), - EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpb3", 0x0c), - EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10), - EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpc0", 0x14), - EXYNOS850_PIN_BANK_EINTG(2, 0xc0, "gpc1", 0x18), - EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpc2", 0x1c), - EXYNOS850_PIN_BANK_EINTG(7, 0x100, "gpg1", 0x20), - EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpg2", 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0, "gpb0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x20, "gpb1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x40, "gpb2", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x60, "gpb3", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x80, "gpp4", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0xa0, "gpc0", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0xc0, "gpc1", 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0xe0, "gpc2", 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x100, "gpg1", 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x120, "gpg2", 0x24), }; /* pin banks of exynos2200 pin-controller - PERIC1 */ static const struct samsung_pin_bank_data exynos2200_pin_banks6[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpp7", 0x00), - EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp8", 0x04), - EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp9", 0x08), - EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpp10", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0, "gpp7", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x20, "gpp8", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x40, "gpp9", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x60, "gpp10", 0x0c), }; /* pin banks of exynos2200 pin-controller - PERIC2 */ static const struct samsung_pin_bank_data exynos2200_pin_banks7[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpp0", 0x00), - EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04), - EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08), - EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpp3", 0x0c), - EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp5", 0x10), - EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp6", 0x14), - EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp11", 0x18), - EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpc3", 0x1c), - EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpc4", 0x20), - EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpc5", 0x24), - EXYNOS850_PIN_BANK_EINTG(2, 0x140, "gpc6", 0x28), - EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpc7", 0x2c), - EXYNOS850_PIN_BANK_EINTG(2, 0x180, "gpc8", 0x30), - EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpc9", 0x34), - EXYNOS850_PIN_BANK_EINTG(5, 0x1c0, "gpg0", 0x38), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0, "gpp0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x20, "gpp1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x40, "gpp2", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x60, "gpp3", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x80, "gpp5", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0xa0, "gpp6", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0xc0, "gpp11", 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0xe0, "gpc3", 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x100, "gpc4", 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x120, "gpc5", 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x140, "gpc6", 0x28), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x160, "gpc7", 0x2c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x180, "gpc8", 0x30), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x1a0, "gpc9", 0x34), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x1c0, "gpg0", 0x38), }; /* pin banks of exynos2200 pin-controller - VTS */ static const struct samsung_pin_bank_data exynos2200_pin_banks8[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpv0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x0, "gpv0", 0x00), }; static const struct samsung_pin_ctrl exynos2200_pin_ctrl[] = { @@ -638,70 +638,70 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { /* pin banks of exynos7870 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynos7870_pin_banks0[] __initconst = { - EXYNOS7870_PIN_BANK_EINTN(6, 0x000, "etc0"), - EXYNOS7870_PIN_BANK_EINTN(3, 0x020, "etc1"), - EXYNOS7870_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00), - EXYNOS7870_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04), - EXYNOS7870_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08), - EXYNOS7870_PIN_BANK_EINTN(2, 0x0c0, "gpq0"), + EXYNOS9_PIN_BANK_EINTN(exynos7870_bank_type_alive, 6, 0x000, "etc0"), + EXYNOS9_PIN_BANK_EINTN(exynos7870_bank_type_alive, 3, 0x020, "etc1"), + EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x040, "gpa0", 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x060, "gpa1", 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x080, "gpa2", 0x08), + EXYNOS9_PIN_BANK_EINTN(exynos7870_bank_type_alive, 2, 0x0c0, "gpq0"), }; /* pin banks of exynos7870 pin-controller 1 (DISPAUD) */ static const struct samsung_pin_bank_data exynos7870_pin_banks1[] __initconst = { - EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpz0", 0x00), - EXYNOS8895_PIN_BANK_EINTG(6, 0x020, "gpz1", 0x04), - EXYNOS8895_PIN_BANK_EINTG(4, 0x040, "gpz2", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x000, "gpz0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x020, "gpz1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x040, "gpz2", 0x08), }; /* pin banks of exynos7870 pin-controller 2 (ESE) */ static const struct samsung_pin_bank_data exynos7870_pin_banks2[] __initconst = { - EXYNOS8895_PIN_BANK_EINTG(5, 0x000, "gpc7", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x000, "gpc7", 0x00), }; /* pin banks of exynos7870 pin-controller 3 (FSYS) */ static const struct samsung_pin_bank_data exynos7870_pin_banks3[] __initconst = { - EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpr0", 0x00), - EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), - EXYNOS8895_PIN_BANK_EINTG(2, 0x040, "gpr2", 0x08), - EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpr3", 0x0c), - EXYNOS8895_PIN_BANK_EINTG(6, 0x080, "gpr4", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x000, "gpr0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x020, "gpr1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x040, "gpr2", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x060, "gpr3", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x080, "gpr4", 0x10), }; /* pin banks of exynos7870 pin-controller 4 (MIF) */ static const struct samsung_pin_bank_data exynos7870_pin_banks4[] __initconst = { - EXYNOS8895_PIN_BANK_EINTG(2, 0x000, "gpm0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x000, "gpm0", 0x00), }; /* pin banks of exynos7870 pin-controller 5 (NFC) */ static const struct samsung_pin_bank_data exynos7870_pin_banks5[] __initconst = { - EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpc2", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x000, "gpc2", 0x00), }; /* pin banks of exynos7870 pin-controller 6 (TOP) */ static const struct samsung_pin_bank_data exynos7870_pin_banks6[] __initconst = { - EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpb0", 0x00), - EXYNOS8895_PIN_BANK_EINTG(3, 0x020, "gpc0", 0x04), - EXYNOS8895_PIN_BANK_EINTG(4, 0x040, "gpc1", 0x08), - EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpc4", 0x0c), - EXYNOS8895_PIN_BANK_EINTG(2, 0x080, "gpc5", 0x10), - EXYNOS8895_PIN_BANK_EINTG(4, 0x0a0, "gpc6", 0x14), - EXYNOS8895_PIN_BANK_EINTG(2, 0x0c0, "gpc8", 0x18), - EXYNOS8895_PIN_BANK_EINTG(2, 0x0e0, "gpc9", 0x1c), - EXYNOS8895_PIN_BANK_EINTG(7, 0x100, "gpd1", 0x20), - EXYNOS8895_PIN_BANK_EINTG(6, 0x120, "gpd2", 0x24), - EXYNOS8895_PIN_BANK_EINTG(8, 0x140, "gpd3", 0x28), - EXYNOS8895_PIN_BANK_EINTG(7, 0x160, "gpd4", 0x2c), - EXYNOS8895_PIN_BANK_EINTG(3, 0x1a0, "gpe0", 0x34), - EXYNOS8895_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), - EXYNOS8895_PIN_BANK_EINTG(2, 0x1e0, "gpf1", 0x3c), - EXYNOS8895_PIN_BANK_EINTG(2, 0x200, "gpf2", 0x40), - EXYNOS8895_PIN_BANK_EINTG(4, 0x220, "gpf3", 0x44), - EXYNOS8895_PIN_BANK_EINTG(5, 0x240, "gpf4", 0x48), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x000, "gpb0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x020, "gpc0", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x040, "gpc1", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x060, "gpc4", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x080, "gpc5", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x0a0, "gpc6", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0c0, "gpc8", 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0e0, "gpc9", 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 7, 0x100, "gpd1", 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x120, "gpd2", 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x140, "gpd3", 0x28), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 7, 0x160, "gpd4", 0x2c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x1a0, "gpe0", 0x34), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x1c0, "gpf0", 0x38), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x1e0, "gpf1", 0x3c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x200, "gpf2", 0x40), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x220, "gpf3", 0x44), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x240, "gpf4", 0x48), }; /* pin banks of exynos7870 pin-controller 7 (TOUCH) */ static const struct samsung_pin_bank_data exynos7870_pin_banks7[] __initconst = { - EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpc3", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x000, "gpc3", 0x00), }; static const struct samsung_pin_ctrl exynos7870_pin_ctrl[] __initconst = { @@ -770,46 +770,46 @@ const struct samsung_pinctrl_of_match_data exynos7870_of_data __initconst = { static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = { EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"), EXYNOS_PIN_BANK_EINTN(3, 0x020, "etc1"), - EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00), - EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04), - EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08), - EXYNOS850_PIN_BANK_EINTW(5, 0x0a0, "gpq0", 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x040, "gpa0", 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x060, "gpa1", 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x080, "gpa2", 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 5, 0x0a0, "gpq0", 0x0c), }; /* pin banks of exynos7885 pin-controller 1 (DISPAUD) */ static const struct samsung_pin_bank_data exynos7885_pin_banks1[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), - EXYNOS850_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04), - EXYNOS850_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x000, "gpb0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x020, "gpb1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x040, "gpb2", 0x08), }; /* pin banks of exynos7885 pin-controller 2 (FSYS) */ static const struct samsung_pin_bank_data exynos7885_pin_banks2[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), - EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf2", 0x04), - EXYNOS850_PIN_BANK_EINTG(6, 0x040, "gpf3", 0x08), - EXYNOS850_PIN_BANK_EINTG(6, 0x060, "gpf4", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpf0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpf2", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x040, "gpf3", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x060, "gpf4", 0x0c), }; /* pin banks of exynos7885 pin-controller 3 (TOP) */ static const struct samsung_pin_bank_data exynos7885_pin_banks3[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpp0", 0x00), - EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gpg0", 0x04), - EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), - EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c), - EXYNOS850_PIN_BANK_EINTG(3, 0x080, "gpp3", 0x10), - EXYNOS850_PIN_BANK_EINTG(6, 0x0a0, "gpp4", 0x14), - EXYNOS850_PIN_BANK_EINTG(4, 0x0c0, "gpp5", 0x18), - EXYNOS850_PIN_BANK_EINTG(5, 0x0e0, "gpp6", 0x1c), - EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpp7", 0x20), - EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp8", 0x24), - EXYNOS850_PIN_BANK_EINTG(8, 0x140, "gpg1", 0x28), - EXYNOS850_PIN_BANK_EINTG(8, 0x160, "gpg2", 0x2c), - EXYNOS850_PIN_BANK_EINTG(8, 0x180, "gpg3", 0x30), - EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpg4", 0x34), - EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpc0", 0x38), - EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpc1", 0x3c), - EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpc2", 0x40), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpp0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x020, "gpg0", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x040, "gpp1", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x060, "gpp2", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x080, "gpp3", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x0a0, "gpp4", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0c0, "gpp5", 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x0e0, "gpp6", 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x100, "gpp7", 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x120, "gpp8", 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x140, "gpg1", 0x28), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x160, "gpg2", 0x2c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x180, "gpg3", 0x30), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x1a0, "gpg4", 0x34), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x1c0, "gpc0", 0x38), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x1e0, "gpc1", 0x3c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x200, "gpc2", 0x40), }; static const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = { @@ -850,59 +850,59 @@ const struct samsung_pinctrl_of_match_data exynos7885_of_data __initconst = { /* pin banks of exynos850 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), - EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), - EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), - EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), - EXYNOS850_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10), - EXYNOS850_PIN_BANK_EINTN(3, 0x0a0, "gpq0"), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x000, "gpa0", 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x020, "gpa1", 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x040, "gpa2", 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x060, "gpa3", 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 4, 0x080, "gpa4", 0x10), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 3, 0x0a0, "gpq0"), }; /* pin banks of exynos850 pin-controller 1 (CMGP) */ static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), - EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), - EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), - EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0c), - EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), - EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpm5", 0x14), - EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpm6", 0x18), - EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpm7", 0x1c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x000, "gpm0", 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x020, "gpm1", 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x040, "gpm2", 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x060, "gpm3", 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x080, "gpm4", 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0a0, "gpm5", 0x14), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0c0, "gpm6", 0x18), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0e0, "gpm7", 0x1c), }; /* pin banks of exynos850 pin-controller 2 (AUD) */ static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), - EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x000, "gpb0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x020, "gpb1", 0x04), }; /* pin banks of exynos850 pin-controller 3 (HSI) */ static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x000, "gpf2", 0x00), }; /* pin banks of exynos850 pin-controller 4 (CORE) */ static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), - EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpf0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpf1", 0x04), }; /* pin banks of exynos850 pin-controller 5 (PERI) */ static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00), - EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04), - EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), - EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c), - EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10), - EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpg2", 0x14), - EXYNOS850_PIN_BANK_EINTG(1, 0x0c0, "gpg3", 0x18), - EXYNOS850_PIN_BANK_EINTG(3, 0x0e0, "gpc0", 0x1c), - EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x000, "gpg0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x020, "gpp0", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x040, "gpp1", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x060, "gpp2", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpg1", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0a0, "gpg2", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 1, 0x0c0, "gpg3", 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x0e0, "gpc0", 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x100, "gpc1", 0x20), }; static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { @@ -946,98 +946,97 @@ const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { /* pin banks of exynos990 pin-controller 0 (ALIVE) */ static struct samsung_pin_bank_data exynos990_pin_banks0[] = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), - EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), - EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), - EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), - EXYNOS850_PIN_BANK_EINTW(2, 0x080, "gpa4", 0x10), - EXYNOS850_PIN_BANK_EINTN(7, 0x0A0, "gpq0"), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x000, "gpa0", 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x020, "gpa1", 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x040, "gpa2", 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x060, "gpa3", 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x080, "gpa4", 0x10), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 7, 0x0a0, "gpq0"), }; /* pin banks of exynos990 pin-controller 1 (CMGP) */ static struct samsung_pin_bank_data exynos990_pin_banks1[] = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS850_PIN_BANK_EINTN(1, 0x000, "gpm0"), - EXYNOS850_PIN_BANK_EINTN(1, 0x020, "gpm1"), - EXYNOS850_PIN_BANK_EINTN(1, 0x040, "gpm2"), - EXYNOS850_PIN_BANK_EINTN(1, 0x060, "gpm3"), - EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x00), - EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x04), - EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x08), - EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x0c), - EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x10), - EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x14), - EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x18), - EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x1c), - EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x20), - EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x24), - EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x28), - EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x2c), - EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x30), - EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x34), - EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x38), - EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x3c), - EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x40), - EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x44), - EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x48), - EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x4c), - EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x50), - EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x54), - EXYNOS850_PIN_BANK_EINTW(1, 0x340, "gpm26", 0x58), - EXYNOS850_PIN_BANK_EINTW(1, 0x360, "gpm27", 0x5c), - EXYNOS850_PIN_BANK_EINTW(1, 0x380, "gpm28", 0x60), - EXYNOS850_PIN_BANK_EINTW(1, 0x3A0, "gpm29", 0x64), - EXYNOS850_PIN_BANK_EINTW(1, 0x3C0, "gpm30", 0x68), - EXYNOS850_PIN_BANK_EINTW(1, 0x3E0, "gpm31", 0x6c), - EXYNOS850_PIN_BANK_EINTW(1, 0x400, "gpm32", 0x70), - EXYNOS850_PIN_BANK_EINTW(1, 0x420, "gpm33", 0x74), - + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 1, 0x000, "gpm0"), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 1, 0x020, "gpm1"), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 1, 0x040, "gpm2"), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 1, 0x060, "gpm3"), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x080, "gpm4", 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0a0, "gpm5", 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0c0, "gpm6", 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0e0, "gpm7", 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x100, "gpm8", 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x120, "gpm9", 0x14), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x140, "gpm10", 0x18), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x160, "gpm11", 0x1c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x180, "gpm12", 0x20), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1a0, "gpm13", 0x24), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1c0, "gpm14", 0x28), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1e0, "gpm15", 0x2c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x200, "gpm16", 0x30), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x220, "gpm17", 0x34), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x240, "gpm18", 0x38), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x260, "gpm19", 0x3c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x280, "gpm20", 0x40), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x2a0, "gpm21", 0x44), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x2c0, "gpm22", 0x48), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x2e0, "gpm23", 0x4c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x300, "gpm24", 0x50), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x320, "gpm25", 0x54), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x340, "gpm26", 0x58), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x360, "gpm27", 0x5c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x380, "gpm28", 0x60), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x3a0, "gpm29", 0x64), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x3c0, "gpm30", 0x68), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x3e0, "gpm31", 0x6c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x400, "gpm32", 0x70), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x420, "gpm33", 0x74), }; /* pin banks of exynos990 pin-controller 2 (HSI1) */ static struct samsung_pin_bank_data exynos990_pin_banks2[] = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), - EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04), - EXYNOS850_PIN_BANK_EINTG(3, 0x040, "gpf2", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpf0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x020, "gpf1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x040, "gpf2", 0x08), }; /* pin banks of exynos990 pin-controller 3 (HSI2) */ static struct samsung_pin_bank_data exynos990_pin_banks3[] = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf3", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x000, "gpf3", 0x00), }; /* pin banks of exynos990 pin-controller 4 (PERIC0) */ static struct samsung_pin_bank_data exynos990_pin_banks4[] = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), - EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), - EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), - EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp3", 0x0C), - EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp4", 0x10), - EXYNOS850_PIN_BANK_EINTG(2, 0x0A0, "gpg0", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpp2", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpp3", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpp4", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x0a0, "gpg0", 0x14), }; /* pin banks of exynos990 pin-controller 5 (PERIC1) */ static struct samsung_pin_bank_data exynos990_pin_banks5[] = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp5", 0x00), - EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp6", 0x04), - EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp7", 0x08), - EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp8", 0x0C), - EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp9", 0x10), - EXYNOS850_PIN_BANK_EINTG(6, 0x0A0, "gpc0", 0x14), - EXYNOS850_PIN_BANK_EINTG(4, 0x0C0, "gpg1", 0x18), - EXYNOS850_PIN_BANK_EINTG(8, 0x0E0, "gpb0", 0x1C), - EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb1", 0x20), - EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb2", 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp5", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp6", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpp7", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpp8", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpp9", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x0a0, "gpc0", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0c0, "gpg1", 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0e0, "gpb0", 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x100, "gpb1", 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x120, "gpb2", 0x24), }; /* pin banks of exynos990 pin-controller 6 (VTS) */ static struct samsung_pin_bank_data exynos990_pin_banks6[] = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpv0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x000, "gpv0", 0x00), }; static const struct samsung_pin_ctrl exynos990_pin_ctrl[] __initconst = { @@ -1085,88 +1084,88 @@ const struct samsung_pinctrl_of_match_data exynos990_of_data __initconst = { /* pin banks of exynos9810 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynos9810_pin_banks0[] __initconst = { - EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc1"), - EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), - EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), - EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), - EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c), - EXYNOS850_PIN_BANK_EINTN(6, 0x0A0, "gpq0"), - EXYNOS850_PIN_BANK_EINTW(2, 0x0C0, "gpa4", 0x10), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 6, 0x000, "etc1"), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x020, "gpa0", 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x040, "gpa1", 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x060, "gpa2", 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x080, "gpa3", 0x0c), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 6, 0x0a0, "gpq0"), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x0c0, "gpa4", 0x10), }; /* pin banks of exynos9810 pin-controller 1 (AUD) */ static const struct samsung_pin_bank_data exynos9810_pin_banks1[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), - EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04), - EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpb2", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x000, "gpb0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpb1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x040, "gpb2", 0x08), }; /* pin banks of exynos9810 pin-controller 2 (CHUB) */ static const struct samsung_pin_bank_data exynos9810_pin_banks2[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00), - EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gph1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gph0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x020, "gph1", 0x04), }; /* pin banks of exynos9810 pin-controller 3 (CMGP) */ static const struct samsung_pin_bank_data exynos9810_pin_banks3[] __initconst = { - EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), - EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), - EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), - EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), - EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), - EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), - EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), - EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), - EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm10", 0x20), - EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm11", 0x24), - EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm12", 0x28), - EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm13", 0x2C), - EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm14", 0x30), - EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm15", 0x34), - EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm16", 0x38), - EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm17", 0x3C), - EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm40", 0x40), - EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm41", 0x44), - EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm42", 0x48), - EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm43", 0x4C), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x000, "gpm0", 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x020, "gpm1", 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x040, "gpm2", 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x060, "gpm3", 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x080, "gpm4", 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0a0, "gpm5", 0x14), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0c0, "gpm6", 0x18), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0e0, "gpm7", 0x1c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x100, "gpm10", 0x20), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x120, "gpm11", 0x24), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x140, "gpm12", 0x28), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x160, "gpm13", 0x2c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x180, "gpm14", 0x30), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1a0, "gpm15", 0x34), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1c0, "gpm16", 0x38), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1e0, "gpm17", 0x3c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x200, "gpm40", 0x40), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x220, "gpm41", 0x44), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x240, "gpm42", 0x48), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x260, "gpm43", 0x4c), }; /* pin banks of exynos9810 pin-controller 4 (FSYS0) */ static const struct samsung_pin_bank_data exynos9810_pin_banks4[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x000, "gpf0", 0x00), }; /* pin banks of exynos9810 pin-controller 5 (FSYS1) */ static const struct samsung_pin_bank_data exynos9810_pin_banks5[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpf1", 0x00), - EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf2", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x000, "gpf1", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x020, "gpf2", 0x04), }; /* pin banks of exynos9810 pin-controller 6 (PERIC0) */ static const struct samsung_pin_bank_data exynos9810_pin_banks6[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), - EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), - EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), - EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp3", 0x0C), - EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), - EXYNOS850_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), - EXYNOS850_PIN_BANK_EINTG(8, 0x0C0, "gpg2", 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpp2", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x060, "gpp3", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpg0", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0a0, "gpg1", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0c0, "gpg2", 0x18), }; /* pin banks of exynos9810 pin-controller 7 (PERIC1) */ static const struct samsung_pin_bank_data exynos9810_pin_banks7[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp4", 0x00), - EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp5", 0x04), - EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp6", 0x08), - EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C), - EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10), - EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), - EXYNOS850_PIN_BANK_EINTG(7, 0x0C0, "gpg3", 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp4", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp5", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x040, "gpp6", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpc0", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpc1", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0a0, "gpd0", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x0c0, "gpg3", 0x18), }; /* pin banks of exynos9810 pin-controller 8 (VTS) */ static const struct samsung_pin_bank_data exynos9810_pin_banks8[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(3, 0x000, "gpt0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x000, "gpt0", 0x00), }; static const struct samsung_pin_ctrl exynos9810_pin_ctrl[] __initconst = { @@ -1239,55 +1238,55 @@ const struct samsung_pinctrl_of_match_data exynos9810_of_data __initconst = { /* pin banks of exynosautov9 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = { - EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), - EXYNOS850_PIN_BANK_EINTW(2, 0x020, "gpa1", 0x04), - EXYNOS850_PIN_BANK_EINTN(2, 0x040, "gpq0"), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x000, "gpa0", 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x020, "gpa1", 0x04), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 2, 0x040, "gpq0"), }; /* pin banks of exynosautov9 pin-controller 1 (AUD) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks1[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), - EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04), - EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpb2", 0x08), - EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpb3", 0x0C), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x000, "gpb0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpb1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpb2", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpb3", 0x0c), }; /* pin banks of exynosautov9 pin-controller 2 (FSYS0) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks2[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf0", 0x00), - EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x000, "gpf0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x020, "gpf1", 0x04), }; /* pin banks of exynosautov9 pin-controller 3 (FSYS1) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks3[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf8", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x000, "gpf8", 0x00), }; /* pin banks of exynosautov9 pin-controller 4 (FSYS2) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks4[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf2", 0x00), - EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf3", 0x04), - EXYNOS850_PIN_BANK_EINTG(7, 0x040, "gpf4", 0x08), - EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpf5", 0x0C), - EXYNOS850_PIN_BANK_EINTG(7, 0x080, "gpf6", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpf2", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpf3", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x040, "gpf4", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpf5", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x080, "gpf6", 0x10), }; /* pin banks of exynosautov9 pin-controller 5 (PERIC0) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks5[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), - EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), - EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), - EXYNOS850_PIN_BANK_EINTG(5, 0x060, "gpg0", 0x0C), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpp2", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x060, "gpg0", 0x0c), }; /* pin banks of exynosautov9 pin-controller 6 (PERIC1) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks6[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp3", 0x00), - EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp4", 0x04), - EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp5", 0x08), - EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpg1", 0x0C), - EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg2", 0x10), - EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpg3", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp3", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp4", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpp5", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpg1", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpg2", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0a0, "gpg3", 0x14), }; static const struct samsung_pin_ctrl exynosautov9_pin_ctrl[] __initconst = { @@ -1349,7 +1348,7 @@ const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = { static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = { EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28), EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24), - EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 2, 0x2000, "gpq0"), }; /* pin banks of exynosautov920 pin-controller 1 (AUD) */ @@ -1488,94 +1487,94 @@ const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = /* pin banks of exynos8890 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynos8890_pin_banks0[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS7870_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), - EXYNOS7870_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), - EXYNOS7870_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), - EXYNOS7870_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x000, "gpa0", 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x020, "gpa1", 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x040, "gpa2", 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x060, "gpa3", 0x0c), }; /* pin banks of exynos8890 pin-controller 1 (AUD) */ static const struct samsung_pin_bank_data exynos8890_pin_banks1[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS8895_PIN_BANK_EINTG(7, 0x000, "gph0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 7, 0x000, "gph0", 0x00), }; /* pin banks of exynos8890 pin-controller 2 (CCORE) */ static const struct samsung_pin_bank_data exynos8890_pin_banks2[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS8895_PIN_BANK_EINTG(2, 0x000, "etc0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x000, "etc0", 0x00), }; /* pin banks of exynos8890 pin-controller 3 (ESE) */ static const struct samsung_pin_bank_data exynos8890_pin_banks3[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS8895_PIN_BANK_EINTG(5, 0x000, "gpf3", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x000, "gpf3", 0x00), }; /* pin banks of exynos8890 pin-controller 4 (FP) */ static const struct samsung_pin_bank_data exynos8890_pin_banks4[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpf2", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x000, "gpf2", 0x00), }; /* pin banks of exynos8890 pin-controller 5 (FSYS0) */ static const struct samsung_pin_bank_data exynos8890_pin_banks5[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpi1", 0x00), - EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpi2", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x000, "gpi1", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x020, "gpi2", 0x04), }; /* pin banks of exynos8890 pin-controller 6 (FSYS1) */ static const struct samsung_pin_bank_data exynos8890_pin_banks6[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS8895_PIN_BANK_EINTG(7, 0x000, "gpj0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 7, 0x000, "gpj0", 0x00), }; /* pin banks of exynos8890 pin-controller 7 (NFC) */ static const struct samsung_pin_bank_data exynos8890_pin_banks7[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpf0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x000, "gpf0", 0x00), }; /* pin banks of exynos8890 pin-controller 8 (PERIC0) */ static const struct samsung_pin_bank_data exynos8890_pin_banks8[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS8895_PIN_BANK_EINTG(6, 0x000, "gpi0", 0x00), - EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpd0", 0x04), - EXYNOS8895_PIN_BANK_EINTG(6, 0x040, "gpd1", 0x08), - EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpd2", 0x0c), - EXYNOS8895_PIN_BANK_EINTG(4, 0x080, "gpd3", 0x10), - EXYNOS8895_PIN_BANK_EINTG(2, 0x0A0, "gpb1", 0x14), - EXYNOS8895_PIN_BANK_EINTG(2, 0x0C0, "gpb2", 0x18), - EXYNOS8895_PIN_BANK_EINTG(3, 0x0E0, "gpb0", 0x1c), - EXYNOS8895_PIN_BANK_EINTG(5, 0x100, "gpc0", 0x20), - EXYNOS8895_PIN_BANK_EINTG(5, 0x120, "gpc1", 0x24), - EXYNOS8895_PIN_BANK_EINTG(6, 0x140, "gpc2", 0x28), - EXYNOS8895_PIN_BANK_EINTG(8, 0x160, "gpc3", 0x2c), - EXYNOS8895_PIN_BANK_EINTG(4, 0x180, "gpk0", 0x30), - EXYNOS8895_PIN_BANK_EINTG(7, 0x1A0, "etc1", 0x34), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x000, "gpi0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x020, "gpd0", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x040, "gpd1", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x060, "gpd2", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x080, "gpd3", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0A0, "gpb1", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0C0, "gpb2", 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x0E0, "gpb0", 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x100, "gpc0", 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x120, "gpc1", 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x140, "gpc2", 0x28), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x160, "gpc3", 0x2c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x180, "gpk0", 0x30), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 7, 0x1A0, "etc1", 0x34), }; /* pin banks of exynos8890 pin-controller 9 (PERIC1) */ static const struct samsung_pin_bank_data exynos8890_pin_banks9[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS8895_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), - EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpe5", 0x04), - EXYNOS8895_PIN_BANK_EINTG(8, 0x040, "gpe6", 0x08), - EXYNOS8895_PIN_BANK_EINTG(8, 0x060, "gpj1", 0x0c), - EXYNOS8895_PIN_BANK_EINTG(2, 0x080, "gpj2", 0x10), - EXYNOS8895_PIN_BANK_EINTG(8, 0x0A0, "gpe2", 0x14), - EXYNOS8895_PIN_BANK_EINTG(8, 0x0C0, "gpe3", 0x18), - EXYNOS8895_PIN_BANK_EINTG(8, 0x0E0, "gpe4", 0x1c), - EXYNOS8895_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), - EXYNOS8895_PIN_BANK_EINTG(4, 0x120, "gpe7", 0x24), - EXYNOS8895_PIN_BANK_EINTG(3, 0x140, "gpg0", 0x28), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x000, "gpe0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x020, "gpe5", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x040, "gpe6", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x060, "gpj1", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x080, "gpj2", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0A0, "gpe2", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0C0, "gpe3", 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0E0, "gpe4", 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x100, "gpe1", 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x120, "gpe7", 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x140, "gpg0", 0x28), }; /* pin banks of exynos8890 pin-controller 10 (TOUCH) */ static const struct samsung_pin_bank_data exynos8890_pin_banks10[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpf1", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x000, "gpf1", 0x00), }; static const struct samsung_pin_ctrl exynos8890_pin_ctrl[] __initconst = { @@ -1644,69 +1643,69 @@ const struct samsung_pinctrl_of_match_data exynos8890_of_data __initconst = { /* pin banks of exynos8895 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynos8895_pin_banks0[] __initconst = { - EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c), - EXYNOS_PIN_BANK_EINTW(7, 0x0a0, "gpa4", 0x24), + EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x020, "gpa0", 0x00), + EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x040, "gpa1", 0x04), + EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x060, "gpa2", 0x08), + EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x080, "gpa3", 0x0c), + EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 7, 0x0a0, "gpa4", 0x24), }; /* pin banks of exynos8895 pin-controller 1 (ABOX) */ static const struct samsung_pin_bank_data exynos8895_pin_banks1[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00), - EXYNOS_PIN_BANK_EINTG(7, 0x020, "gph1", 0x04), - EXYNOS_PIN_BANK_EINTG(4, 0x040, "gph3", 0x08), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x000, "gph0", 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 7, 0x020, "gph1", 0x04), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x040, "gph3", 0x08), }; /* pin banks of exynos8895 pin-controller 2 (VTS) */ static const struct samsung_pin_bank_data exynos8895_pin_banks2[] __initconst = { - EXYNOS_PIN_BANK_EINTG(3, 0x000, "gph2", 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 3, 0x000, "gph2", 0x00), }; /* pin banks of exynos8895 pin-controller 3 (FSYS0) */ static const struct samsung_pin_bank_data exynos8895_pin_banks3[] __initconst = { - EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpi0", 0x00), - EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpi1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x000, "gpi0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x020, "gpi1", 0x04), }; /* pin banks of exynos8895 pin-controller 4 (FSYS1) */ static const struct samsung_pin_bank_data exynos8895_pin_banks4[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj1", 0x00), - EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpj0", 0x04), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x000, "gpj1", 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 7, 0x020, "gpj0", 0x04), }; /* pin banks of exynos8895 pin-controller 5 (BUSC) */ static const struct samsung_pin_bank_data exynos8895_pin_banks5[] __initconst = { - EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpb2", 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 2, 0x000, "gpb2", 0x00), }; /* pin banks of exynos8895 pin-controller 6 (PERIC0) */ static const struct samsung_pin_bank_data exynos8895_pin_banks6[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpd0", 0x00), - EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpd1", 0x04), - EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpd2", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpd3", 0x0C), - EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), - EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpe7", 0x14), - EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf1", 0x18), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x000, "gpd0", 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x020, "gpd1", 0x04), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x040, "gpd2", 0x08), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 5, 0x060, "gpd3", 0x0C), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x080, "gpb1", 0x10), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0a0, "gpe7", 0x14), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0c0, "gpf1", 0x18), }; /* pin banks of exynos8895 pin-controller 7 (PERIC1) */ static const struct samsung_pin_bank_data exynos8895_pin_banks7[] __initconst = { - EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpb0", 0x00), - EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpc0", 0x04), - EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpc1", 0x08), - EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpc2", 0x0C), - EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpk0", 0x14), - EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpe5", 0x18), - EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe6", 0x1C), - EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe2", 0x20), - EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpe3", 0x24), - EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe4", 0x28), - EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpf0", 0x2C), - EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe1", 0x30), - EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 3, 0x000, "gpb0", 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 5, 0x020, "gpc0", 0x04), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 5, 0x040, "gpc1", 0x08), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x060, "gpc2", 0x0C), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x080, "gpc3", 0x10), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x0a0, "gpk0", 0x14), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0c0, "gpe5", 0x18), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0e0, "gpe6", 0x1C), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x100, "gpe2", 0x20), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x120, "gpe3", 0x24), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x140, "gpe4", 0x28), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x160, "gpf0", 0x2C), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x180, "gpe1", 0x30), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 2, 0x1a0, "gpg0", 0x34), }; static const struct samsung_pin_ctrl exynos8895_pin_ctrl[] __initconst = { @@ -1777,41 +1776,41 @@ const struct samsung_pinctrl_of_match_data exynos8895_of_data __initconst = { /* pin banks of FSD pin-controller 0 (FSYS) */ static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00), - EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04), - EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08), - EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c), - EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x00, "gpf0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x20, "gpf1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x40, "gpf6", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x60, "gpf4", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x80, "gpf5", 0x10), }; /* pin banks of FSD pin-controller 1 (PERIC) */ static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = { - EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00), - EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04), - EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08), - EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c), - EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10), - EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14), - EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18), - EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c), - EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20), - EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24), - EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28), - EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), - EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30), - EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34), - EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38), - EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c), - EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), - EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44), - EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48), - EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c), - EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpc8", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x020, "gpf2", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpf3", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpd0", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpb0", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0a0, "gpb1", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0c0, "gpb4", 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0e0, "gpb5", 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x100, "gpb6", 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x120, "gpb7", 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x140, "gpd1", 0x28), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x160, "gpd2", 0x2c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x180, "gpd3", 0x30), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x1a0, "gpg0", 0x34), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x1c0, "gpg1", 0x38), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x1e0, "gpg2", 0x3c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x200, "gpg3", 0x40), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x220, "gpg4", 0x44), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x240, "gpg5", 0x48), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x260, "gpg6", 0x4c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x280, "gpg7", 0x50), }; /* pin banks of FSD pin-controller 2 (PMU) */ static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = { - EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 3, 0x00, "gpq0"), }; static const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = { diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index c9c38f8988dd..41cec8408d0d 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -132,37 +132,18 @@ .pctl_res_idx = pctl_idx, \ } \ -#define EXYNOS7870_PIN_BANK_EINTN(pins, reg, id) \ +#define EXYNOS9_PIN_BANK_EINTN(bank_type, pins, reg, id) \ { \ - .type = &exynos7870_bank_type_alive, \ + .type = &bank_type, \ .pctl_offset = reg, \ .nr_pins = pins, \ .eint_type = EINT_TYPE_NONE, \ .name = id \ } -#define EXYNOS7870_PIN_BANK_EINTW(pins, reg, id, offs) \ +#define EXYNOS9_PIN_BANK_EINTG(bank_type, pins, reg, id, offs) \ { \ - .type = &exynos7870_bank_type_alive, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_WKUP, \ - .eint_offset = offs, \ - .name = id \ - } - -#define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \ - { \ - .type = &exynos850_bank_type_alive, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_NONE, \ - .name = id \ - } - -#define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs) \ - { \ - .type = &exynos850_bank_type_off, \ + .type = &bank_type, \ .pctl_offset = reg, \ .nr_pins = pins, \ .eint_type = EINT_TYPE_GPIO, \ @@ -170,9 +151,9 @@ .name = id \ } -#define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs) \ +#define EXYNOS9_PIN_BANK_EINTW(bank_type, pins, reg, id, offs) \ { \ - .type = &exynos850_bank_type_alive, \ + .type = &bank_type, \ .pctl_offset = reg, \ .nr_pins = pins, \ .eint_type = EINT_TYPE_WKUP, \ @@ -180,19 +161,9 @@ .name = id \ } -#define EXYNOS8895_PIN_BANK_EINTG(pins, reg, id, offs) \ - { \ - .type = &exynos8895_bank_type_off, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_GPIO, \ - .eint_offset = offs, \ - .name = id \ - } - #define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs) \ { \ - .type = &exynos850_bank_type_off, \ + .type = &exynos9_bank_type_off, \ .pctl_offset = reg, \ .nr_pins = pins, \ .eint_type = EINT_TYPE_GPIO, \ @@ -204,7 +175,7 @@ #define EXYNOSV920_PIN_BANK_EINTW(pins, reg, id, con_offs, mask_offs, pend_offs) \ { \ - .type = &exynos850_bank_type_alive, \ + .type = &exynos9_bank_type_alive, \ .pctl_offset = reg, \ .nr_pins = pins, \ .eint_type = EINT_TYPE_WKUP, \ @@ -216,7 +187,7 @@ #define GS101_PIN_BANK_EINTG(pins, reg, id, offs, fltcon_offs) \ { \ - .type = &exynos850_bank_type_off, \ + .type = &exynos9_bank_type_off, \ .pctl_offset = reg, \ .nr_pins = pins, \ .eint_type = EINT_TYPE_GPIO, \ @@ -227,7 +198,7 @@ #define GS101_PIN_BANK_EINTW(pins, reg, id, offs, fltcon_offs) \ { \ - .type = &exynos850_bank_type_alive, \ + .type = &exynos9_bank_type_alive, \ .pctl_offset = reg, \ .nr_pins = pins, \ .eint_type = EINT_TYPE_WKUP, \ -- 2.52.0 ^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH v3 1/5] pinctrl: samsung: Consolidate pin-bank macros under EXYNOS9_* and pass bank_type explicitly 2025-12-02 9:36 ` [PATCH v3 1/5] pinctrl: samsung: Consolidate pin-bank macros under EXYNOS9_* and pass bank_type explicitly Youngmin Nam @ 2025-12-17 4:28 ` Alim Akhtar 2025-12-28 11:40 ` Krzysztof Kozlowski 1 sibling, 0 replies; 19+ messages in thread From: Alim Akhtar @ 2025-12-17 4:28 UTC (permalink / raw) To: 'Youngmin Nam', krzk, s.nawrocki, linus.walleij, peter.griffin, semen.protsenko, ivo.ivanov.ivanov1 Cc: ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel Hello Youngmin, > -----Original Message----- > From: Youngmin Nam <youngmin.nam@samsung.com> > Sent: Tuesday, December 2, 2025 3:06 PM > To: krzk@kernel.org; s.nawrocki@samsung.com; alim.akhtar@samsung.com; > linus.walleij@linaro.org; peter.griffin@linaro.org; > semen.protsenko@linaro.org; ivo.ivanov.ivanov1@gmail.com > Cc: ryu.real@samsung.com; d7271.choe@samsung.com; > shin.son@samsung.com; jaewon02.kim@samsung.com; linux-arm- > kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux- > gpio@vger.kernel.org; linux-kernel@vger.kernel.org; Youngmin Nam > <youngmin.nam@samsung.com> > Subject: [PATCH v3 1/5] pinctrl: samsung: Consolidate pin-bank macros under > EXYNOS9_* and pass bank_type explicitly > > Modern Exynos platforms have several near-duplicate pin-bank macro > families (EXYNOS850_*, EXYNOS8895_*, EXYNOS7870_*), which makes > tables verbose and harder to share across SoCs that differ only by > bank_type (alive/off) layout. > > This patch unifies them into one EXYNOS9_* macro family and makes the > bank_type an explicit argument. The common 850-era bank types are also > renamed to 'exynos9_bank_type_{alive,off}' to reflect their reuse on > later Exynos 9xxx-generation parts. > > Naming rationale: > - Use of the EXYNOS9_* prefix indicates that these macros target > current Exynos generations sharing the same register layout and > EINT wiring model. Compared to SoC-specific prefixes > (EXYNOS850_*, EXYNOS8895_*), > EXYNOS9_* is clearer and more future-proof for modern parts. > > Key changes: > - Introduce: > - 'EXYNOS9_PIN_BANK_EINTN(bank_type, pins, reg, id)' > - 'EXYNOS9_PIN_BANK_EINTG(bank_type, pins, reg, id, offs)' > - 'EXYNOS9_PIN_BANK_EINTW(bank_type, pins, reg, id, offs)' > - Rename: > - 'exynos850_bank_type_alive'-> 'exynos9_bank_type_alive' > - 'exynos850_bank_type_off' -> 'exynos9_bank_type_off' > - Convert pin-bank tables for: > - Exynos2200, 7870, 7885, 850, 990, 9810, 8890, 8895, > AutoV9, AutoV920, FSD > - Update GS101/EXYNOSV920 helpers to reference 'exynos9_bank_type_*' > instead of the old exynos850 names. > - Standardize on EXYNOS9_* macros while keeping SoC-specific > '*_bank_type_*' when layouts differ (e.g., 7870/8895). > > No functional change intended. > > Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Tested-by: Sam Protsenko <semen.protsenko@linaro.org> > --- Thanks for consolidating this. Feel free to add Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Also tested on SADK based on Exynosautov920, GPIO EINT works fine. Tested-by: Alim Akhtar <alim.akhtar@samsung.com> ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 1/5] pinctrl: samsung: Consolidate pin-bank macros under EXYNOS9_* and pass bank_type explicitly 2025-12-02 9:36 ` [PATCH v3 1/5] pinctrl: samsung: Consolidate pin-bank macros under EXYNOS9_* and pass bank_type explicitly Youngmin Nam 2025-12-17 4:28 ` Alim Akhtar @ 2025-12-28 11:40 ` Krzysztof Kozlowski 1 sibling, 0 replies; 19+ messages in thread From: Krzysztof Kozlowski @ 2025-12-28 11:40 UTC (permalink / raw) To: Youngmin Nam, s.nawrocki, alim.akhtar, linus.walleij, peter.griffin, semen.protsenko, ivo.ivanov.ivanov1 Cc: ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel On 02/12/2025 10:36, Youngmin Nam wrote: > Modern Exynos platforms have several near-duplicate pin-bank macro > families (EXYNOS850_*, EXYNOS8895_*, EXYNOS7870_*), which makes > tables verbose and harder to share across SoCs that differ only by > bank_type (alive/off) layout. I do not see at all how you reduced duplication, reduced verbosity or made here anything easier to read. Previous explicit EXYNOS850_PIN_BANK_EINTW() - so having one information about SoC - is now containing more verbose two informations: EXYNOS9_PIN_BANK_EINTW + exynos9_bank_type_alive, > > This patch unifies them into one EXYNOS9_* macro family and makes the > bank_type an explicit argument. The common 850-era bank types are also > renamed to 'exynos9_bank_type_{alive,off}' to reflect their reuse on > later Exynos 9xxx-generation parts. > > Naming rationale: > - Use of the EXYNOS9_* prefix indicates that these macros target > current Exynos generations sharing the same register layout and > EINT wiring model. Compared to SoC-specific prefixes There is no exynos9 chip. There is also no need to rename Exynos850 to Exynos9, because old name is correct, accurate and probably even older, thus more suitable choice. > (EXYNOS850_*, EXYNOS8895_*), > EXYNOS9_* is clearer and more future-proof for modern parts. > > Key changes: > - Introduce: > - 'EXYNOS9_PIN_BANK_EINTN(bank_type, pins, reg, id)' > - 'EXYNOS9_PIN_BANK_EINTG(bank_type, pins, reg, id, offs)' > - 'EXYNOS9_PIN_BANK_EINTW(bank_type, pins, reg, id, offs)' > - Rename: > - 'exynos850_bank_type_alive'-> 'exynos9_bank_type_alive' > - 'exynos850_bank_type_off' -> 'exynos9_bank_type_off' > - Convert pin-bank tables for: > - Exynos2200, 7870, 7885, 850, 990, 9810, 8890, 8895, > AutoV9, AutoV920, FSD > - Update GS101/EXYNOSV920 helpers to reference 'exynos9_bank_type_*' > instead of the old exynos850 names. > - Standardize on EXYNOS9_* macros while keeping SoC-specific > '*_bank_type_*' when layouts differ (e.g., 7870/8895). > > No functional change intended. > > Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Tested-by: Sam Protsenko <semen.protsenko@linaro.org> > --- > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 785 +++++++++--------- > drivers/pinctrl/samsung/pinctrl-exynos.h | 49 +- > 2 files changed, 402 insertions(+), 432 deletions(-) > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > index 627dca504d7a..d11b2d4ca913 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > @@ -53,7 +53,7 @@ static const struct samsung_pin_bank_type exynos7870_bank_type_alive = { > * Bank type for non-alive type. Bit fields: > * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 > */ > -static const struct samsung_pin_bank_type exynos850_bank_type_off = { > +static const struct samsung_pin_bank_type exynos9_bank_type_off = { This is completely pointless. > .fld_width = { 4, 1, 4, 4, 2, 4, }, > .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, > }; > @@ -62,7 +62,7 @@ static const struct samsung_pin_bank_type exynos850_bank_type_off = { > * Bank type for alive type. Bit fields: > * CON: 4, DAT: 1, PUD: 4, DRV: 4 > */ > -static const struct samsung_pin_bank_type exynos850_bank_type_alive = { > +static const struct samsung_pin_bank_type exynos9_bank_type_alive = { > .fld_width = { 4, 1, 4, 4, }, > .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, > }; > @@ -90,11 +90,11 @@ static atomic_t exynos_shared_retention_refcnt; > > /* pin banks of exynos2200 pin-controller - ALIVE */ > static const struct samsung_pin_bank_data exynos2200_pin_banks0[] __initconst = { > - EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00), > - EXYNOS850_PIN_BANK_EINTW(8, 0x20, "gpa1", 0x04), > - EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa2", 0x08), > - EXYNOS850_PIN_BANK_EINTW(8, 0x60, "gpa3", 0x0c), > - EXYNOS850_PIN_BANK_EINTW(2, 0x80, "gpa4", 0x10), > + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x0, "gpa0", 0x00), And this is less readable. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 19+ messages in thread
[parent not found: <CGME20251202093027epcas2p24adbd3226dd50b2780baceee6588f3ba@epcas2p2.samsung.com>]
* [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries on Exynos2200/7885/8890/8895 [not found] ` <CGME20251202093027epcas2p24adbd3226dd50b2780baceee6588f3ba@epcas2p2.samsung.com> @ 2025-12-02 9:36 ` Youngmin Nam 2025-12-17 4:33 ` Alim Akhtar ` (2 more replies) 0 siblings, 3 replies; 19+ messages in thread From: Youngmin Nam @ 2025-12-02 9:36 UTC (permalink / raw) To: krzk, s.nawrocki, alim.akhtar, linus.walleij, peter.griffin, semen.protsenko, ivo.ivanov.ivanov1 Cc: ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel, Youngmin Nam This patch corrects wrong pin bank table definitions for 4 SoCs based on their TRMs. Exynos2200 - gpq0/1/2 were using EXYNOS_PIN_BANK_EINTN(), which implies a 'bank_type_off' layout (.fld_width = {4,1,2,2,2,2}). - Per the SoC TRM these banks must use the 'alive' layout (.fld_width = {4,1,4,4}). - Switch them to EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, ...). Exynos7885 - etc0, etc1: update bank type to match the SoC TRM. - gpq0 is a non-wakeup interrupt bank; change EINTW -> EINTN accordingly. Exynos8890 - Per the SoC TRM, rename bank ect0 to gpb3 and mark it as a non-external interrupt bank. - gpi1, gpi2: update bank type to match the SoC TRM. exynos8895_bank_type_off (.fld_width = {4,1,2,3,2,2}) -> exynos5433_bank_type_off (.fld_width = {4,1,2,4,2,2}) - Per the SoC TRM, mark etc1 as a non-external interrupt bank. - apply lower case style for hex numbers. Exynos8895 - gpa4 is a non-wakeup interrupt bank per the SoC TRM. change EINTW -> EINTN. (The bank_type itself was correct and is kept unchanged.) - apply lower case style for hex numbers. This aligns the pin-bank tables with the documented bitfield layouts and wakeup domains. No DT/ABI change. Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Tested-by: Sam Protsenko <semen.protsenko@linaro.org> --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 40 +++++++++---------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index d11b2d4ca913..b4a7d86b82fe 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -95,9 +95,9 @@ static const struct samsung_pin_bank_data exynos2200_pin_banks0[] __initconst = EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x40, "gpa2", 0x08), EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x60, "gpa3", 0x0c), EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x80, "gpa4", 0x10), - EXYNOS_PIN_BANK_EINTN(4, 0xa0, "gpq0"), - EXYNOS_PIN_BANK_EINTN(2, 0xc0, "gpq1"), - EXYNOS_PIN_BANK_EINTN(2, 0xe0, "gpq2"), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 4, 0xa0, "gpq0"), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 2, 0xc0, "gpq1"), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 2, 0xe0, "gpq2"), }; /* pin banks of exynos2200 pin-controller - CMGP */ @@ -768,12 +768,12 @@ const struct samsung_pinctrl_of_match_data exynos7870_of_data __initconst = { /* pin banks of exynos7885 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = { - EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"), - EXYNOS_PIN_BANK_EINTN(3, 0x020, "etc1"), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 3, 0x000, "etc0"), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 3, 0x020, "etc1"), EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x040, "gpa0", 0x00), EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x060, "gpa1", 0x04), EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x080, "gpa2", 0x08), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 5, 0x0a0, "gpq0", 0x0c), + EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 5, 0x0a0, "gpq0"), }; /* pin banks of exynos7885 pin-controller 1 (DISPAUD) */ @@ -1502,7 +1502,7 @@ static const struct samsung_pin_bank_data exynos8890_pin_banks1[] __initconst = /* pin banks of exynos8890 pin-controller 2 (CCORE) */ static const struct samsung_pin_bank_data exynos8890_pin_banks2[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x000, "etc0", 0x00), + EXYNOS9_PIN_BANK_EINTN(exynos8895_bank_type_off, 2, 0x000, "gpb3"), }; /* pin banks of exynos8890 pin-controller 3 (ESE) */ @@ -1520,8 +1520,8 @@ static const struct samsung_pin_bank_data exynos8890_pin_banks4[] __initconst = /* pin banks of exynos8890 pin-controller 5 (FSYS0) */ static const struct samsung_pin_bank_data exynos8890_pin_banks5[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x000, "gpi1", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x020, "gpi2", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos5433_bank_type_off, 4, 0x000, "gpi1", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos5433_bank_type_off, 8, 0x020, "gpi2", 0x04), }; /* pin banks of exynos8890 pin-controller 6 (FSYS1) */ @@ -1544,15 +1544,15 @@ static const struct samsung_pin_bank_data exynos8890_pin_banks8[] __initconst = EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x040, "gpd1", 0x08), EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x060, "gpd2", 0x0c), EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x080, "gpd3", 0x10), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0A0, "gpb1", 0x14), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0C0, "gpb2", 0x18), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x0E0, "gpb0", 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0a0, "gpb1", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0c0, "gpb2", 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x0e0, "gpb0", 0x1c), EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x100, "gpc0", 0x20), EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x120, "gpc1", 0x24), EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x140, "gpc2", 0x28), EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x160, "gpc3", 0x2c), EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x180, "gpk0", 0x30), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 7, 0x1A0, "etc1", 0x34), + EXYNOS9_PIN_BANK_EINTN(exynos8895_bank_type_off, 7, 0x1a0, "etc1"), }; /* pin banks of exynos8890 pin-controller 9 (PERIC1) */ @@ -1563,9 +1563,9 @@ static const struct samsung_pin_bank_data exynos8890_pin_banks9[] __initconst = EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x040, "gpe6", 0x08), EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x060, "gpj1", 0x0c), EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x080, "gpj2", 0x10), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0A0, "gpe2", 0x14), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0C0, "gpe3", 0x18), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0E0, "gpe4", 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0a0, "gpe2", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0c0, "gpe3", 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0e0, "gpe4", 0x1c), EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x100, "gpe1", 0x20), EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x120, "gpe7", 0x24), EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x140, "gpg0", 0x28), @@ -1647,7 +1647,7 @@ static const struct samsung_pin_bank_data exynos8895_pin_banks0[] __initconst = EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x040, "gpa1", 0x04), EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x060, "gpa2", 0x08), EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x080, "gpa3", 0x0c), - EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 7, 0x0a0, "gpa4", 0x24), + EXYNOS9_PIN_BANK_EINTN(bank_type_alive, 7, 0x0a0, "gpa4"), }; /* pin banks of exynos8895 pin-controller 1 (ABOX) */ @@ -1695,15 +1695,15 @@ static const struct samsung_pin_bank_data exynos8895_pin_banks7[] __initconst = EXYNOS9_PIN_BANK_EINTG(bank_type_off, 3, 0x000, "gpb0", 0x00), EXYNOS9_PIN_BANK_EINTG(bank_type_off, 5, 0x020, "gpc0", 0x04), EXYNOS9_PIN_BANK_EINTG(bank_type_off, 5, 0x040, "gpc1", 0x08), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x060, "gpc2", 0x0C), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x060, "gpc2", 0x0c), EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x080, "gpc3", 0x10), EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x0a0, "gpk0", 0x14), EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0c0, "gpe5", 0x18), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0e0, "gpe6", 0x1C), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0e0, "gpe6", 0x1c), EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x100, "gpe2", 0x20), EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x120, "gpe3", 0x24), EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x140, "gpe4", 0x28), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x160, "gpf0", 0x2C), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x160, "gpf0", 0x2c), EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x180, "gpe1", 0x30), EXYNOS9_PIN_BANK_EINTG(bank_type_off, 2, 0x1a0, "gpg0", 0x34), }; -- 2.52.0 ^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries on Exynos2200/7885/8890/8895 2025-12-02 9:36 ` [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries on Exynos2200/7885/8890/8895 Youngmin Nam @ 2025-12-17 4:33 ` Alim Akhtar 2025-12-28 11:37 ` Krzysztof Kozlowski 2026-03-06 21:17 ` Peter Griffin 2 siblings, 0 replies; 19+ messages in thread From: Alim Akhtar @ 2025-12-17 4:33 UTC (permalink / raw) To: 'Youngmin Nam', krzk, s.nawrocki, linus.walleij, peter.griffin, semen.protsenko, ivo.ivanov.ivanov1 Cc: ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel Hello Youngmin > -----Original Message----- > From: Youngmin Nam <youngmin.nam@samsung.com> > Sent: Tuesday, December 2, 2025 3:06 PM > To: krzk@kernel.org; s.nawrocki@samsung.com; alim.akhtar@samsung.com; > linus.walleij@linaro.org; peter.griffin@linaro.org; > semen.protsenko@linaro.org; ivo.ivanov.ivanov1@gmail.com > Cc: ryu.real@samsung.com; d7271.choe@samsung.com; > shin.son@samsung.com; jaewon02.kim@samsung.com; linux-arm- > kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux- > gpio@vger.kernel.org; linux-kernel@vger.kernel.org; Youngmin Nam > <youngmin.nam@samsung.com> > Subject: [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries on > Exynos2200/7885/8890/8895 > > This patch corrects wrong pin bank table definitions for 4 SoCs based on their > TRMs. > > Exynos2200 > - gpq0/1/2 were using EXYNOS_PIN_BANK_EINTN(), which implies a > 'bank_type_off' layout (.fld_width = {4,1,2,2,2,2}). > - Per the SoC TRM these banks must use the 'alive' layout > (.fld_width = {4,1,4,4}). > - Switch them to EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, ...). > > Exynos7885 > - etc0, etc1: update bank type to match the SoC TRM. > - gpq0 is a non-wakeup interrupt bank; change EINTW -> EINTN accordingly. > > Exynos8890 > - Per the SoC TRM, rename bank ect0 to gpb3 and mark it as > a non-external interrupt bank. > - gpi1, gpi2: update bank type to match the SoC TRM. > exynos8895_bank_type_off (.fld_width = {4,1,2,3,2,2}) -> > exynos5433_bank_type_off (.fld_width = {4,1,2,4,2,2}) > - Per the SoC TRM, mark etc1 as a non-external interrupt bank. > - apply lower case style for hex numbers. > > Exynos8895 > - gpa4 is a non-wakeup interrupt bank per the SoC TRM. > change EINTW -> EINTN. (The bank_type itself was correct and is kept > unchanged.) > - apply lower case style for hex numbers. > > This aligns the pin-bank tables with the documented bitfield layouts and > wakeup domains. No DT/ABI change. > > Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Reviewed-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > Tested-by: Sam Protsenko <semen.protsenko@linaro.org> > --- Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Tested on Exynosautov920 SADK board Tested-by: Alim Akhtar <alim.akhtar@samsung.com> ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries on Exynos2200/7885/8890/8895 2025-12-02 9:36 ` [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries on Exynos2200/7885/8890/8895 Youngmin Nam 2025-12-17 4:33 ` Alim Akhtar @ 2025-12-28 11:37 ` Krzysztof Kozlowski 2026-03-06 21:17 ` Peter Griffin 2 siblings, 0 replies; 19+ messages in thread From: Krzysztof Kozlowski @ 2025-12-28 11:37 UTC (permalink / raw) To: Youngmin Nam, s.nawrocki, alim.akhtar, linus.walleij, peter.griffin, semen.protsenko, ivo.ivanov.ivanov1 Cc: ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel On 02/12/2025 10:36, Youngmin Nam wrote: > This patch corrects wrong pin bank table definitions for 4 SoCs based on Please do not use "This commit/patch/change", but imperative mood. See longer explanation here: https://elixir.bootlin.com/linux/v6.16/source/Documentation/process/submitting-patches.rst#L94 > their TRMs. > > Exynos2200 > - gpq0/1/2 were using EXYNOS_PIN_BANK_EINTN(), which implies a > 'bank_type_off' layout (.fld_width = {4,1,2,2,2,2}). > - Per the SoC TRM these banks must use the 'alive' layout > (.fld_width = {4,1,4,4}). > - Switch them to EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, ...). > > Exynos7885 > - etc0, etc1: update bank type to match the SoC TRM. > - gpq0 is a non-wakeup interrupt bank; change EINTW -> EINTN accordingly. > > Exynos8890 > - Per the SoC TRM, rename bank ect0 to gpb3 and mark it as > a non-external interrupt bank. > - gpi1, gpi2: update bank type to match the SoC TRM. > exynos8895_bank_type_off (.fld_width = {4,1,2,3,2,2}) -> > exynos5433_bank_type_off (.fld_width = {4,1,2,4,2,2}) > - Per the SoC TRM, mark etc1 as a non-external interrupt bank. > - apply lower case style for hex numbers. > > Exynos8895 > - gpa4 is a non-wakeup interrupt bank per the SoC TRM. > change EINTW -> EINTN. (The bank_type itself was correct and is kept > unchanged.) > - apply lower case style for hex numbers. Please separate logical changes into separate commits. Fix for given commit is one commit. Also, fixes cannot be in the middle of the patchset. > > This aligns the pin-bank tables with the documented bitfield layouts and > wakeup domains. No DT/ABI change. > > Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Reviewed-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > Tested-by: Sam Protsenko <semen.protsenko@linaro.org> Missing Fixes tags. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries on Exynos2200/7885/8890/8895 2025-12-02 9:36 ` [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries on Exynos2200/7885/8890/8895 Youngmin Nam 2025-12-17 4:33 ` Alim Akhtar 2025-12-28 11:37 ` Krzysztof Kozlowski @ 2026-03-06 21:17 ` Peter Griffin 2026-06-29 9:23 ` Alim Akhtar 2 siblings, 1 reply; 19+ messages in thread From: Peter Griffin @ 2026-03-06 21:17 UTC (permalink / raw) To: Youngmin Nam Cc: krzk, s.nawrocki, alim.akhtar, linus.walleij, semen.protsenko, ivo.ivanov.ivanov1, ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel Hi Youngmin, On Tue, 2 Dec 2025 at 09:30, Youngmin Nam <youngmin.nam@samsung.com> wrote: > > This patch corrects wrong pin bank table definitions for 4 SoCs based on > their TRMs. > > Exynos2200 > - gpq0/1/2 were using EXYNOS_PIN_BANK_EINTN(), which implies a > 'bank_type_off' layout (.fld_width = {4,1,2,2,2,2}). > - Per the SoC TRM these banks must use the 'alive' layout > (.fld_width = {4,1,4,4}). > - Switch them to EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, ...). > > Exynos7885 > - etc0, etc1: update bank type to match the SoC TRM. > - gpq0 is a non-wakeup interrupt bank; change EINTW -> EINTN accordingly. > > Exynos8890 > - Per the SoC TRM, rename bank ect0 to gpb3 and mark it as > a non-external interrupt bank. > - gpi1, gpi2: update bank type to match the SoC TRM. > exynos8895_bank_type_off (.fld_width = {4,1,2,3,2,2}) -> > exynos5433_bank_type_off (.fld_width = {4,1,2,4,2,2}) > - Per the SoC TRM, mark etc1 as a non-external interrupt bank. > - apply lower case style for hex numbers. > > Exynos8895 > - gpa4 is a non-wakeup interrupt bank per the SoC TRM. > change EINTW -> EINTN. (The bank_type itself was correct and is kept > unchanged.) > - apply lower case style for hex numbers. > > This aligns the pin-bank tables with the documented bitfield layouts and > wakeup domains. No DT/ABI change. > > Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Reviewed-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > Tested-by: Sam Protsenko <semen.protsenko@linaro.org> > --- This patch contains some worthwhile fixes for multiple Exynos SoCs. Do you plan to re-send it? I think it would be good to get this merged (even if there isn't broad agreement around renaming the pinctrl macros to EXYNOS9_) Thanks, Peter ^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries on Exynos2200/7885/8890/8895 2026-03-06 21:17 ` Peter Griffin @ 2026-06-29 9:23 ` Alim Akhtar 2026-07-03 12:15 ` 남영민 0 siblings, 1 reply; 19+ messages in thread From: Alim Akhtar @ 2026-06-29 9:23 UTC (permalink / raw) To: 'Peter Griffin', 'Youngmin Nam' Cc: krzk, s.nawrocki, linus.walleij, semen.protsenko, ivo.ivanov.ivanov1, ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel Hi Krzysztof, Peter > -----Original Message----- > From: Peter Griffin <peter.griffin@linaro.org> > Sent: Saturday, March 7, 2026 2:47 AM > To: Youngmin Nam <youngmin.nam@samsung.com> > Cc: krzk@kernel.org; s.nawrocki@samsung.com; alim.akhtar@samsung.com; > linus.walleij@linaro.org; semen.protsenko@linaro.org; > ivo.ivanov.ivanov1@gmail.com; ryu.real@samsung.com; > d7271.choe@samsung.com; shin.son@samsung.com; > jaewon02.kim@samsung.com; linux-arm-kernel@lists.infradead.org; linux- > samsung-soc@vger.kernel.org; linux-gpio@vger.kernel.org; linux- > kernel@vger.kernel.org > Subject: Re: [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries on > Exynos2200/7885/8890/8895 > > Hi Youngmin, > > On Tue, 2 Dec 2025 at 09:30, Youngmin Nam > <youngmin.nam@samsung.com> wrote: > > > > This patch corrects wrong pin bank table definitions for 4 SoCs based > > on their TRMs. > > > > Exynos2200 > > - gpq0/1/2 were using EXYNOS_PIN_BANK_EINTN(), which implies a > > 'bank_type_off' layout (.fld_width = {4,1,2,2,2,2}). > > - Per the SoC TRM these banks must use the 'alive' layout > > (.fld_width = {4,1,4,4}). > > - Switch them to > EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, ...). > > > > Exynos7885 > > - etc0, etc1: update bank type to match the SoC TRM. > > - gpq0 is a non-wakeup interrupt bank; change EINTW -> EINTN accordingly. > > > > Exynos8890 > > - Per the SoC TRM, rename bank ect0 to gpb3 and mark it as > > a non-external interrupt bank. > > - gpi1, gpi2: update bank type to match the SoC TRM. > > exynos8895_bank_type_off (.fld_width = {4,1,2,3,2,2}) -> > > exynos5433_bank_type_off (.fld_width = {4,1,2,4,2,2}) > > - Per the SoC TRM, mark etc1 as a non-external interrupt bank. > > - apply lower case style for hex numbers. > > > > Exynos8895 > > - gpa4 is a non-wakeup interrupt bank per the SoC TRM. > > change EINTW -> EINTN. (The bank_type itself was correct and is kept > > unchanged.) > > - apply lower case style for hex numbers. > > > > This aligns the pin-bank tables with the documented bitfield layouts > > and wakeup domains. No DT/ABI change. > > > > Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > > Reviewed-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > > Tested-by: Sam Protsenko <semen.protsenko@linaro.org> > > --- > > This patch contains some worthwhile fixes for multiple Exynos SoCs. Do you > plan to re-send it? I think it would be good to get this merged (even if there > isn't broad agreement around renaming the pinctrl macros to EXYNOS9_) > Can we relook into this series? AFA EXYNOS9_ macro is concern, Exynos990, Exynos9810 etc already support available upstream. Of course it does not justify why Exynos9, but we can consider all SoCs which has come after 2020 have this newer architecture. Or Just have SAMSUNG_ prefix for all such newer SoC. A unified Macro help in adding new SoC support without much confusion(like I am trying with Exynos8855) @Youngmin, will you have some time to re-spin these series? > Thanks, > > Peter ^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries on Exynos2200/7885/8890/8895 2026-06-29 9:23 ` Alim Akhtar @ 2026-07-03 12:15 ` 남영민 0 siblings, 0 replies; 19+ messages in thread From: 남영민 @ 2026-07-03 12:15 UTC (permalink / raw) To: 'Alim Akhtar', 'Peter Griffin' Cc: krzk, s.nawrocki, linus.walleij, semen.protsenko, ivo.ivanov.ivanov1, ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel, youngmin.nam Hi Alim > -----Original Message----- > From: Alim Akhtar <alim.akhtar@samsung.com> > Sent: Monday, June 29, 2026 6:23 PM > To: 'Peter Griffin' <peter.griffin@linaro.org>; 'Youngmin Nam' > <youngmin.nam@samsung.com> > Cc: krzk@kernel.org; s.nawrocki@samsung.com; linus.walleij@linaro.org; > semen.protsenko@linaro.org; ivo.ivanov.ivanov1@gmail.com; > ryu.real@samsung.com; d7271.choe@samsung.com; shin.son@samsung.com; > jaewon02.kim@samsung.com; linux-arm-kernel@lists.infradead.org; linux- > samsung-soc@vger.kernel.org; linux-gpio@vger.kernel.org; linux- > kernel@vger.kernel.org > Subject: RE: [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank > entries on Exynos2200/7885/8890/8895 > > Hi Krzysztof, Peter > > > -----Original Message----- > > From: Peter Griffin <peter.griffin@linaro.org> > > Sent: Saturday, March 7, 2026 2:47 AM > > To: Youngmin Nam <youngmin.nam@samsung.com> > > Cc: krzk@kernel.org; s.nawrocki@samsung.com; alim.akhtar@samsung.com; > > linus.walleij@linaro.org; semen.protsenko@linaro.org; > > ivo.ivanov.ivanov1@gmail.com; ryu.real@samsung.com; > > d7271.choe@samsung.com; shin.son@samsung.com; > > jaewon02.kim@samsung.com; linux-arm-kernel@lists.infradead.org; linux- > > samsung-soc@vger.kernel.org; linux-gpio@vger.kernel.org; linux- > > kernel@vger.kernel.org > > Subject: Re: [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank > > entries on > > Exynos2200/7885/8890/8895 > > > > Hi Youngmin, > > > > On Tue, 2 Dec 2025 at 09:30, Youngmin Nam <youngmin.nam@samsung.com> > > wrote: > > > > > > This patch corrects wrong pin bank table definitions for 4 SoCs > > > based on their TRMs. > > > > > > Exynos2200 > > > - gpq0/1/2 were using EXYNOS_PIN_BANK_EINTN(), which implies a > > > 'bank_type_off' layout (.fld_width = {4,1,2,2,2,2}). > > > - Per the SoC TRM these banks must use the 'alive' layout > > > (.fld_width = {4,1,4,4}). > > > - Switch them to > > EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, ...). > > > > > > Exynos7885 > > > - etc0, etc1: update bank type to match the SoC TRM. > > > - gpq0 is a non-wakeup interrupt bank; change EINTW -> EINTN > accordingly. > > > > > > Exynos8890 > > > - Per the SoC TRM, rename bank ect0 to gpb3 and mark it as > > > a non-external interrupt bank. > > > - gpi1, gpi2: update bank type to match the SoC TRM. > > > exynos8895_bank_type_off (.fld_width = {4,1,2,3,2,2}) -> > > > exynos5433_bank_type_off (.fld_width = {4,1,2,4,2,2}) > > > - Per the SoC TRM, mark etc1 as a non-external interrupt bank. > > > - apply lower case style for hex numbers. > > > > > > Exynos8895 > > > - gpa4 is a non-wakeup interrupt bank per the SoC TRM. > > > change EINTW -> EINTN. (The bank_type itself was correct and is kept > > > unchanged.) > > > - apply lower case style for hex numbers. > > > > > > This aligns the pin-bank tables with the documented bitfield layouts > > > and wakeup domains. No DT/ABI change. > > > > > > Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> > > > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > > > Reviewed-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > > > Tested-by: Sam Protsenko <semen.protsenko@linaro.org> > > > --- > > > > This patch contains some worthwhile fixes for multiple Exynos SoCs. Do > > you plan to re-send it? I think it would be good to get this merged > > (even if there isn't broad agreement around renaming the pinctrl > > macros to EXYNOS9_) > > > Can we relook into this series? > AFA EXYNOS9_ macro is concern, Exynos990, Exynos9810 etc already support > available upstream. > Of course it does not justify why Exynos9, but we can consider all SoCs > which has come after 2020 have this newer architecture. > Or Just have SAMSUNG_ prefix for all such newer SoC. > > A unified Macro help in adding new SoC support without much confusion(like > I am trying with Exynos8855) > > @Youngmin, will you have some time to re-spin these series? > Sure. Let me re visit my patches and will try. > > Thanks, > > > > Peter > ^ permalink raw reply [flat|nested] 19+ messages in thread
[parent not found: <CGME20251202093028epcas2p456b6a2bfebfc76384f706a9962266fcf@epcas2p4.samsung.com>]
* [PATCH v3 3/5] pinctrl: samsung: add per-bank FLTCON offset to EXYNOS9_PIN_BANK_* and fix tables [not found] ` <CGME20251202093028epcas2p456b6a2bfebfc76384f706a9962266fcf@epcas2p4.samsung.com> @ 2025-12-02 9:36 ` Youngmin Nam 2025-12-17 4:46 ` Alim Akhtar 2025-12-28 11:41 ` Krzysztof Kozlowski 0 siblings, 2 replies; 19+ messages in thread From: Youngmin Nam @ 2025-12-02 9:36 UTC (permalink / raw) To: krzk, s.nawrocki, alim.akhtar, linus.walleij, peter.griffin, semen.protsenko, ivo.ivanov.ivanov1 Cc: ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel, Youngmin Nam Several Exynos9-era pin-bank tables were implicitly assuming that the filter control (FLTCON) registers are laid out contiguously from the EINT base offset. Per the TRMs this is not always true. FLTCON can live at a separate per-bank offset, and the current tables cause the driver to program the wrong FLTCON addresses for some banks. - Extends EXYNOS9_PIN_BANK_EINTG()/EINTW() to take an explicit .eint_fltcon_offset parameter. - Updates pin-bank tables with the correct FLTCON offsets for: Exynos2200 (ALIVE/CMGP/HSI1/UFS/HSI1UFS/PERIC0/1/2/VTS), Exynos7870 (ALIVE/DISPAUD/ESE/FSYS/MIF/NFC/TOP/TOUCH), Exynos7885 (ALIVE/DISPAUD/FSYS/TOP), Exynos850 (ALIVE/CMGP/AUD/HSI/CORE/PERI), Exynos990 (ALIVE/CMGP/HSI1/HSI2/PERIC0/1/VTS), Exynos9810 (ALIVE/AUD/CHUB/CMGP/FSYS0/FSYS1/PERIC0/1/VTS), ExynosAuto v9 (ALIVE/AUD/FSYS0/1/2/PERIC0/1), Exynos8890 (ALIVE/AUD/CCORE/ESE/FP/FSYS0/1/NFC/PERIC0/1/TOUCH), Exynos8895 (ALIVE/ABOX/VTS/FSYS0/1/BUSC/PERIC0/1), and FSD (FSYS/PERIC). Notes: - GS101 already programs per-bank filter control registers. This change aligns the Exynos9 path with that model. - Banks without filters (EINTN) are unaffected. Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Tested-by: Sam Protsenko <semen.protsenko@linaro.org> --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 744 +++++++++--------- drivers/pinctrl/samsung/pinctrl-exynos.h | 34 +- 2 files changed, 390 insertions(+), 388 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index b4a7d86b82fe..92ae1bc80f9c 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -90,11 +90,11 @@ static atomic_t exynos_shared_retention_refcnt; /* pin banks of exynos2200 pin-controller - ALIVE */ static const struct samsung_pin_bank_data exynos2200_pin_banks0[] __initconst = { - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x0, "gpa0", 0x00), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x20, "gpa1", 0x04), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x40, "gpa2", 0x08), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x60, "gpa3", 0x0c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x80, "gpa4", 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x0, "gpa0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x20, "gpa1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x40, "gpa2", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x60, "gpa3", 0x0c, 0x18), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x80, "gpa4", 0x10, 0x20), EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 4, 0xa0, "gpq0"), EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 2, 0xc0, "gpq1"), EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 2, 0xe0, "gpq2"), @@ -102,90 +102,90 @@ static const struct samsung_pin_bank_data exynos2200_pin_banks0[] __initconst = /* pin banks of exynos2200 pin-controller - CMGP */ static const struct samsung_pin_bank_data exynos2200_pin_banks1[] __initconst = { - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x0, "gpm0", 0x00), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x20, "gpm1", 0x04), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x40, "gpm2", 0x08), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x60, "gpm3", 0x0c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x80, "gpm4", 0x10), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0xa0, "gpm5", 0x14), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0xc0, "gpm6", 0x18), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0xe0, "gpm7", 0x1c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x100, "gpm8", 0x20), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x120, "gpm9", 0x24), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x140, "gpm10", 0x28), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x160, "gpm11", 0x2c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x180, "gpm12", 0x30), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x1a0, "gpm13", 0x34), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1c0, "gpm14", 0x38), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1e0, "gpm15", 0x3c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x200, "gpm16", 0x40), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x220, "gpm17", 0x44), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x240, "gpm20", 0x48), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x260, "gpm21", 0x4c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x280, "gpm22", 0x50), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x2a0, "gpm23", 0x54), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x2c0, "gpm24", 0x58), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x0, "gpm0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x20, "gpm1", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x40, "gpm2", 0x08, 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x60, "gpm3", 0x0c, 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x80, "gpm4", 0x10, 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0xa0, "gpm5", 0x14, 0x14), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0xc0, "gpm6", 0x18, 0x18), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0xe0, "gpm7", 0x1c, 0x1c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x100, "gpm8", 0x20, 0x20), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x120, "gpm9", 0x24, 0x24), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x140, "gpm10", 0x28, 0x28), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x160, "gpm11", 0x2c, 0x2c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x180, "gpm12", 0x30, 0x30), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x1a0, "gpm13", 0x34, 0x34), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1c0, "gpm14", 0x38, 0x38), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1e0, "gpm15", 0x3c, 0x3c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x200, "gpm16", 0x40, 0x40), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x220, "gpm17", 0x44, 0x44), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x240, "gpm20", 0x48, 0x48), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x260, "gpm21", 0x4c, 0x4c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x280, "gpm22", 0x50, 0x50), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x2a0, "gpm23", 0x54, 0x54), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x2c0, "gpm24", 0x58, 0x58), }; /* pin banks of exynos2200 pin-controller - HSI1 */ static const struct samsung_pin_bank_data exynos2200_pin_banks2[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0, "gpf0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0, "gpf0", 0x00, 0x00), }; /* pin banks of exynos2200 pin-controller - UFS */ static const struct samsung_pin_bank_data exynos2200_pin_banks3[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x0, "gpf1", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x0, "gpf1", 0x00, 0x00), }; /* pin banks of exynos2200 pin-controller - HSI1UFS */ static const struct samsung_pin_bank_data exynos2200_pin_banks4[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x0, "gpf2", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x0, "gpf2", 0x00, 0x00), }; /* pin banks of exynos2200 pin-controller - PERIC0 */ static const struct samsung_pin_bank_data exynos2200_pin_banks5[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0, "gpb0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x20, "gpb1", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x40, "gpb2", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x60, "gpb3", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x80, "gpp4", 0x10), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0xa0, "gpc0", 0x14), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0xc0, "gpc1", 0x18), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0xe0, "gpc2", 0x1c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x100, "gpg1", 0x20), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x120, "gpg2", 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0, "gpb0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x20, "gpb1", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x40, "gpb2", 0x08, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x60, "gpb3", 0x0c, 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x80, "gpp4", 0x10, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0xa0, "gpc0", 0x14, 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0xc0, "gpc1", 0x18, 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0xe0, "gpc2", 0x1c, 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x100, "gpg1", 0x20, 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x120, "gpg2", 0x24, 0x24), }; /* pin banks of exynos2200 pin-controller - PERIC1 */ static const struct samsung_pin_bank_data exynos2200_pin_banks6[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0, "gpp7", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x20, "gpp8", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x40, "gpp9", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x60, "gpp10", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0, "gpp7", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x20, "gpp8", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x40, "gpp9", 0x08, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x60, "gpp10", 0x0c, 0x0c), }; /* pin banks of exynos2200 pin-controller - PERIC2 */ static const struct samsung_pin_bank_data exynos2200_pin_banks7[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0, "gpp0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x20, "gpp1", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x40, "gpp2", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x60, "gpp3", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x80, "gpp5", 0x10), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0xa0, "gpp6", 0x14), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0xc0, "gpp11", 0x18), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0xe0, "gpc3", 0x1c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x100, "gpc4", 0x20), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x120, "gpc5", 0x24), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x140, "gpc6", 0x28), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x160, "gpc7", 0x2c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x180, "gpc8", 0x30), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x1a0, "gpc9", 0x34), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x1c0, "gpg0", 0x38), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0, "gpp0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x20, "gpp1", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x40, "gpp2", 0x08, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x60, "gpp3", 0x0c, 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x80, "gpp5", 0x10, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0xa0, "gpp6", 0x14, 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0xc0, "gpp11", 0x18, 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0xe0, "gpc3", 0x1c, 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x100, "gpc4", 0x20, 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x120, "gpc5", 0x24, 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x140, "gpc6", 0x28, 0x28), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x160, "gpc7", 0x2c, 0x2c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x180, "gpc8", 0x30, 0x30), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x1a0, "gpc9", 0x34, 0x34), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x1c0, "gpg0", 0x38, 0x38), }; /* pin banks of exynos2200 pin-controller - VTS */ static const struct samsung_pin_bank_data exynos2200_pin_banks8[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x0, "gpv0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x0, "gpv0", 0x00, 0x00), }; static const struct samsung_pin_ctrl exynos2200_pin_ctrl[] = { @@ -640,68 +640,68 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { static const struct samsung_pin_bank_data exynos7870_pin_banks0[] __initconst = { EXYNOS9_PIN_BANK_EINTN(exynos7870_bank_type_alive, 6, 0x000, "etc0"), EXYNOS9_PIN_BANK_EINTN(exynos7870_bank_type_alive, 3, 0x020, "etc1"), - EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x040, "gpa0", 0x00), - EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x060, "gpa1", 0x04), - EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x080, "gpa2", 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x040, "gpa0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x060, "gpa1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x080, "gpa2", 0x08, 0x10), EXYNOS9_PIN_BANK_EINTN(exynos7870_bank_type_alive, 2, 0x0c0, "gpq0"), }; /* pin banks of exynos7870 pin-controller 1 (DISPAUD) */ static const struct samsung_pin_bank_data exynos7870_pin_banks1[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x000, "gpz0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x020, "gpz1", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x040, "gpz2", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x000, "gpz0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x020, "gpz1", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x040, "gpz2", 0x08, 0x0c), }; /* pin banks of exynos7870 pin-controller 2 (ESE) */ static const struct samsung_pin_bank_data exynos7870_pin_banks2[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x000, "gpc7", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x000, "gpc7", 0x00, 0x00), }; /* pin banks of exynos7870 pin-controller 3 (FSYS) */ static const struct samsung_pin_bank_data exynos7870_pin_banks3[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x000, "gpr0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x020, "gpr1", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x040, "gpr2", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x060, "gpr3", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x080, "gpr4", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x000, "gpr0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x020, "gpr1", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x040, "gpr2", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x060, "gpr3", 0x0c, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x080, "gpr4", 0x10, 0x14), }; /* pin banks of exynos7870 pin-controller 4 (MIF) */ static const struct samsung_pin_bank_data exynos7870_pin_banks4[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x000, "gpm0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x000, "gpm0", 0x00, 0x00), }; /* pin banks of exynos7870 pin-controller 5 (NFC) */ static const struct samsung_pin_bank_data exynos7870_pin_banks5[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x000, "gpc2", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x000, "gpc2", 0x00, 0x00), }; /* pin banks of exynos7870 pin-controller 6 (TOP) */ static const struct samsung_pin_bank_data exynos7870_pin_banks6[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x000, "gpb0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x020, "gpc0", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x040, "gpc1", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x060, "gpc4", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x080, "gpc5", 0x10), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x0a0, "gpc6", 0x14), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0c0, "gpc8", 0x18), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0e0, "gpc9", 0x1c), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 7, 0x100, "gpd1", 0x20), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x120, "gpd2", 0x24), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x140, "gpd3", 0x28), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 7, 0x160, "gpd4", 0x2c), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x1a0, "gpe0", 0x34), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x1c0, "gpf0", 0x38), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x1e0, "gpf1", 0x3c), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x200, "gpf2", 0x40), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x220, "gpf3", 0x44), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x240, "gpf4", 0x48), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x000, "gpb0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x020, "gpc0", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x040, "gpc1", 0x08, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x060, "gpc4", 0x0c, 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x080, "gpc5", 0x10, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x0a0, "gpc6", 0x14, 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0c0, "gpc8", 0x18, 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0e0, "gpc9", 0x1c, 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 7, 0x100, "gpd1", 0x20, 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x120, "gpd2", 0x24, 0x28), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x140, "gpd3", 0x28, 0x30), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 7, 0x160, "gpd4", 0x2c, 0x38), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x1a0, "gpe0", 0x34, 0x48), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x1c0, "gpf0", 0x38, 0x4c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x1e0, "gpf1", 0x3c, 0x50), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x200, "gpf2", 0x40, 0x54), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x220, "gpf3", 0x44, 0x58), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x240, "gpf4", 0x48, 0x5c), }; /* pin banks of exynos7870 pin-controller 7 (TOUCH) */ static const struct samsung_pin_bank_data exynos7870_pin_banks7[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x000, "gpc3", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x000, "gpc3", 0x00, 0x00), }; static const struct samsung_pin_ctrl exynos7870_pin_ctrl[] __initconst = { @@ -770,46 +770,46 @@ const struct samsung_pinctrl_of_match_data exynos7870_of_data __initconst = { static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = { EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 3, 0x000, "etc0"), EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 3, 0x020, "etc1"), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x040, "gpa0", 0x00), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x060, "gpa1", 0x04), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x080, "gpa2", 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x040, "gpa0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x060, "gpa1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x080, "gpa2", 0x08, 0x10), EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 5, 0x0a0, "gpq0"), }; /* pin banks of exynos7885 pin-controller 1 (DISPAUD) */ static const struct samsung_pin_bank_data exynos7885_pin_banks1[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x000, "gpb0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x020, "gpb1", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x040, "gpb2", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x000, "gpb0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x020, "gpb1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x040, "gpb2", 0x08, 0x0c), }; /* pin banks of exynos7885 pin-controller 2 (FSYS) */ static const struct samsung_pin_bank_data exynos7885_pin_banks2[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpf0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpf2", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x040, "gpf3", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x060, "gpf4", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpf0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpf2", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x040, "gpf3", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x060, "gpf4", 0x0c, 0x14), }; /* pin banks of exynos7885 pin-controller 3 (TOP) */ static const struct samsung_pin_bank_data exynos7885_pin_banks3[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpp0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x020, "gpg0", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x040, "gpp1", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x060, "gpp2", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x080, "gpp3", 0x10), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x0a0, "gpp4", 0x14), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0c0, "gpp5", 0x18), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x0e0, "gpp6", 0x1c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x100, "gpp7", 0x20), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x120, "gpp8", 0x24), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x140, "gpg1", 0x28), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x160, "gpg2", 0x2c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x180, "gpg3", 0x30), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x1a0, "gpg4", 0x34), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x1c0, "gpc0", 0x38), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x1e0, "gpc1", 0x3c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x200, "gpc2", 0x40), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpp0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x020, "gpg0", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x040, "gpp1", 0x08, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x060, "gpp2", 0x0c, 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x080, "gpp3", 0x10, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x0a0, "gpp4", 0x14, 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0c0, "gpp5", 0x18, 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x0e0, "gpp6", 0x1c, 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x100, "gpp7", 0x20, 0x28), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x120, "gpp8", 0x24, 0x2c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x140, "gpg1", 0x28, 0x30), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x160, "gpg2", 0x2c, 0x38), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x180, "gpg3", 0x30, 0x40), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x1a0, "gpg4", 0x34, 0x48), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x1c0, "gpc0", 0x38, 0x4c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x1e0, "gpc1", 0x3c, 0x50), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x200, "gpc2", 0x40, 0x58), }; static const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = { @@ -850,59 +850,59 @@ const struct samsung_pinctrl_of_match_data exynos7885_of_data __initconst = { /* pin banks of exynos850 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x000, "gpa0", 0x00), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x020, "gpa1", 0x04), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x040, "gpa2", 0x08), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x060, "gpa3", 0x0c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 4, 0x080, "gpa4", 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x000, "gpa0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x020, "gpa1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x040, "gpa2", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x060, "gpa3", 0x0c, 0x18), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 4, 0x080, "gpa4", 0x10, 0x20), EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 3, 0x0a0, "gpq0"), }; /* pin banks of exynos850 pin-controller 1 (CMGP) */ static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x000, "gpm0", 0x00), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x020, "gpm1", 0x04), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x040, "gpm2", 0x08), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x060, "gpm3", 0x0c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x080, "gpm4", 0x10), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0a0, "gpm5", 0x14), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0c0, "gpm6", 0x18), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0e0, "gpm7", 0x1c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x000, "gpm0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x020, "gpm1", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x040, "gpm2", 0x08, 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x060, "gpm3", 0x0c, 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x080, "gpm4", 0x10, 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0a0, "gpm5", 0x14, 0x14), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0c0, "gpm6", 0x18, 0x18), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0e0, "gpm7", 0x1c, 0x1c), }; /* pin banks of exynos850 pin-controller 2 (AUD) */ static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x000, "gpb0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x020, "gpb1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x000, "gpb0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x020, "gpb1", 0x04, 0x08), }; /* pin banks of exynos850 pin-controller 3 (HSI) */ static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x000, "gpf2", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x000, "gpf2", 0x00, 0x00), }; /* pin banks of exynos850 pin-controller 4 (CORE) */ static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpf0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpf1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpf0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpf1", 0x04, 0x04), }; /* pin banks of exynos850 pin-controller 5 (PERI) */ static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x000, "gpg0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x020, "gpp0", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x040, "gpp1", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x060, "gpp2", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpg1", 0x10), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0a0, "gpg2", 0x14), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 1, 0x0c0, "gpg3", 0x18), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x0e0, "gpc0", 0x1c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x100, "gpc1", 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x000, "gpg0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x020, "gpp0", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x040, "gpp1", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x060, "gpp2", 0x0c, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpg1", 0x10, 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0a0, "gpg2", 0x14, 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 1, 0x0c0, "gpg3", 0x18, 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x0e0, "gpc0", 0x1c, 0x28), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x100, "gpc1", 0x20, 0x2c), }; static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { @@ -946,11 +946,11 @@ const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { /* pin banks of exynos990 pin-controller 0 (ALIVE) */ static struct samsung_pin_bank_data exynos990_pin_banks0[] = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x000, "gpa0", 0x00), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x020, "gpa1", 0x04), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x040, "gpa2", 0x08), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x060, "gpa3", 0x0c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x080, "gpa4", 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x000, "gpa0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x020, "gpa1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x040, "gpa2", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x060, "gpa3", 0x0c, 0x18), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x080, "gpa4", 0x10, 0x20), EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 7, 0x0a0, "gpq0"), }; @@ -961,82 +961,82 @@ static struct samsung_pin_bank_data exynos990_pin_banks1[] = { EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 1, 0x020, "gpm1"), EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 1, 0x040, "gpm2"), EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 1, 0x060, "gpm3"), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x080, "gpm4", 0x00), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0a0, "gpm5", 0x04), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0c0, "gpm6", 0x08), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0e0, "gpm7", 0x0c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x100, "gpm8", 0x10), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x120, "gpm9", 0x14), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x140, "gpm10", 0x18), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x160, "gpm11", 0x1c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x180, "gpm12", 0x20), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1a0, "gpm13", 0x24), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1c0, "gpm14", 0x28), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1e0, "gpm15", 0x2c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x200, "gpm16", 0x30), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x220, "gpm17", 0x34), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x240, "gpm18", 0x38), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x260, "gpm19", 0x3c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x280, "gpm20", 0x40), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x2a0, "gpm21", 0x44), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x2c0, "gpm22", 0x48), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x2e0, "gpm23", 0x4c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x300, "gpm24", 0x50), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x320, "gpm25", 0x54), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x340, "gpm26", 0x58), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x360, "gpm27", 0x5c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x380, "gpm28", 0x60), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x3a0, "gpm29", 0x64), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x3c0, "gpm30", 0x68), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x3e0, "gpm31", 0x6c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x400, "gpm32", 0x70), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x420, "gpm33", 0x74), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x080, "gpm4", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0a0, "gpm5", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0c0, "gpm6", 0x08, 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0e0, "gpm7", 0x0c, 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x100, "gpm8", 0x10, 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x120, "gpm9", 0x14, 0x14), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x140, "gpm10", 0x18, 0x18), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x160, "gpm11", 0x1c, 0x1c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x180, "gpm12", 0x20, 0x20), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1a0, "gpm13", 0x24, 0x24), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1c0, "gpm14", 0x28, 0x28), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1e0, "gpm15", 0x2c, 0x2c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x200, "gpm16", 0x30, 0x30), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x220, "gpm17", 0x34, 0x34), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x240, "gpm18", 0x38, 0x38), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x260, "gpm19", 0x3c, 0x3c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x280, "gpm20", 0x40, 0x40), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x2a0, "gpm21", 0x44, 0x44), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x2c0, "gpm22", 0x48, 0x48), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x2e0, "gpm23", 0x4c, 0x4c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x300, "gpm24", 0x50, 0x50), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x320, "gpm25", 0x54, 0x54), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x340, "gpm26", 0x58, 0x58), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x360, "gpm27", 0x5c, 0x5c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x380, "gpm28", 0x60, 0x60), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x3a0, "gpm29", 0x64, 0x64), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x3c0, "gpm30", 0x68, 0x68), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x3e0, "gpm31", 0x6c, 0x6c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x400, "gpm32", 0x70, 0x70), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x420, "gpm33", 0x74, 0x74), }; /* pin banks of exynos990 pin-controller 2 (HSI1) */ static struct samsung_pin_bank_data exynos990_pin_banks2[] = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpf0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x020, "gpf1", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x040, "gpf2", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpf0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x020, "gpf1", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x040, "gpf2", 0x08, 0x0c), }; /* pin banks of exynos990 pin-controller 3 (HSI2) */ static struct samsung_pin_bank_data exynos990_pin_banks3[] = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x000, "gpf3", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x000, "gpf3", 0x00, 0x00), }; /* pin banks of exynos990 pin-controller 4 (PERIC0) */ static struct samsung_pin_bank_data exynos990_pin_banks4[] = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp1", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpp2", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpp3", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpp4", 0x10), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x0a0, "gpg0", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpp2", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpp3", 0x0c, 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpp4", 0x10, 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x0a0, "gpg0", 0x14, 0x28), }; /* pin banks of exynos990 pin-controller 5 (PERIC1) */ static struct samsung_pin_bank_data exynos990_pin_banks5[] = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp5", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp6", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpp7", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpp8", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpp9", 0x10), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x0a0, "gpc0", 0x14), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0c0, "gpg1", 0x18), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0e0, "gpb0", 0x1c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x100, "gpb1", 0x20), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x120, "gpb2", 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp5", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp6", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpp7", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpp8", 0x0c, 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpp9", 0x10, 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x0a0, "gpc0", 0x14, 0x28), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0c0, "gpg1", 0x18, 0x30), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0e0, "gpb0", 0x1c, 0x34), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x100, "gpb1", 0x20, 0x3c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x120, "gpb2", 0x24, 0x44), }; /* pin banks of exynos990 pin-controller 6 (VTS) */ static struct samsung_pin_bank_data exynos990_pin_banks6[] = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x000, "gpv0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x000, "gpv0", 0x00, 0x00), }; static const struct samsung_pin_ctrl exynos990_pin_ctrl[] __initconst = { @@ -1085,87 +1085,87 @@ const struct samsung_pinctrl_of_match_data exynos990_of_data __initconst = { /* pin banks of exynos9810 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynos9810_pin_banks0[] __initconst = { EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 6, 0x000, "etc1"), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x020, "gpa0", 0x00), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x040, "gpa1", 0x04), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x060, "gpa2", 0x08), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x080, "gpa3", 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x020, "gpa0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x040, "gpa1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x060, "gpa2", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x080, "gpa3", 0x0c, 0x18), EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 6, 0x0a0, "gpq0"), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x0c0, "gpa4", 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x0C0, "gpa4", 0x10, 0x20), }; /* pin banks of exynos9810 pin-controller 1 (AUD) */ static const struct samsung_pin_bank_data exynos9810_pin_banks1[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x000, "gpb0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpb1", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x040, "gpb2", 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x000, "gpb0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpb1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x040, "gpb2", 0x08, 0x10), }; /* pin banks of exynos9810 pin-controller 2 (CHUB) */ static const struct samsung_pin_bank_data exynos9810_pin_banks2[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gph0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x020, "gph1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gph0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x020, "gph1", 0x04, 0x08), }; /* pin banks of exynos9810 pin-controller 3 (CMGP) */ static const struct samsung_pin_bank_data exynos9810_pin_banks3[] __initconst = { - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x000, "gpm0", 0x00), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x020, "gpm1", 0x04), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x040, "gpm2", 0x08), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x060, "gpm3", 0x0c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x080, "gpm4", 0x10), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0a0, "gpm5", 0x14), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0c0, "gpm6", 0x18), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0e0, "gpm7", 0x1c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x100, "gpm10", 0x20), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x120, "gpm11", 0x24), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x140, "gpm12", 0x28), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x160, "gpm13", 0x2c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x180, "gpm14", 0x30), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1a0, "gpm15", 0x34), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1c0, "gpm16", 0x38), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1e0, "gpm17", 0x3c), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x200, "gpm40", 0x40), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x220, "gpm41", 0x44), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x240, "gpm42", 0x48), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x260, "gpm43", 0x4c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x000, "gpm0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x020, "gpm1", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x040, "gpm2", 0x08, 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x060, "gpm3", 0x0c, 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x080, "gpm4", 0x10, 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0a0, "gpm5", 0x14, 0x14), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0c0, "gpm6", 0x18, 0x18), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x0e0, "gpm7", 0x1c, 0x1c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x100, "gpm10", 0x20, 0x20), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x120, "gpm11", 0x24, 0x24), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x140, "gpm12", 0x28, 0x28), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x160, "gpm13", 0x2c, 0x2c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x180, "gpm14", 0x30, 0x30), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1a0, "gpm15", 0x34, 0x34), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1c0, "gpm16", 0x38, 0x38), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x1e0, "gpm17", 0x3c, 0x3c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x200, "gpm40", 0x40, 0x40), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x220, "gpm41", 0x44, 0x44), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x240, "gpm42", 0x48, 0x48), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 1, 0x260, "gpm43", 0x4c, 0x4c), }; /* pin banks of exynos9810 pin-controller 4 (FSYS0) */ static const struct samsung_pin_bank_data exynos9810_pin_banks4[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x000, "gpf0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x000, "gpf0", 0x00, 0x00), }; /* pin banks of exynos9810 pin-controller 5 (FSYS1) */ static const struct samsung_pin_bank_data exynos9810_pin_banks5[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x000, "gpf1", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x020, "gpf2", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x000, "gpf1", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x020, "gpf2", 0x04, 0x08), }; /* pin banks of exynos9810 pin-controller 6 (PERIC0) */ static const struct samsung_pin_bank_data exynos9810_pin_banks6[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp1", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpp2", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x060, "gpp3", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpg0", 0x10), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0a0, "gpg1", 0x14), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0c0, "gpg2", 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpp2", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x060, "gpp3", 0x0c, 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpg0", 0x10, 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0a0, "gpg1", 0x14, 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0c0, "gpg2", 0x18, 0x2c), }; /* pin banks of exynos9810 pin-controller 7 (PERIC1) */ static const struct samsung_pin_bank_data exynos9810_pin_banks7[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp4", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp5", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x040, "gpp6", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpc0", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpc1", 0x10), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0a0, "gpd0", 0x14), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x0c0, "gpg3", 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp4", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp5", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x040, "gpp6", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpc0", 0x0c, 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpc1", 0x10, 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0a0, "gpd0", 0x14, 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x0c0, "gpg3", 0x18, 0x28), }; /* pin banks of exynos9810 pin-controller 8 (VTS) */ static const struct samsung_pin_bank_data exynos9810_pin_banks8[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x000, "gpt0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x000, "gpt0", 0x00, 0x00), }; static const struct samsung_pin_ctrl exynos9810_pin_ctrl[] __initconst = { @@ -1238,55 +1238,55 @@ const struct samsung_pinctrl_of_match_data exynos9810_of_data __initconst = { /* pin banks of exynosautov9 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = { - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x000, "gpa0", 0x00), - EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x020, "gpa1", 0x04), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x000, "gpa0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x020, "gpa1", 0x04, 0x08), EXYNOS9_PIN_BANK_EINTN(exynos9_bank_type_alive, 2, 0x040, "gpq0"), }; /* pin banks of exynosautov9 pin-controller 1 (AUD) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks1[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x000, "gpb0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpb1", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpb2", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpb3", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x000, "gpb0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpb1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpb2", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpb3", 0x0c, 0x18), }; /* pin banks of exynosautov9 pin-controller 2 (FSYS0) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks2[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x000, "gpf0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x020, "gpf1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x000, "gpf0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x020, "gpf1", 0x04, 0x08), }; /* pin banks of exynosautov9 pin-controller 3 (FSYS1) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks3[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x000, "gpf8", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x000, "gpf8", 0x00, 0x00), }; /* pin banks of exynosautov9 pin-controller 4 (FSYS2) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks4[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpf2", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpf3", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x040, "gpf4", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpf5", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x080, "gpf6", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpf2", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpf3", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x040, "gpf4", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpf5", 0x0c, 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x080, "gpf6", 0x10, 0x1c), }; /* pin banks of exynosautov9 pin-controller 5 (PERIC0) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks5[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp1", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpp2", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x060, "gpg0", 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpp2", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x060, "gpg0", 0x0c, 0x18), }; /* pin banks of exynosautov9 pin-controller 6 (PERIC1) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks6[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp3", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp4", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpp5", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpg1", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpg2", 0x10), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0a0, "gpg3", 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x000, "gpp3", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x020, "gpp4", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpp5", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpg1", 0x0c, 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpg2", 0x10, 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0a0, "gpg3", 0x14, 0x28), }; static const struct samsung_pin_ctrl exynosautov9_pin_ctrl[] __initconst = { @@ -1487,16 +1487,16 @@ const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = /* pin banks of exynos8890 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynos8890_pin_banks0[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x000, "gpa0", 0x00), - EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x020, "gpa1", 0x04), - EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x040, "gpa2", 0x08), - EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x060, "gpa3", 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x000, "gpa0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x020, "gpa1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x040, "gpa2", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos7870_bank_type_alive, 8, 0x060, "gpa3", 0x0c, 0x18), }; /* pin banks of exynos8890 pin-controller 1 (AUD) */ static const struct samsung_pin_bank_data exynos8890_pin_banks1[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 7, 0x000, "gph0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 7, 0x000, "gph0", 0x00, 0x00), }; /* pin banks of exynos8890 pin-controller 2 (CCORE) */ @@ -1508,73 +1508,73 @@ static const struct samsung_pin_bank_data exynos8890_pin_banks2[] __initconst = /* pin banks of exynos8890 pin-controller 3 (ESE) */ static const struct samsung_pin_bank_data exynos8890_pin_banks3[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x000, "gpf3", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x000, "gpf3", 0x00, 0x00), }; /* pin banks of exynos8890 pin-controller 4 (FP) */ static const struct samsung_pin_bank_data exynos8890_pin_banks4[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x000, "gpf2", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x000, "gpf2", 0x00, 0x00), }; /* pin banks of exynos8890 pin-controller 5 (FSYS0) */ static const struct samsung_pin_bank_data exynos8890_pin_banks5[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos5433_bank_type_off, 4, 0x000, "gpi1", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos5433_bank_type_off, 8, 0x020, "gpi2", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos5433_bank_type_off, 4, 0x000, "gpi1", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos5433_bank_type_off, 8, 0x020, "gpi2", 0x04, 0x04), }; /* pin banks of exynos8890 pin-controller 6 (FSYS1) */ static const struct samsung_pin_bank_data exynos8890_pin_banks6[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 7, 0x000, "gpj0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 7, 0x000, "gpj0", 0x00, 0x00), }; /* pin banks of exynos8890 pin-controller 7 (NFC) */ static const struct samsung_pin_bank_data exynos8890_pin_banks7[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x000, "gpf0", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x000, "gpf0", 0x00, 0x00), }; /* pin banks of exynos8890 pin-controller 8 (PERIC0) */ static const struct samsung_pin_bank_data exynos8890_pin_banks8[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x000, "gpi0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x020, "gpd0", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x040, "gpd1", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x060, "gpd2", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x080, "gpd3", 0x10), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0a0, "gpb1", 0x14), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0c0, "gpb2", 0x18), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x0e0, "gpb0", 0x1c), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x100, "gpc0", 0x20), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x120, "gpc1", 0x24), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x140, "gpc2", 0x28), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x160, "gpc3", 0x2c), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x180, "gpk0", 0x30), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x000, "gpi0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x020, "gpd0", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x040, "gpd1", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x060, "gpd2", 0x0c, 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x080, "gpd3", 0x10, 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0a0, "gpb1", 0x14, 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x0c0, "gpb2", 0x18, 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x0e0, "gpb0", 0x1c, 0x28), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x100, "gpc0", 0x20, 0x2c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 5, 0x120, "gpc1", 0x24, 0x34), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 6, 0x140, "gpc2", 0x28, 0x3c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x160, "gpc3", 0x2c, 0x44), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x180, "gpk0", 0x30, 0x4c), EXYNOS9_PIN_BANK_EINTN(exynos8895_bank_type_off, 7, 0x1a0, "etc1"), }; /* pin banks of exynos8890 pin-controller 9 (PERIC1) */ static const struct samsung_pin_bank_data exynos8890_pin_banks9[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x000, "gpe0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x020, "gpe5", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x040, "gpe6", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x060, "gpj1", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x080, "gpj2", 0x10), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0a0, "gpe2", 0x14), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0c0, "gpe3", 0x18), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0e0, "gpe4", 0x1c), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x100, "gpe1", 0x20), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x120, "gpe7", 0x24), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x140, "gpg0", 0x28), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x000, "gpe0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x020, "gpe5", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x040, "gpe6", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x060, "gpj1", 0x0c, 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 2, 0x080, "gpj2", 0x10, 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0a0, "gpe2", 0x14, 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0c0, "gpe3", 0x18, 0x2c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x0e0, "gpe4", 0x1c, 0x34), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x100, "gpe1", 0x20, 0x3c), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 4, 0x120, "gpe7", 0x24, 0x44), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x140, "gpg0", 0x28, 0x48), }; /* pin banks of exynos8890 pin-controller 10 (TOUCH) */ static const struct samsung_pin_bank_data exynos8890_pin_banks10[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x000, "gpf1", 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x000, "gpf1", 0x00, 0x00), }; static const struct samsung_pin_ctrl exynos8890_pin_ctrl[] __initconst = { @@ -1643,69 +1643,69 @@ const struct samsung_pinctrl_of_match_data exynos8890_of_data __initconst = { /* pin banks of exynos8895 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynos8895_pin_banks0[] __initconst = { - EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x020, "gpa0", 0x00), - EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x040, "gpa1", 0x04), - EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x060, "gpa2", 0x08), - EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x080, "gpa3", 0x0c), + EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x020, "gpa0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x040, "gpa1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x060, "gpa2", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTW(bank_type_alive, 8, 0x080, "gpa3", 0x0c, 0x18), EXYNOS9_PIN_BANK_EINTN(bank_type_alive, 7, 0x0a0, "gpa4"), }; /* pin banks of exynos8895 pin-controller 1 (ABOX) */ static const struct samsung_pin_bank_data exynos8895_pin_banks1[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x000, "gph0", 0x00), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 7, 0x020, "gph1", 0x04), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x040, "gph3", 0x08), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x000, "gph0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 7, 0x020, "gph1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x040, "gph3", 0x08, 0x10), }; /* pin banks of exynos8895 pin-controller 2 (VTS) */ static const struct samsung_pin_bank_data exynos8895_pin_banks2[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 3, 0x000, "gph2", 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 3, 0x000, "gph2", 0x00, 0x00), }; /* pin banks of exynos8895 pin-controller 3 (FSYS0) */ static const struct samsung_pin_bank_data exynos8895_pin_banks3[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x000, "gpi0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x020, "gpi1", 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 3, 0x000, "gpi0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos8895_bank_type_off, 8, 0x020, "gpi1", 0x04, 0x04), }; /* pin banks of exynos8895 pin-controller 4 (FSYS1) */ static const struct samsung_pin_bank_data exynos8895_pin_banks4[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x000, "gpj1", 0x00), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 7, 0x020, "gpj0", 0x04), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x000, "gpj1", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 7, 0x020, "gpj0", 0x04, 0x08), }; /* pin banks of exynos8895 pin-controller 5 (BUSC) */ static const struct samsung_pin_bank_data exynos8895_pin_banks5[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 2, 0x000, "gpb2", 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 2, 0x000, "gpb2", 0x00, 0x00), }; /* pin banks of exynos8895 pin-controller 6 (PERIC0) */ static const struct samsung_pin_bank_data exynos8895_pin_banks6[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x000, "gpd0", 0x00), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x020, "gpd1", 0x04), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x040, "gpd2", 0x08), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 5, 0x060, "gpd3", 0x0C), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x080, "gpb1", 0x10), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0a0, "gpe7", 0x14), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0c0, "gpf1", 0x18), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x000, "gpd0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x020, "gpd1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x040, "gpd2", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 5, 0x060, "gpd3", 0x0C, 0x14), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x080, "gpb1", 0x10, 0x1c), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0a0, "gpe7", 0x14, 0x20), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0c0, "gpf1", 0x18, 0x28), }; /* pin banks of exynos8895 pin-controller 7 (PERIC1) */ static const struct samsung_pin_bank_data exynos8895_pin_banks7[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 3, 0x000, "gpb0", 0x00), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 5, 0x020, "gpc0", 0x04), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 5, 0x040, "gpc1", 0x08), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x060, "gpc2", 0x0c), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x080, "gpc3", 0x10), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x0a0, "gpk0", 0x14), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0c0, "gpe5", 0x18), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0e0, "gpe6", 0x1c), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x100, "gpe2", 0x20), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x120, "gpe3", 0x24), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x140, "gpe4", 0x28), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x160, "gpf0", 0x2c), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x180, "gpe1", 0x30), - EXYNOS9_PIN_BANK_EINTG(bank_type_off, 2, 0x1a0, "gpg0", 0x34), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 3, 0x000, "gpb0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 5, 0x020, "gpc0", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 5, 0x040, "gpc1", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x060, "gpc2", 0x0c, 0x14), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x080, "gpc3", 0x10, 0x1c), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x0a0, "gpk0", 0x14, 0x24), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0c0, "gpe5", 0x18, 0x28), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x0e0, "gpe6", 0x1c, 0x30), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x100, "gpe2", 0x20, 0x38), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x120, "gpe3", 0x24, 0x40), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x140, "gpe4", 0x28, 0x48), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 4, 0x160, "gpf0", 0x2c, 0x50), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 8, 0x180, "gpe1", 0x30, 0x54), + EXYNOS9_PIN_BANK_EINTG(bank_type_off, 2, 0x1a0, "gpg0", 0x34, 0x5c), }; static const struct samsung_pin_ctrl exynos8895_pin_ctrl[] __initconst = { @@ -1776,36 +1776,36 @@ const struct samsung_pinctrl_of_match_data exynos8895_of_data __initconst = { /* pin banks of FSD pin-controller 0 (FSYS) */ static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x00, "gpf0", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x20, "gpf1", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x40, "gpf6", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x60, "gpf4", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x80, "gpf5", 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x00, "gpf0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x20, "gpf1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x40, "gpf6", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x60, "gpf4", 0x0c, 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x80, "gpf5", 0x10, 0x18), }; /* pin banks of FSD pin-controller 1 (PERIC) */ static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = { - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpc8", 0x00), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x020, "gpf2", 0x04), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpf3", 0x08), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpd0", 0x0c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpb0", 0x10), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0a0, "gpb1", 0x14), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0c0, "gpb4", 0x18), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0e0, "gpb5", 0x1c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x100, "gpb6", 0x20), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x120, "gpb7", 0x24), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x140, "gpd1", 0x28), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x160, "gpd2", 0x2c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x180, "gpd3", 0x30), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x1a0, "gpg0", 0x34), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x1c0, "gpg1", 0x38), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x1e0, "gpg2", 0x3c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x200, "gpg3", 0x40), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x220, "gpg4", 0x44), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x240, "gpg5", 0x48), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x260, "gpg6", 0x4c), - EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x280, "gpg7", 0x50), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x000, "gpc8", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x020, "gpf2", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x040, "gpf3", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x060, "gpd0", 0x0c, 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x080, "gpb0", 0x10, 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0a0, "gpb1", 0x14, 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0c0, "gpb4", 0x18, 0x2c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x0e0, "gpb5", 0x1c, 0x34), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x100, "gpb6", 0x20, 0x38), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x120, "gpb7", 0x24, 0x40), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x140, "gpd1", 0x28, 0x48), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x160, "gpd2", 0x2c, 0x50), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x180, "gpd3", 0x30, 0x58), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x1a0, "gpg0", 0x34, 0x60), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x1c0, "gpg1", 0x38, 0x68), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x1e0, "gpg2", 0x3c, 0x70), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x200, "gpg3", 0x40, 0x78), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x220, "gpg4", 0x44, 0x80), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x240, "gpg5", 0x48, 0x88), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x260, "gpg6", 0x4c, 0x90), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x280, "gpg7", 0x50, 0x98), }; /* pin banks of FSD pin-controller 2 (PMU) */ diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index 41cec8408d0d..7ebfdcaf2781 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -141,24 +141,26 @@ .name = id \ } -#define EXYNOS9_PIN_BANK_EINTG(bank_type, pins, reg, id, offs) \ - { \ - .type = &bank_type, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_GPIO, \ - .eint_offset = offs, \ - .name = id \ +#define EXYNOS9_PIN_BANK_EINTG(bank_type, pins, reg, id, offs, fltcon_offs) \ + { \ + .type = &bank_type, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .eint_fltcon_offset = fltcon_offs, \ + .name = id \ } -#define EXYNOS9_PIN_BANK_EINTW(bank_type, pins, reg, id, offs) \ - { \ - .type = &bank_type, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_WKUP, \ - .eint_offset = offs, \ - .name = id \ +#define EXYNOS9_PIN_BANK_EINTW(bank_type, pins, reg, id, offs, fltcon_offs) \ + { \ + .type = &bank_type, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .eint_fltcon_offset = fltcon_offs, \ + .name = id \ } #define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs) \ -- 2.52.0 ^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH v3 3/5] pinctrl: samsung: add per-bank FLTCON offset to EXYNOS9_PIN_BANK_* and fix tables 2025-12-02 9:36 ` [PATCH v3 3/5] pinctrl: samsung: add per-bank FLTCON offset to EXYNOS9_PIN_BANK_* and fix tables Youngmin Nam @ 2025-12-17 4:46 ` Alim Akhtar 2025-12-28 11:41 ` Krzysztof Kozlowski 1 sibling, 0 replies; 19+ messages in thread From: Alim Akhtar @ 2025-12-17 4:46 UTC (permalink / raw) To: 'Youngmin Nam', krzk, s.nawrocki, linus.walleij, peter.griffin, semen.protsenko, ivo.ivanov.ivanov1 Cc: ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel Hi Youngmin > -----Original Message----- > From: Youngmin Nam <youngmin.nam@samsung.com> > Sent: Tuesday, December 2, 2025 3:06 PM > To: krzk@kernel.org; s.nawrocki@samsung.com; alim.akhtar@samsung.com; > linus.walleij@linaro.org; peter.griffin@linaro.org; > semen.protsenko@linaro.org; ivo.ivanov.ivanov1@gmail.com > Cc: ryu.real@samsung.com; d7271.choe@samsung.com; > shin.son@samsung.com; jaewon02.kim@samsung.com; linux-arm- > kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux- > gpio@vger.kernel.org; linux-kernel@vger.kernel.org; Youngmin Nam > <youngmin.nam@samsung.com> > Subject: [PATCH v3 3/5] pinctrl: samsung: add per-bank FLTCON offset to > EXYNOS9_PIN_BANK_* and fix tables > > Several Exynos9-era pin-bank tables were implicitly assuming that the > filter control (FLTCON) registers are laid out contiguously from the > EINT base offset. Per the TRMs this is not always true. FLTCON can live > at a separate per-bank offset, and the current tables cause the driver > to program the wrong FLTCON addresses for some banks. > > - Extends EXYNOS9_PIN_BANK_EINTG()/EINTW() to take an explicit > .eint_fltcon_offset parameter. > - Updates pin-bank tables with the correct FLTCON offsets for: > Exynos2200 (ALIVE/CMGP/HSI1/UFS/HSI1UFS/PERIC0/1/2/VTS), > Exynos7870 (ALIVE/DISPAUD/ESE/FSYS/MIF/NFC/TOP/TOUCH), > Exynos7885 (ALIVE/DISPAUD/FSYS/TOP), > Exynos850 (ALIVE/CMGP/AUD/HSI/CORE/PERI), > Exynos990 (ALIVE/CMGP/HSI1/HSI2/PERIC0/1/VTS), > Exynos9810 (ALIVE/AUD/CHUB/CMGP/FSYS0/FSYS1/PERIC0/1/VTS), > ExynosAuto v9 (ALIVE/AUD/FSYS0/1/2/PERIC0/1), > Exynos8890 (ALIVE/AUD/CCORE/ESE/FP/FSYS0/1/NFC/PERIC0/1/TOUCH), > Exynos8895 (ALIVE/ABOX/VTS/FSYS0/1/BUSC/PERIC0/1), > and FSD (FSYS/PERIC). > > Notes: > - GS101 already programs per-bank filter control registers. This change > aligns the Exynos9 path with that model. > - Banks without filters (EINTN) are unaffected. > > Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Tested-by: Sam Protsenko <semen.protsenko@linaro.org> > --- Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Tested this series on Exynosautov920 sadk Tested-by: Alim Akhtar <alim.akhtar@samsung.com> ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 3/5] pinctrl: samsung: add per-bank FLTCON offset to EXYNOS9_PIN_BANK_* and fix tables 2025-12-02 9:36 ` [PATCH v3 3/5] pinctrl: samsung: add per-bank FLTCON offset to EXYNOS9_PIN_BANK_* and fix tables Youngmin Nam 2025-12-17 4:46 ` Alim Akhtar @ 2025-12-28 11:41 ` Krzysztof Kozlowski 2026-03-06 21:55 ` Peter Griffin 1 sibling, 1 reply; 19+ messages in thread From: Krzysztof Kozlowski @ 2025-12-28 11:41 UTC (permalink / raw) To: Youngmin Nam, s.nawrocki, alim.akhtar, linus.walleij, peter.griffin, semen.protsenko, ivo.ivanov.ivanov1 Cc: ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel On 02/12/2025 10:36, Youngmin Nam wrote: > Several Exynos9-era pin-bank tables were implicitly assuming that the > filter control (FLTCON) registers are laid out contiguously from the > EINT base offset. Per the TRMs this is not always true. FLTCON can live > at a separate per-bank offset, and the current tables cause the driver > to program the wrong FLTCON addresses for some banks. "Can live" or "Does live"? Adding unused offset is not improving the code. The implicit offset is fine, if it is correct. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 3/5] pinctrl: samsung: add per-bank FLTCON offset to EXYNOS9_PIN_BANK_* and fix tables 2025-12-28 11:41 ` Krzysztof Kozlowski @ 2026-03-06 21:55 ` Peter Griffin 0 siblings, 0 replies; 19+ messages in thread From: Peter Griffin @ 2026-03-06 21:55 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Youngmin Nam, s.nawrocki, alim.akhtar, linus.walleij, semen.protsenko, ivo.ivanov.ivanov1, ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel Hi Youngmin & Krzysztof, On Sun, 28 Dec 2025 at 11:41, Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On 02/12/2025 10:36, Youngmin Nam wrote: > > Several Exynos9-era pin-bank tables were implicitly assuming that the > > filter control (FLTCON) registers are laid out contiguously from the > > EINT base offset. Per the TRMs this is not always true. FLTCON can live > > at a separate per-bank offset, and the current tables cause the driver > > to program the wrong FLTCON addresses for some banks. > > "Can live" or "Does live"? Adding unused offset is not improving the > code. The implicit offset is fine, if it is correct. I saw the same issue Youngmin outlines here on gs101 SoC. The current implicit offset calculation sometimes results in programming an incorrect register (if you're lucky). I also saw Serror if it turns out to be a nonexistent register (which kills the system). As Youngmin mentioned "Exynos9-era" in the commit description, I suspect (but can't say for sure) that all the SoCs mentioned in this patch are the same as gs101, and the implicit offset calculation is incorrect. IIRC this code path is only triggered on suspend/resume paths which likely explains why nobody noticed the bug previously. IMO, resending this patch would be good, as it should bring these SoCs one small step closer to functional suspend/resume. It's probably also worthwhile splitting this into separate commits, and adding Fixes tags. Thanks, Peter. ^ permalink raw reply [flat|nested] 19+ messages in thread
[parent not found: <CGME20251202093028epcas2p1955176332d21ce4cadf7ed8894c5c1fa@epcas2p1.samsung.com>]
* [PATCH v3 4/5] pinctrl: samsung: fold GS101 pin-bank macros into EXYNOS9_* [not found] ` <CGME20251202093028epcas2p1955176332d21ce4cadf7ed8894c5c1fa@epcas2p1.samsung.com> @ 2025-12-02 9:36 ` Youngmin Nam 2025-12-17 4:43 ` Alim Akhtar 0 siblings, 1 reply; 19+ messages in thread From: Youngmin Nam @ 2025-12-02 9:36 UTC (permalink / raw) To: krzk, s.nawrocki, alim.akhtar, linus.walleij, peter.griffin, semen.protsenko, ivo.ivanov.ivanov1 Cc: ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel, Youngmin Nam GS101 had dedicated GS101_PIN_BANK_EINT{G,W} helpers, but they are redundant with EXYNOS9_PIN_BANK_EINT{G,W} (same semantics, including the per-bank .eint_fltcon_offset). This change removes the GS101_* macros and switches the GS101 pin-bank tables to the EXYNOS9_* helpers with exynos9_bank_type_{alive,off}. While here, update the struct comment to note FLTCON is Exynos9-specific (not 'GS101-specific'). One macro family for all Exynos9-era SoCs (incl. GS101) reduces copy-paste drift and keeps the FLTCON handling consistent. There is no functional change. Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Sam Protsenko <semen.protsenko@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> (tested on Pixel6/gs101) --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 98 +++++++++---------- drivers/pinctrl/samsung/pinctrl-exynos.h | 22 ----- drivers/pinctrl/samsung/pinctrl-samsung.h | 4 +- 3 files changed, 51 insertions(+), 73 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 92ae1bc80f9c..f473a576f58c 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -1842,83 +1842,83 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { /* pin banks of gs101 pin-controller (ALIVE) */ static const struct samsung_pin_bank_data gs101_pin_alive[] = { - GS101_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00, 0x00), - GS101_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04, 0x08), - GS101_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08, 0x10), - GS101_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c, 0x18), - GS101_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10, 0x1c), - GS101_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14, 0x20), - GS101_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18, 0x28), - GS101_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c, 0x30), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x0, "gpa0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 7, 0x20, "gpa1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 5, 0x40, "gpa2", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 4, 0x60, "gpa3", 0x0c, 0x18), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 4, 0x80, "gpa4", 0x10, 0x1c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 7, 0xa0, "gpa5", 0x14, 0x20), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0xc0, "gpa9", 0x18, 0x28), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0xe0, "gpa10", 0x1c, 0x30), }; /* pin banks of gs101 pin-controller (FAR_ALIVE) */ static const struct samsung_pin_bank_data gs101_pin_far_alive[] = { - GS101_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00, 0x00), - GS101_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04, 0x08), - GS101_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08, 0x0c), - GS101_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c, 0x14), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x0, "gpa6", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 4, 0x20, "gpa7", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 8, 0x40, "gpa8", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 2, 0x60, "gpa11", 0x0c, 0x14), }; /* pin banks of gs101 pin-controller (GSACORE) */ static const struct samsung_pin_bank_data gs101_pin_gsacore[] = { - GS101_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00, 0x00), - GS101_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04, 0x04), - GS101_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x0, "gps0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x20, "gps1", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 3, 0x40, "gps2", 0x08, 0x0c), }; /* pin banks of gs101 pin-controller (GSACTRL) */ static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = { - GS101_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(exynos9_bank_type_alive, 6, 0x0, "gps3", 0x00, 0x00), }; /* pin banks of gs101 pin-controller (PERIC0) */ static const struct samsung_pin_bank_data gs101_pin_peric0[] = { - GS101_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00, 0x00), - GS101_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04, 0x08), - GS101_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08, 0x0c), - GS101_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c, 0x10), - GS101_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10, 0x14), - GS101_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14, 0x18), - GS101_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18, 0x1c), - GS101_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c, 0x20), - GS101_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20, 0x24), - GS101_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24, 0x28), - GS101_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28, 0x2c), - GS101_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c, 0x30), - GS101_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30, 0x34), - GS101_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34, 0x38), - GS101_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38, 0x3c), - GS101_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c, 0x40), - GS101_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40, 0x44), - GS101_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44, 0x48), - GS101_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48, 0x4c), - GS101_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c, 0x50), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0x0, "gpp0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x20, "gpp1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x40, "gpp2", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x60, "gpp3", 0x0c, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x80, "gpp4", 0x10, 0x14), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0xa0, "gpp5", 0x14, 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0xc0, "gpp6", 0x18, 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0xe0, "gpp7", 0x1c, 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x100, "gpp8", 0x20, 0x24), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x120, "gpp9", 0x24, 0x28), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x140, "gpp10", 0x28, 0x2c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x160, "gpp11", 0x2c, 0x30), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x180, "gpp12", 0x30, 0x34), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x1a0, "gpp13", 0x34, 0x38), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x1c0, "gpp14", 0x38, 0x3c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x1e0, "gpp15", 0x3c, 0x40), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x200, "gpp16", 0x40, 0x44), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x220, "gpp17", 0x44, 0x48), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x240, "gpp18", 0x48, 0x4c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x260, "gpp19", 0x4c, 0x50), }; /* pin banks of gs101 pin-controller (PERIC1) */ static const struct samsung_pin_bank_data gs101_pin_peric1[] = { - GS101_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00, 0x00), - GS101_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04, 0x08), - GS101_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08, 0x0c), - GS101_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c, 0x10), - GS101_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10, 0x18), - GS101_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14, 0x1c), - GS101_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18, 0x20), - GS101_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c, 0x28), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x0, "gpp20", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x20, "gpp21", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x40, "gpp22", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 8, 0x60, "gpp23", 0x0c, 0x10), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0x80, "gpp24", 0x10, 0x18), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0xa0, "gpp25", 0x14, 0x1c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 5, 0xc0, "gpp26", 0x18, 0x20), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 4, 0xe0, "gpp27", 0x1c, 0x28), }; /* pin banks of gs101 pin-controller (HSI1) */ static const struct samsung_pin_bank_data gs101_pin_hsi1[] = { - GS101_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00, 0x00), - GS101_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x0, "gph0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 7, 0x20, "gph1", 0x04, 0x08), }; /* pin banks of gs101 pin-controller (HSI2) */ static const struct samsung_pin_bank_data gs101_pin_hsi2[] = { - GS101_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00, 0x00), - GS101_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04, 0x08), - GS101_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x0, "gph2", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 2, 0x20, "gph3", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(exynos9_bank_type_off, 6, 0x40, "gph4", 0x08, 0x0c), }; static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index 7ebfdcaf2781..24f85ff5ed30 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -187,28 +187,6 @@ .name = id \ } -#define GS101_PIN_BANK_EINTG(pins, reg, id, offs, fltcon_offs) \ - { \ - .type = &exynos9_bank_type_off, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_GPIO, \ - .eint_offset = offs, \ - .eint_fltcon_offset = fltcon_offs, \ - .name = id \ - } - -#define GS101_PIN_BANK_EINTW(pins, reg, id, offs, fltcon_offs) \ - { \ - .type = &exynos9_bank_type_alive, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_WKUP, \ - .eint_offset = offs, \ - .eint_fltcon_offset = fltcon_offs, \ - .name = id \ - } - #define ARTPEC_PIN_BANK_EINTG(pins, reg, id, offs) \ { \ .type = &artpec_bank_type_off, \ diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 0f7b2ea98158..0209c2d28858 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -145,7 +145,7 @@ struct samsung_pin_bank_type { * @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank. * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank. * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank. - * @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset. + * @eint_fltcon_offset: Exynos9 SoC-specific EINT filter config register offset. * @name: name to be prefixed for each pin in this pin bank. */ struct samsung_pin_bank_data { @@ -180,7 +180,7 @@ struct samsung_pin_bank_data { * @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank. * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank. * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank. - * @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset. + * @eint_fltcon_offset: Exynos9 SoC-specific EINT filter config register offset. * @name: name to be prefixed for each pin in this pin bank. * @id: id of the bank, propagated to the pin range. * @pin_base: starting pin number of the bank. -- 2.52.0 ^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH v3 4/5] pinctrl: samsung: fold GS101 pin-bank macros into EXYNOS9_* 2025-12-02 9:36 ` [PATCH v3 4/5] pinctrl: samsung: fold GS101 pin-bank macros into EXYNOS9_* Youngmin Nam @ 2025-12-17 4:43 ` Alim Akhtar 0 siblings, 0 replies; 19+ messages in thread From: Alim Akhtar @ 2025-12-17 4:43 UTC (permalink / raw) To: 'Youngmin Nam', krzk, s.nawrocki, linus.walleij, peter.griffin, semen.protsenko, ivo.ivanov.ivanov1 Cc: ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel Hi Youngmin > -----Original Message----- > From: Youngmin Nam <youngmin.nam@samsung.com> > Sent: Tuesday, December 2, 2025 3:06 PM > To: krzk@kernel.org; s.nawrocki@samsung.com; alim.akhtar@samsung.com; > linus.walleij@linaro.org; peter.griffin@linaro.org; > semen.protsenko@linaro.org; ivo.ivanov.ivanov1@gmail.com > Cc: ryu.real@samsung.com; d7271.choe@samsung.com; > shin.son@samsung.com; jaewon02.kim@samsung.com; linux-arm- > kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux- > gpio@vger.kernel.org; linux-kernel@vger.kernel.org; Youngmin Nam > <youngmin.nam@samsung.com> > Subject: [PATCH v3 4/5] pinctrl: samsung: fold GS101 pin-bank macros into > EXYNOS9_* > > GS101 had dedicated GS101_PIN_BANK_EINT{G,W} helpers, but they are > redundant with EXYNOS9_PIN_BANK_EINT{G,W} (same semantics, including > the per-bank .eint_fltcon_offset). > This change removes the GS101_* macros and switches the GS101 pin-bank > tables to the EXYNOS9_* helpers with exynos9_bank_type_{alive,off}. > While here, update the struct comment to note FLTCON is Exynos9-specific > (not 'GS101-specific'). > > One macro family for all Exynos9-era SoCs (incl. GS101) reduces copy-paste > drift and keeps the FLTCON handling consistent. > There is no functional change. > > Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Reviewed-by: Peter Griffin <peter.griffin@linaro.org> > Tested-by: Sam Protsenko <semen.protsenko@linaro.org> > Tested-by: Peter Griffin <peter.griffin@linaro.org> (tested on Pixel6/gs101) > --- Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Tested this series on Exynosautov920 sadk board Tested-by: Alim Akhtar <alim.akhtar@samsung.com> ^ permalink raw reply [flat|nested] 19+ messages in thread
[parent not found: <CGME20251202093029epcas2p19224bab81f8ed2b9f63613fdd010ab57@epcas2p1.samsung.com>]
* [PATCH v3 5/5] pinctrl: samsung: rename gs101_pinctrl_* to exynos9_pinctrl_* [not found] ` <CGME20251202093029epcas2p19224bab81f8ed2b9f63613fdd010ab57@epcas2p1.samsung.com> @ 2025-12-02 9:36 ` Youngmin Nam 2025-12-17 4:53 ` Alim Akhtar 2025-12-28 11:43 ` Krzysztof Kozlowski 0 siblings, 2 replies; 19+ messages in thread From: Youngmin Nam @ 2025-12-02 9:36 UTC (permalink / raw) To: krzk, s.nawrocki, alim.akhtar, linus.walleij, peter.griffin, semen.protsenko, ivo.ivanov.ivanov1 Cc: ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel, Youngmin Nam The suspend/resume helpers named gs101_pinctrl_{suspend,resume} are not GS101-specific. They implement the generic save/restore sequence used by Exynos9-style controllers that have EINT filter configuration (eint_fltcon) to preserve. Rename them to exynos9_pinctrl_{suspend,resume} and update all users: - exynos2200, exynos9810, exynos8895, exynos7885, exynos7870, exynosautov9, fsd, and gs101 controller tables - prototypes in pinctrl-exynos.h - definitions in pinctrl-exynos.c This aligns naming with the earlier macro/doc cleanups (e.g. using EXYNOS9_PIN_BANK_* and describing eint_fltcon as Exynos9-specific) and makes the helpers clearly reusable by other Exynos9-like SoCs. Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> (tested on Pixel6/gs101) --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 176 +++++++++--------- drivers/pinctrl/samsung/pinctrl-exynos.c | 4 +- drivers/pinctrl/samsung/pinctrl-exynos.h | 4 +- 3 files changed, 92 insertions(+), 92 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index f473a576f58c..3839256ebf80 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -195,16 +195,16 @@ static const struct samsung_pin_ctrl exynos2200_pin_ctrl[] = { .nr_banks = ARRAY_SIZE(exynos2200_pin_banks0), .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 1 CMGP data */ .pin_banks = exynos2200_pin_banks1, .nr_banks = ARRAY_SIZE(exynos2200_pin_banks1), .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 2 HSI1 data */ .pin_banks = exynos2200_pin_banks2, @@ -214,36 +214,36 @@ static const struct samsung_pin_ctrl exynos2200_pin_ctrl[] = { .pin_banks = exynos2200_pin_banks3, .nr_banks = ARRAY_SIZE(exynos2200_pin_banks3), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 4 HSI1UFS data */ .pin_banks = exynos2200_pin_banks4, .nr_banks = ARRAY_SIZE(exynos2200_pin_banks4), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 5 PERIC0 data */ .pin_banks = exynos2200_pin_banks5, .nr_banks = ARRAY_SIZE(exynos2200_pin_banks5), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 6 PERIC1 data */ .pin_banks = exynos2200_pin_banks6, .nr_banks = ARRAY_SIZE(exynos2200_pin_banks6), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 7 PERIC2 data */ .pin_banks = exynos2200_pin_banks7, .nr_banks = ARRAY_SIZE(exynos2200_pin_banks7), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 8 VTS data */ .pin_banks = exynos2200_pin_banks8, @@ -710,8 +710,8 @@ static const struct samsung_pin_ctrl exynos7870_pin_ctrl[] __initconst = { .pin_banks = exynos7870_pin_banks0, .nr_banks = ARRAY_SIZE(exynos7870_pin_banks0), .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 1 DISPAUD data */ .pin_banks = exynos7870_pin_banks1, @@ -721,43 +721,43 @@ static const struct samsung_pin_ctrl exynos7870_pin_ctrl[] __initconst = { .pin_banks = exynos7870_pin_banks2, .nr_banks = ARRAY_SIZE(exynos7870_pin_banks2), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 3 FSYS data */ .pin_banks = exynos7870_pin_banks3, .nr_banks = ARRAY_SIZE(exynos7870_pin_banks3), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 4 MIF data */ .pin_banks = exynos7870_pin_banks4, .nr_banks = ARRAY_SIZE(exynos7870_pin_banks4), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 5 NFC data */ .pin_banks = exynos7870_pin_banks5, .nr_banks = ARRAY_SIZE(exynos7870_pin_banks5), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 6 TOP data */ .pin_banks = exynos7870_pin_banks6, .nr_banks = ARRAY_SIZE(exynos7870_pin_banks6), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 7 TOUCH data */ .pin_banks = exynos7870_pin_banks7, .nr_banks = ARRAY_SIZE(exynos7870_pin_banks7), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, }; @@ -819,8 +819,8 @@ static const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = { .nr_banks = ARRAY_SIZE(exynos7885_pin_banks0), .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 1 DISPAUD data */ .pin_banks = exynos7885_pin_banks1, @@ -830,15 +830,15 @@ static const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = { .pin_banks = exynos7885_pin_banks2, .nr_banks = ARRAY_SIZE(exynos7885_pin_banks2), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 3 TOP data */ .pin_banks = exynos7885_pin_banks3, .nr_banks = ARRAY_SIZE(exynos7885_pin_banks3), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, }; @@ -1175,8 +1175,8 @@ static const struct samsung_pin_ctrl exynos9810_pin_ctrl[] __initconst = { .nr_banks = ARRAY_SIZE(exynos9810_pin_banks0), .eint_wkup_init = exynos_eint_wkup_init, .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 1 AUD data */ .pin_banks = exynos9810_pin_banks1, @@ -1186,44 +1186,44 @@ static const struct samsung_pin_ctrl exynos9810_pin_ctrl[] __initconst = { .pin_banks = exynos9810_pin_banks2, .nr_banks = ARRAY_SIZE(exynos9810_pin_banks2), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 3 CMGP data */ .pin_banks = exynos9810_pin_banks3, .nr_banks = ARRAY_SIZE(exynos9810_pin_banks3), .eint_wkup_init = exynos_eint_wkup_init, .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 4 FSYS0 data */ .pin_banks = exynos9810_pin_banks4, .nr_banks = ARRAY_SIZE(exynos9810_pin_banks4), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 5 FSYS1 data */ .pin_banks = exynos9810_pin_banks5, .nr_banks = ARRAY_SIZE(exynos9810_pin_banks5), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 6 PERIC0 data */ .pin_banks = exynos9810_pin_banks6, .nr_banks = ARRAY_SIZE(exynos9810_pin_banks6), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 7 PERIC1 data */ .pin_banks = exynos9810_pin_banks7, .nr_banks = ARRAY_SIZE(exynos9810_pin_banks7), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 8 VTS data */ .pin_banks = exynos9810_pin_banks8, @@ -1295,8 +1295,8 @@ static const struct samsung_pin_ctrl exynosautov9_pin_ctrl[] __initconst = { .pin_banks = exynosautov9_pin_banks0, .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks0), .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 1 AUD data */ .pin_banks = exynosautov9_pin_banks1, @@ -1306,36 +1306,36 @@ static const struct samsung_pin_ctrl exynosautov9_pin_ctrl[] __initconst = { .pin_banks = exynosautov9_pin_banks2, .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks2), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 3 FSYS1 data */ .pin_banks = exynosautov9_pin_banks3, .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks3), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 4 FSYS2 data */ .pin_banks = exynosautov9_pin_banks4, .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks4), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 5 PERIC0 data */ .pin_banks = exynosautov9_pin_banks5, .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks5), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 6 PERIC1 data */ .pin_banks = exynosautov9_pin_banks6, .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks6), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, }; @@ -1715,8 +1715,8 @@ static const struct samsung_pin_ctrl exynos8895_pin_ctrl[] __initconst = { .nr_banks = ARRAY_SIZE(exynos8895_pin_banks0), .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 1 ABOX data */ .pin_banks = exynos8895_pin_banks1, @@ -1731,36 +1731,36 @@ static const struct samsung_pin_ctrl exynos8895_pin_ctrl[] __initconst = { .pin_banks = exynos8895_pin_banks3, .nr_banks = ARRAY_SIZE(exynos8895_pin_banks3), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 4 FSYS1 data */ .pin_banks = exynos8895_pin_banks4, .nr_banks = ARRAY_SIZE(exynos8895_pin_banks4), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 5 BUSC data */ .pin_banks = exynos8895_pin_banks5, .nr_banks = ARRAY_SIZE(exynos8895_pin_banks5), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 6 PERIC0 data */ .pin_banks = exynos8895_pin_banks6, .nr_banks = ARRAY_SIZE(exynos8895_pin_banks6), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 7 PERIC1 data */ .pin_banks = exynos8895_pin_banks7, .nr_banks = ARRAY_SIZE(exynos8895_pin_banks7), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, }; @@ -1819,15 +1819,15 @@ static const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = { .pin_banks = fsd_pin_banks0, .nr_banks = ARRAY_SIZE(fsd_pin_banks0), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 1 PERIC data */ .pin_banks = fsd_pin_banks1, .nr_banks = ARRAY_SIZE(fsd_pin_banks1), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin-controller instance 2 PMU data */ .pin_banks = fsd_pin_banks2, @@ -1927,16 +1927,16 @@ static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { .pin_banks = gs101_pin_alive, .nr_banks = ARRAY_SIZE(gs101_pin_alive), .eint_wkup_init = exynos_eint_wkup_init, - .suspend = gs101_pinctrl_suspend, - .resume = gs101_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, .retention_data = &no_retention_data, }, { /* pin banks of gs101 pin-controller (FAR_ALIVE) */ .pin_banks = gs101_pin_far_alive, .nr_banks = ARRAY_SIZE(gs101_pin_far_alive), .eint_wkup_init = exynos_eint_wkup_init, - .suspend = gs101_pinctrl_suspend, - .resume = gs101_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, .retention_data = &no_retention_data, }, { /* pin banks of gs101 pin-controller (GSACORE) */ @@ -1951,29 +1951,29 @@ static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { .pin_banks = gs101_pin_peric0, .nr_banks = ARRAY_SIZE(gs101_pin_peric0), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = gs101_pinctrl_suspend, - .resume = gs101_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (PERIC1) */ .pin_banks = gs101_pin_peric1, .nr_banks = ARRAY_SIZE(gs101_pin_peric1), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = gs101_pinctrl_suspend, - .resume = gs101_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (HSI1) */ .pin_banks = gs101_pin_hsi1, .nr_banks = ARRAY_SIZE(gs101_pin_hsi1), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = gs101_pinctrl_suspend, - .resume = gs101_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (HSI2) */ .pin_banks = gs101_pin_hsi2, .nr_banks = ARRAY_SIZE(gs101_pin_hsi2), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = gs101_pinctrl_suspend, - .resume = gs101_pinctrl_resume, + .suspend = exynos9_pinctrl_suspend, + .resume = exynos9_pinctrl_resume, }, }; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 81fe0b08a9af..a6dd0fa59230 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -906,7 +906,7 @@ void exynos_pinctrl_suspend(struct samsung_pin_bank *bank) } } -void gs101_pinctrl_suspend(struct samsung_pin_bank *bank) +void exynos9_pinctrl_suspend(struct samsung_pin_bank *bank) { struct exynos_eint_gpio_save *save = bank->soc_priv; const void __iomem *regs = bank->eint_base; @@ -961,7 +961,7 @@ void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank) } } -void gs101_pinctrl_resume(struct samsung_pin_bank *bank) +void exynos9_pinctrl_resume(struct samsung_pin_bank *bank) { struct exynos_eint_gpio_save *save = bank->soc_priv; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index 24f85ff5ed30..612d9a7e8577 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -225,8 +225,8 @@ void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank); void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank); void exynos_pinctrl_suspend(struct samsung_pin_bank *bank); void exynos_pinctrl_resume(struct samsung_pin_bank *bank); -void gs101_pinctrl_suspend(struct samsung_pin_bank *bank); -void gs101_pinctrl_resume(struct samsung_pin_bank *bank); +void exynos9_pinctrl_suspend(struct samsung_pin_bank *bank); +void exynos9_pinctrl_resume(struct samsung_pin_bank *bank); struct samsung_retention_ctrl * exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, const struct samsung_retention_data *data); -- 2.52.0 ^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH v3 5/5] pinctrl: samsung: rename gs101_pinctrl_* to exynos9_pinctrl_* 2025-12-02 9:36 ` [PATCH v3 5/5] pinctrl: samsung: rename gs101_pinctrl_* to exynos9_pinctrl_* Youngmin Nam @ 2025-12-17 4:53 ` Alim Akhtar 2025-12-28 11:43 ` Krzysztof Kozlowski 1 sibling, 0 replies; 19+ messages in thread From: Alim Akhtar @ 2025-12-17 4:53 UTC (permalink / raw) To: 'Youngmin Nam', krzk, s.nawrocki, linus.walleij, peter.griffin, semen.protsenko, ivo.ivanov.ivanov1 Cc: ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel Hello Youngmin > -----Original Message----- > From: Youngmin Nam <youngmin.nam@samsung.com> > Sent: Tuesday, December 2, 2025 3:06 PM > To: krzk@kernel.org; s.nawrocki@samsung.com; alim.akhtar@samsung.com; > linus.walleij@linaro.org; peter.griffin@linaro.org; > semen.protsenko@linaro.org; ivo.ivanov.ivanov1@gmail.com > Cc: ryu.real@samsung.com; d7271.choe@samsung.com; > shin.son@samsung.com; jaewon02.kim@samsung.com; linux-arm- > kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux- > gpio@vger.kernel.org; linux-kernel@vger.kernel.org; Youngmin Nam > <youngmin.nam@samsung.com> > Subject: [PATCH v3 5/5] pinctrl: samsung: rename gs101_pinctrl_* to > exynos9_pinctrl_* > > The suspend/resume helpers named gs101_pinctrl_{suspend,resume} are > not GS101-specific. They implement the generic save/restore sequence used > by Exynos9-style controllers that have EINT filter configuration > (eint_fltcon) to preserve. > > Rename them to exynos9_pinctrl_{suspend,resume} and update all users: > - exynos2200, exynos9810, exynos8895, exynos7885, exynos7870, > exynosautov9, fsd, and gs101 controller tables > - prototypes in pinctrl-exynos.h > - definitions in pinctrl-exynos.c > > This aligns naming with the earlier macro/doc cleanups (e.g. using > EXYNOS9_PIN_BANK_* and describing eint_fltcon as Exynos9-specific) and > makes the helpers clearly reusable by other Exynos9-like SoCs. > > Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > Reviewed-by: Peter Griffin <peter.griffin@linaro.org> > Tested-by: Peter Griffin <peter.griffin@linaro.org> (tested on Pixel6/gs101) > --- Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Tested this series on Exynosautov920 sadk Tested-by: Alim Akhtar <alim.akhtar@samsung.com> ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 5/5] pinctrl: samsung: rename gs101_pinctrl_* to exynos9_pinctrl_* 2025-12-02 9:36 ` [PATCH v3 5/5] pinctrl: samsung: rename gs101_pinctrl_* to exynos9_pinctrl_* Youngmin Nam 2025-12-17 4:53 ` Alim Akhtar @ 2025-12-28 11:43 ` Krzysztof Kozlowski 1 sibling, 0 replies; 19+ messages in thread From: Krzysztof Kozlowski @ 2025-12-28 11:43 UTC (permalink / raw) To: Youngmin Nam, s.nawrocki, alim.akhtar, linus.walleij, peter.griffin, semen.protsenko, ivo.ivanov.ivanov1 Cc: ryu.real, d7271.choe, shin.son, jaewon02.kim, linux-arm-kernel, linux-samsung-soc, linux-gpio, linux-kernel On 02/12/2025 10:36, Youngmin Nam wrote: > The suspend/resume helpers named gs101_pinctrl_{suspend,resume} are not > GS101-specific. They implement the generic save/restore sequence used by > Exynos9-style controllers that have EINT filter configuration > (eint_fltcon) to preserve. > > Rename them to exynos9_pinctrl_{suspend,resume} and update all users: Why? Exynos9 does not exist, there is no such SoC. All other SoCs can use GS101 naming, just like GS101 could use Exynos-foo. You need to come with a reason why Exynos9 is better than GS101. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2026-07-03 12:15 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <CGME20251202093024epcas2p1567dddf09e3599867e9dc14a9a234d38@epcas2p1.samsung.com>
2025-12-02 9:36 ` [PATCH v3 0/5] pinctrl: samsung: exynos9 cleanups and fixes Youngmin Nam
[not found] ` <CGME20251202093026epcas2p28ddfd32305695df996841fd73b231b6b@epcas2p2.samsung.com>
2025-12-02 9:36 ` [PATCH v3 1/5] pinctrl: samsung: Consolidate pin-bank macros under EXYNOS9_* and pass bank_type explicitly Youngmin Nam
2025-12-17 4:28 ` Alim Akhtar
2025-12-28 11:40 ` Krzysztof Kozlowski
[not found] ` <CGME20251202093027epcas2p24adbd3226dd50b2780baceee6588f3ba@epcas2p2.samsung.com>
2025-12-02 9:36 ` [PATCH v3 2/5] pinctrl: samsung: fix incorrect pin-bank entries on Exynos2200/7885/8890/8895 Youngmin Nam
2025-12-17 4:33 ` Alim Akhtar
2025-12-28 11:37 ` Krzysztof Kozlowski
2026-03-06 21:17 ` Peter Griffin
2026-06-29 9:23 ` Alim Akhtar
2026-07-03 12:15 ` 남영민
[not found] ` <CGME20251202093028epcas2p456b6a2bfebfc76384f706a9962266fcf@epcas2p4.samsung.com>
2025-12-02 9:36 ` [PATCH v3 3/5] pinctrl: samsung: add per-bank FLTCON offset to EXYNOS9_PIN_BANK_* and fix tables Youngmin Nam
2025-12-17 4:46 ` Alim Akhtar
2025-12-28 11:41 ` Krzysztof Kozlowski
2026-03-06 21:55 ` Peter Griffin
[not found] ` <CGME20251202093028epcas2p1955176332d21ce4cadf7ed8894c5c1fa@epcas2p1.samsung.com>
2025-12-02 9:36 ` [PATCH v3 4/5] pinctrl: samsung: fold GS101 pin-bank macros into EXYNOS9_* Youngmin Nam
2025-12-17 4:43 ` Alim Akhtar
[not found] ` <CGME20251202093029epcas2p19224bab81f8ed2b9f63613fdd010ab57@epcas2p1.samsung.com>
2025-12-02 9:36 ` [PATCH v3 5/5] pinctrl: samsung: rename gs101_pinctrl_* to exynos9_pinctrl_* Youngmin Nam
2025-12-17 4:53 ` Alim Akhtar
2025-12-28 11:43 ` Krzysztof Kozlowski
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