* staging: et131x: Move function declarations from et131x.h to et131x.c
@ 2011-10-19 23:00 Mark Einon
2011-10-19 23:00 ` staging: et131x: Move non-register defines " Mark Einon
` (16 more replies)
0 siblings, 17 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:00 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
The function declarations in et131x.h are no longer used now all
functions are in one file. Removed declarations from et131x.h and
added any required forward declarations to et131x.c.
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/et131x.c | 31 ++++++++++++
drivers/staging/et131x/et131x.h | 102 ---------------------------------------
2 files changed, 31 insertions(+), 102 deletions(-)
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index fdf6385..a038a37 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -96,6 +96,37 @@ MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver "
"for the ET1310 by Agere Systems");
+void et131x_error_timer_handler(unsigned long data);
+void et131x_enable_interrupts(struct et131x_adapter *adapter);
+void et131x_disable_interrupts(struct et131x_adapter *adapter);
+void et131x_align_allocated_memory(struct et131x_adapter *adapter,
+ u64 *phys_addr,
+ u64 *offset, u64 mask);
+void et131x_adapter_setup(struct et131x_adapter *adapter);
+void et131x_soft_reset(struct et131x_adapter *adapter);
+void et131x_isr_handler(struct work_struct *work);
+void et1310_setup_device_for_multicast(struct et131x_adapter *adapter);
+void et1310_setup_device_for_unicast(struct et131x_adapter *adapter);
+void et131x_up(struct net_device *netdev);
+void et131x_down(struct net_device *netdev);
+struct net_device *et131x_device_alloc(void);
+void et131x_enable_txrx(struct net_device *netdev);
+void et131x_disable_txrx(struct net_device *netdev);
+int et1310_in_phy_coma(struct et131x_adapter *adapter);
+void et1310_phy_access_mii_bit(struct et131x_adapter *adapter,
+ u16 action,
+ u16 regnum, u16 bitnum, u8 *value);
+int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
+ u8 reg, u16 *value);
+int32_t et131x_mii_write(struct et131x_adapter *adapter,
+ u8 reg, u16 value);
+void et131x_rx_dma_memory_free(struct et131x_adapter *adapter);
+void et131x_rx_dma_disable(struct et131x_adapter *adapter);
+void et131x_rx_dma_enable(struct et131x_adapter *adapter);
+void et131x_reset_recv(struct et131x_adapter *adapter);
+void et131x_init_send(struct et131x_adapter *adapter);
+void et131x_tx_dma_enable(struct et131x_adapter *adapter);
+
/* EEPROM functions */
static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
diff --git a/drivers/staging/et131x/et131x.h b/drivers/staging/et131x/et131x.h
index 0531414..71fd7fe 100644
--- a/drivers/staging/et131x/et131x.h
+++ b/drivers/staging/et131x/et131x.h
@@ -108,105 +108,3 @@
#define INT_MASK_ENABLE 0xfffebf17
#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
-
-/* et131x_eeprom.c */
-int et131x_init_eeprom(struct et131x_adapter *adapter);
-
-/* et131x_initpci.c */
-void et131x_error_timer_handler(unsigned long data);
-void et131x_configure_global_regs(struct et131x_adapter *adapter);
-void et131x_enable_interrupts(struct et131x_adapter *adapter);
-void et131x_disable_interrupts(struct et131x_adapter *adapter);
-void et131x_align_allocated_memory(struct et131x_adapter *adapter,
- u64 *phys_addr,
- u64 *offset, u64 mask);
-
-void et131x_adapter_setup(struct et131x_adapter *adapter);
-int et131x_adapter_memory_alloc(struct et131x_adapter *adapter);
-void et131x_adapter_memory_free(struct et131x_adapter *adapter);
-void et131x_hwaddr_init(struct et131x_adapter *adapter);
-void et131x_soft_reset(struct et131x_adapter *adapter);
-
-/* et131x_isr.c */
-irqreturn_t et131x_isr(int irq, void *dev_id);
-void et131x_isr_handler(struct work_struct *work);
-
-/* et1310_mac.c */
-void et1310_config_mac_regs1(struct et131x_adapter *adapter);
-void et1310_config_mac_regs2(struct et131x_adapter *adapter);
-void et1310_config_rxmac_regs(struct et131x_adapter *adapter);
-void et1310_config_txmac_regs(struct et131x_adapter *adapter);
-void et1310_config_macstat_regs(struct et131x_adapter *adapter);
-void et1310_config_flow_control(struct et131x_adapter *adapter);
-void et1310_update_macstat_host_counters(struct et131x_adapter *adapter);
-void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter);
-void et1310_setup_device_for_multicast(struct et131x_adapter *adapter);
-void et1310_setup_device_for_unicast(struct et131x_adapter *adapter);
-
-/* et131x_netdev.c */
-int et131x_open(struct net_device *netdev);
-int et131x_close(struct net_device *netdev);
-void et131x_up(struct net_device *netdev);
-void et131x_down(struct net_device *netdev);
-struct net_device *et131x_device_alloc(void);
-void et131x_enable_txrx(struct net_device *netdev);
-void et131x_disable_txrx(struct net_device *netdev);
-
-/* et1310_pm.c */
-int et1310_in_phy_coma(struct et131x_adapter *adapter);
-void et1310_enable_phy_coma(struct et131x_adapter *adapter);
-void et1310_disable_phy_coma(struct et131x_adapter *adapter);
-
-/* et1310_phy.c */
-void et1310_phy_power_down(struct et131x_adapter *adapter, bool down);
-void et1310_phy_access_mii_bit(struct et131x_adapter *adapter,
- u16 action,
- u16 regnum, u16 bitnum, u8 *value);
-
-void et131x_xcvr_init(struct et131x_adapter *adapter);
-
-/* static inline function does not work because et131x_adapter is not always
- * defined
- */
-int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
- u8 reg, u16 *value);
-int32_t et131x_mii_read(struct et131x_adapter *adapter,
- u8 reg, u16 *value);
-int32_t et131x_mii_write(struct et131x_adapter *adapter,
- u8 reg, u16 value);
-
-int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg);
-int et131x_mdio_write(struct mii_bus *bus, int phy_addr, int reg, u16 value);
-int et131x_mdio_reset(struct mii_bus *bus);
-
-/* et1310_rx.c */
-int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter);
-void et131x_rx_dma_memory_free(struct et131x_adapter *adapter);
-int et131x_rfd_resources_alloc(struct et131x_adapter *adapter,
- struct rfd *rfd);
-void et131x_rfd_resources_free(struct et131x_adapter *adapter,
- struct rfd *rfd);
-int et131x_init_recv(struct et131x_adapter *adapter);
-
-void et131x_config_rx_dma_regs(struct et131x_adapter *adapter);
-void et131x_set_rx_dma_timer(struct et131x_adapter *adapter);
-void et131x_rx_dma_disable(struct et131x_adapter *adapter);
-void et131x_rx_dma_enable(struct et131x_adapter *adapter);
-
-void et131x_reset_recv(struct et131x_adapter *adapter);
-
-void et131x_handle_recv_interrupt(struct et131x_adapter *adapter);
-
-/* et131x_tx.c */
-int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter);
-void et131x_tx_dma_memory_free(struct et131x_adapter *adapter);
-void et131x_config_tx_dma_regs(struct et131x_adapter *adapter);
-void et131x_init_send(struct et131x_adapter *adapter);
-void et131x_tx_dma_disable(struct et131x_adapter *adapter);
-void et131x_tx_dma_enable(struct et131x_adapter *adapter);
-void et131x_handle_send_interrupt(struct et131x_adapter *adapter);
-void et131x_free_busy_send_packets(struct et131x_adapter *adapter);
-int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev);
-
-/* et131x_ethtool.c */
-void et131x_set_ethtool_ops(struct net_device *netdev);
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: Move non-register defines from et131x.h to et131x.c
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
@ 2011-10-19 23:00 ` Mark Einon
2011-10-19 23:00 ` staging: et131x: move et1310_address_map.h contents into et131x.h Mark Einon
` (15 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:00 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
Header file should only have register defines, moved non-register
defines to et131x.c
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/et131x.c | 31 +++++++++++++++++++++++++++++++
drivers/staging/et131x/et131x.h | 33 +--------------------------------
2 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index a038a37..cad271b 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -96,6 +96,37 @@ MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver "
"for the ET1310 by Agere Systems");
+/* EEPROM defines */
+#define MAX_NUM_REGISTER_POLLS 1000
+#define MAX_NUM_WRITE_RETRIES 2
+
+/* MAC defines */
+#define COUNTER_WRAP_16_BIT 0x10000
+#define COUNTER_WRAP_12_BIT 0x1000
+
+/* PCI defines */
+#define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
+#define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
+
+/* ISR defines */
+/*
+ * For interrupts, normal running is:
+ * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
+ * watchdog_interrupt & txdma_xfer_done
+ *
+ * In both cases, when flow control is enabled for either Tx or bi-direction,
+ * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
+ * buffer rings are running low.
+ */
+#define INT_MASK_DISABLE 0xffffffff
+
+/* NOTE: Masking out MAC_STAT Interrupt for now...
+ * #define INT_MASK_ENABLE 0xfff6bf17
+ * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
+ */
+#define INT_MASK_ENABLE 0xfffebf17
+#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
+
void et131x_error_timer_handler(unsigned long data);
void et131x_enable_interrupts(struct et131x_adapter *adapter);
void et131x_disable_interrupts(struct et131x_adapter *adapter);
diff --git a/drivers/staging/et131x/et131x.h b/drivers/staging/et131x/et131x.h
index 71fd7fe..115d307 100644
--- a/drivers/staging/et131x/et131x.h
+++ b/drivers/staging/et131x/et131x.h
@@ -49,7 +49,7 @@
#define DRIVER_NAME "et131x"
#define DRIVER_VERSION "v2.0"
-/* EEPROM defines */
+/* EEPROM registers */
/* LBCIF Register Groups (addressed via 32-bit offsets) */
#define LBCIF_DWORD0_GROUP 0xAC
@@ -77,34 +77,3 @@
#define LBCIF_STATUS_CHECKSUM_ERROR 0x40
#define LBCIF_STATUS_EEPROM_PRESENT 0x80
-/* Miscellaneous Constraints */
-#define MAX_NUM_REGISTER_POLLS 1000
-#define MAX_NUM_WRITE_RETRIES 2
-
-/* MAC defines */
-#define COUNTER_WRAP_16_BIT 0x10000
-#define COUNTER_WRAP_12_BIT 0x1000
-
-/* PCI defines */
-#define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
-#define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
-
-/* ISR defines */
-/*
- * For interrupts, normal running is:
- * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
- * watchdog_interrupt & txdma_xfer_done
- *
- * In both cases, when flow control is enabled for either Tx or bi-direction,
- * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
- * buffer rings are running low.
- */
-#define INT_MASK_DISABLE 0xffffffff
-
-/* NOTE: Masking out MAC_STAT Interrupt for now...
- * #define INT_MASK_ENABLE 0xfff6bf17
- * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
- */
-#define INT_MASK_ENABLE 0xfffebf17
-#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
-
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: move et1310_address_map.h contents into et131x.h
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
2011-10-19 23:00 ` staging: et131x: Move non-register defines " Mark Einon
@ 2011-10-19 23:00 ` Mark Einon
2011-10-19 23:00 ` staging: et131x: move et1310_phy.h " Mark Einon
` (14 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:00 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
Move et1310_address_map.h register defines into et131x.h and delete
et1310_address_map.h
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/et1310_address_map.h | 1436 ---------------------------
drivers/staging/et131x/et1310_phy.h | 2 -
drivers/staging/et131x/et1310_rx.h | 2 -
drivers/staging/et131x/et131x.c | 1 -
drivers/staging/et131x/et131x.h | 1370 +++++++++++++++++++++++++
drivers/staging/et131x/et131x_adapter.h | 1 -
6 files changed, 1370 insertions(+), 1442 deletions(-)
delete mode 100644 drivers/staging/et131x/et1310_address_map.h
diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h
deleted file mode 100644
index b502ce3..0000000
--- a/drivers/staging/et131x/et1310_address_map.h
+++ /dev/null
@@ -1,1436 +0,0 @@
-/*
- * Agere Systems Inc.
- * 10/100/1000 Base-T Ethernet Driver for the ET1310 and ET131x series MACs
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- * http://www.agere.com
- *
- * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
- *
- *------------------------------------------------------------------------------
- *
- * et1310_address_map.h - Contains the register mapping for the ET1310
- *
- *------------------------------------------------------------------------------
- *
- * SOFTWARE LICENSE
- *
- * This software is provided subject to the following terms and conditions,
- * which you should read carefully before using the software. Using this
- * software indicates your acceptance of these terms and conditions. If you do
- * not agree with these terms and conditions, do not use the software.
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- *
- * Redistribution and use in source or binary forms, with or without
- * modifications, are permitted provided that the following conditions are met:
- *
- * . Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following Disclaimer as comments in the code as
- * well as in the documentation and/or other materials provided with the
- * distribution.
- *
- * . Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following Disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * . Neither the name of Agere Systems Inc. nor the names of the contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * Disclaimer
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
- * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
- * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGE.
- *
- */
-
-#ifndef _ET1310_ADDRESS_MAP_H_
-#define _ET1310_ADDRESS_MAP_H_
-
-
-/* START OF GLOBAL REGISTER ADDRESS MAP */
-
-/*
- * 10bit registers
- *
- * Tx queue start address reg in global address map at address 0x0000
- * tx queue end address reg in global address map at address 0x0004
- * rx queue start address reg in global address map at address 0x0008
- * rx queue end address reg in global address map at address 0x000C
- */
-
-/*
- * structure for power management control status reg in global address map
- * located at address 0x0010
- * jagcore_rx_rdy bit 9
- * jagcore_tx_rdy bit 8
- * phy_lped_en bit 7
- * phy_sw_coma bit 6
- * rxclk_gate bit 5
- * txclk_gate bit 4
- * sysclk_gate bit 3
- * jagcore_rx_en bit 2
- * jagcore_tx_en bit 1
- * gigephy_en bit 0
- */
-
-#define ET_PM_PHY_SW_COMA 0x40
-#define ET_PMCSR_INIT 0x38
-
-/*
- * Interrupt status reg at address 0x0018
- */
-
-#define ET_INTR_TXDMA_ISR 0x00000008
-#define ET_INTR_TXDMA_ERR 0x00000010
-#define ET_INTR_RXDMA_XFR_DONE 0x00000020
-#define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
-#define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
-#define ET_INTR_RXDMA_STAT_LOW 0x00000100
-#define ET_INTR_RXDMA_ERR 0x00000200
-#define ET_INTR_WATCHDOG 0x00004000
-#define ET_INTR_WOL 0x00008000
-#define ET_INTR_PHY 0x00010000
-#define ET_INTR_TXMAC 0x00020000
-#define ET_INTR_RXMAC 0x00040000
-#define ET_INTR_MAC_STAT 0x00080000
-#define ET_INTR_SLV_TIMEOUT 0x00100000
-
-/*
- * Interrupt mask register at address 0x001C
- * Interrupt alias clear mask reg at address 0x0020
- * Interrupt status alias reg at address 0x0024
- *
- * Same masks as above
- */
-
-/*
- * Software reset reg at address 0x0028
- * 0: txdma_sw_reset
- * 1: rxdma_sw_reset
- * 2: txmac_sw_reset
- * 3: rxmac_sw_reset
- * 4: mac_sw_reset
- * 5: mac_stat_sw_reset
- * 6: mmc_sw_reset
- *31: selfclr_disable
- */
-
-/*
- * SLV Timer reg at address 0x002C (low 24 bits)
- */
-
-/*
- * MSI Configuration reg at address 0x0030
- */
-
-#define ET_MSI_VECTOR 0x0000001F
-#define ET_MSI_TC 0x00070000
-
-/*
- * Loopback reg located at address 0x0034
- */
-
-#define ET_LOOP_MAC 0x00000001
-#define ET_LOOP_DMA 0x00000002
-
-/*
- * GLOBAL Module of JAGCore Address Mapping
- * Located at address 0x0000
- */
-struct global_regs { /* Location: */
- u32 txq_start_addr; /* 0x0000 */
- u32 txq_end_addr; /* 0x0004 */
- u32 rxq_start_addr; /* 0x0008 */
- u32 rxq_end_addr; /* 0x000C */
- u32 pm_csr; /* 0x0010 */
- u32 unused; /* 0x0014 */
- u32 int_status; /* 0x0018 */
- u32 int_mask; /* 0x001C */
- u32 int_alias_clr_en; /* 0x0020 */
- u32 int_status_alias; /* 0x0024 */
- u32 sw_reset; /* 0x0028 */
- u32 slv_timer; /* 0x002C */
- u32 msi_config; /* 0x0030 */
- u32 loopback; /* 0x0034 */
- u32 watchdog_timer; /* 0x0038 */
-};
-
-
-/* START OF TXDMA REGISTER ADDRESS MAP */
-
-/*
- * txdma control status reg at address 0x1000
- */
-
-#define ET_TXDMA_CSR_HALT 0x00000001
-#define ET_TXDMA_DROP_TLP 0x00000002
-#define ET_TXDMA_CACHE_THRS 0x000000F0
-#define ET_TXDMA_CACHE_SHIFT 4
-#define ET_TXDMA_SNGL_EPKT 0x00000100
-#define ET_TXDMA_CLASS 0x00001E00
-
-/*
- * structure for txdma packet ring base address hi reg in txdma address map
- * located at address 0x1004
- * Defined earlier (u32)
- */
-
-/*
- * structure for txdma packet ring base address low reg in txdma address map
- * located at address 0x1008
- * Defined earlier (u32)
- */
-
-/*
- * structure for txdma packet ring number of descriptor reg in txdma address
- * map. Located at address 0x100C
- *
- * 31-10: unused
- * 9-0: pr ndes
- */
-
-#define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */
-#define ET_DMA12_WRAP 0x1000
-#define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */
-#define ET_DMA10_WRAP 0x0400
-#define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */
-#define ET_DMA4_WRAP 0x0010
-
-#define INDEX12(x) ((x) & ET_DMA12_MASK)
-#define INDEX10(x) ((x) & ET_DMA10_MASK)
-#define INDEX4(x) ((x) & ET_DMA4_MASK)
-
-extern inline void add_10bit(u32 *v, int n)
-{
- *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
-}
-
-extern inline void add_12bit(u32 *v, int n)
-{
- *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
-}
-
-/*
- * 10bit DMA with wrap
- * txdma tx queue write address reg in txdma address map at 0x1010
- * txdma tx queue write address external reg in txdma address map at 0x1014
- * txdma tx queue read address reg in txdma address map at 0x1018
- *
- * u32
- * txdma status writeback address hi reg in txdma address map at0x101C
- * txdma status writeback address lo reg in txdma address map at 0x1020
- *
- * 10bit DMA with wrap
- * txdma service request reg in txdma address map at 0x1024
- * structure for txdma service complete reg in txdma address map at 0x1028
- *
- * 4bit DMA with wrap
- * txdma tx descriptor cache read index reg in txdma address map at 0x102C
- * txdma tx descriptor cache write index reg in txdma address map at 0x1030
- *
- * txdma error reg in txdma address map at address 0x1034
- * 0: PyldResend
- * 1: PyldRewind
- * 4: DescrResend
- * 5: DescrRewind
- * 8: WrbkResend
- * 9: WrbkRewind
- */
-
-/*
- * Tx DMA Module of JAGCore Address Mapping
- * Located at address 0x1000
- */
-struct txdma_regs { /* Location: */
- u32 csr; /* 0x1000 */
- u32 pr_base_hi; /* 0x1004 */
- u32 pr_base_lo; /* 0x1008 */
- u32 pr_num_des; /* 0x100C */
- u32 txq_wr_addr; /* 0x1010 */
- u32 txq_wr_addr_ext; /* 0x1014 */
- u32 txq_rd_addr; /* 0x1018 */
- u32 dma_wb_base_hi; /* 0x101C */
- u32 dma_wb_base_lo; /* 0x1020 */
- u32 service_request; /* 0x1024 */
- u32 service_complete; /* 0x1028 */
- u32 cache_rd_index; /* 0x102C */
- u32 cache_wr_index; /* 0x1030 */
- u32 tx_dma_error; /* 0x1034 */
- u32 desc_abort_cnt; /* 0x1038 */
- u32 payload_abort_cnt; /* 0x103c */
- u32 writeback_abort_cnt; /* 0x1040 */
- u32 desc_timeout_cnt; /* 0x1044 */
- u32 payload_timeout_cnt; /* 0x1048 */
- u32 writeback_timeout_cnt; /* 0x104c */
- u32 desc_error_cnt; /* 0x1050 */
- u32 payload_error_cnt; /* 0x1054 */
- u32 writeback_error_cnt; /* 0x1058 */
- u32 dropped_tlp_cnt; /* 0x105c */
- u32 new_service_complete; /* 0x1060 */
- u32 ethernet_packet_cnt; /* 0x1064 */
-};
-
-/* END OF TXDMA REGISTER ADDRESS MAP */
-
-
-/* START OF RXDMA REGISTER ADDRESS MAP */
-
-/*
- * structure for control status reg in rxdma address map
- * Located at address 0x2000
- *
- * CSR
- * 0: halt
- * 1-3: tc
- * 4: fbr_big_endian
- * 5: psr_big_endian
- * 6: pkt_big_endian
- * 7: dma_big_endian
- * 8-9: fbr0_size
- * 10: fbr0_enable
- * 11-12: fbr1_size
- * 13: fbr1_enable
- * 14: unused
- * 15: pkt_drop_disable
- * 16: pkt_done_flush
- * 17: halt_status
- * 18-31: unused
- */
-
-
-/*
- * structure for dma writeback lo reg in rxdma address map
- * located at address 0x2004
- * Defined earlier (u32)
- */
-
-/*
- * structure for dma writeback hi reg in rxdma address map
- * located at address 0x2008
- * Defined earlier (u32)
- */
-
-/*
- * structure for number of packets done reg in rxdma address map
- * located at address 0x200C
- *
- * 31-8: unused
- * 7-0: num done
- */
-
-/*
- * structure for max packet time reg in rxdma address map
- * located at address 0x2010
- *
- * 31-18: unused
- * 17-0: time done
- */
-
-/*
- * structure for rx queue read address reg in rxdma address map
- * located at address 0x2014
- * Defined earlier (u32)
- */
-
-/*
- * structure for rx queue read address external reg in rxdma address map
- * located at address 0x2018
- * Defined earlier (u32)
- */
-
-/*
- * structure for rx queue write address reg in rxdma address map
- * located at address 0x201C
- * Defined earlier (u32)
- */
-
-/*
- * structure for packet status ring base address lo reg in rxdma address map
- * located at address 0x2020
- * Defined earlier (u32)
- */
-
-/*
- * structure for packet status ring base address hi reg in rxdma address map
- * located at address 0x2024
- * Defined earlier (u32)
- */
-
-/*
- * structure for packet status ring number of descriptors reg in rxdma address
- * map. Located at address 0x2028
- *
- * 31-12: unused
- * 11-0: psr ndes
- */
-
-/*
- * structure for packet status ring available offset reg in rxdma address map
- * located at address 0x202C
- *
- * 31-13: unused
- * 12: psr avail wrap
- * 11-0: psr avail
- */
-
-/*
- * structure for packet status ring full offset reg in rxdma address map
- * located at address 0x2030
- *
- * 31-13: unused
- * 12: psr full wrap
- * 11-0: psr full
- */
-
-/*
- * structure for packet status ring access index reg in rxdma address map
- * located at address 0x2034
- *
- * 31-5: unused
- * 4-0: psr_ai
- */
-
-/*
- * structure for packet status ring minimum descriptors reg in rxdma address
- * map. Located at address 0x2038
- *
- * 31-12: unused
- * 11-0: psr_min
- */
-
-/*
- * structure for free buffer ring base lo address reg in rxdma address map
- * located at address 0x203C
- * Defined earlier (u32)
- */
-
-/*
- * structure for free buffer ring base hi address reg in rxdma address map
- * located at address 0x2040
- * Defined earlier (u32)
- */
-
-/*
- * structure for free buffer ring number of descriptors reg in rxdma address
- * map. Located at address 0x2044
- *
- * 31-10: unused
- * 9-0: fbr ndesc
- */
-
-/*
- * structure for free buffer ring 0 available offset reg in rxdma address map
- * located at address 0x2048
- * Defined earlier (u32)
- */
-
-/*
- * structure for free buffer ring 0 full offset reg in rxdma address map
- * located at address 0x204C
- * Defined earlier (u32)
- */
-
-/*
- * structure for free buffer cache 0 full offset reg in rxdma address map
- * located at address 0x2050
- *
- * 31-5: unused
- * 4-0: fbc rdi
- */
-
-/*
- * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
- * located at address 0x2054
- *
- * 31-10: unused
- * 9-0: fbr min
- */
-
-/*
- * structure for free buffer ring 1 base address lo reg in rxdma address map
- * located at address 0x2058 - 0x205C
- * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
- */
-
-/*
- * structure for free buffer ring 1 number of descriptors reg in rxdma address
- * map. Located at address 0x2060
- * Defined earlier (RXDMA_FBR_NUM_DES_t)
- */
-
-/*
- * structure for free buffer ring 1 available offset reg in rxdma address map
- * located at address 0x2064
- * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
- */
-
-/*
- * structure for free buffer ring 1 full offset reg in rxdma address map
- * located at address 0x2068
- * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
- */
-
-/*
- * structure for free buffer cache 1 read index reg in rxdma address map
- * located at address 0x206C
- * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
- */
-
-/*
- * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
- * located at address 0x2070
- * Defined Earlier (RXDMA_FBR_MIN_DES_t)
- */
-
-/*
- * Rx DMA Module of JAGCore Address Mapping
- * Located at address 0x2000
- */
-struct rxdma_regs { /* Location: */
- u32 csr; /* 0x2000 */
- u32 dma_wb_base_lo; /* 0x2004 */
- u32 dma_wb_base_hi; /* 0x2008 */
- u32 num_pkt_done; /* 0x200C */
- u32 max_pkt_time; /* 0x2010 */
- u32 rxq_rd_addr; /* 0x2014 */
- u32 rxq_rd_addr_ext; /* 0x2018 */
- u32 rxq_wr_addr; /* 0x201C */
- u32 psr_base_lo; /* 0x2020 */
- u32 psr_base_hi; /* 0x2024 */
- u32 psr_num_des; /* 0x2028 */
- u32 psr_avail_offset; /* 0x202C */
- u32 psr_full_offset; /* 0x2030 */
- u32 psr_access_index; /* 0x2034 */
- u32 psr_min_des; /* 0x2038 */
- u32 fbr0_base_lo; /* 0x203C */
- u32 fbr0_base_hi; /* 0x2040 */
- u32 fbr0_num_des; /* 0x2044 */
- u32 fbr0_avail_offset; /* 0x2048 */
- u32 fbr0_full_offset; /* 0x204C */
- u32 fbr0_rd_index; /* 0x2050 */
- u32 fbr0_min_des; /* 0x2054 */
- u32 fbr1_base_lo; /* 0x2058 */
- u32 fbr1_base_hi; /* 0x205C */
- u32 fbr1_num_des; /* 0x2060 */
- u32 fbr1_avail_offset; /* 0x2064 */
- u32 fbr1_full_offset; /* 0x2068 */
- u32 fbr1_rd_index; /* 0x206C */
- u32 fbr1_min_des; /* 0x2070 */
-};
-
-/* END OF RXDMA REGISTER ADDRESS MAP */
-
-
-/* START OF TXMAC REGISTER ADDRESS MAP */
-
-/*
- * structure for control reg in txmac address map
- * located at address 0x3000
- *
- * bits
- * 31-8: unused
- * 7: cklseg_disable
- * 6: ckbcnt_disable
- * 5: cksegnum
- * 4: async_disable
- * 3: fc_disable
- * 2: mcif_disable
- * 1: mif_disable
- * 0: txmac_en
- */
-
-/*
- * structure for shadow pointer reg in txmac address map
- * located at address 0x3004
- * 31-27: reserved
- * 26-16: txq rd ptr
- * 15-11: reserved
- * 10-0: txq wr ptr
- */
-
-/*
- * structure for error count reg in txmac address map
- * located at address 0x3008
- *
- * 31-12: unused
- * 11-8: reserved
- * 7-4: txq_underrun
- * 3-0: fifo_underrun
- */
-
-/*
- * structure for max fill reg in txmac address map
- * located at address 0x300C
- * 31-12: unused
- * 11-0: max fill
- */
-
-/*
- * structure for cf parameter reg in txmac address map
- * located at address 0x3010
- * 31-16: cfep
- * 15-0: cfpt
- */
-
-/*
- * structure for tx test reg in txmac address map
- * located at address 0x3014
- * 31-17: unused
- * 16: reserved1
- * 15: txtest_en
- * 14-11: unused
- * 10-0: txq test pointer
- */
-
-/*
- * structure for error reg in txmac address map
- * located at address 0x3018
- *
- * 31-9: unused
- * 8: fifo_underrun
- * 7-6: unused
- * 5: ctrl2_err
- * 4: txq_underrun
- * 3: bcnt_err
- * 2: lseg_err
- * 1: segnum_err
- * 0: seg0_err
- */
-
-/*
- * structure for error interrupt reg in txmac address map
- * located at address 0x301C
- *
- * 31-9: unused
- * 8: fifo_underrun
- * 7-6: unused
- * 5: ctrl2_err
- * 4: txq_underrun
- * 3: bcnt_err
- * 2: lseg_err
- * 1: segnum_err
- * 0: seg0_err
- */
-
-/*
- * structure for error interrupt reg in txmac address map
- * located at address 0x3020
- *
- * 31-2: unused
- * 1: bp_req
- * 0: bp_xonxoff
- */
-
-/*
- * Tx MAC Module of JAGCore Address Mapping
- */
-struct txmac_regs { /* Location: */
- u32 ctl; /* 0x3000 */
- u32 shadow_ptr; /* 0x3004 */
- u32 err_cnt; /* 0x3008 */
- u32 max_fill; /* 0x300C */
- u32 cf_param; /* 0x3010 */
- u32 tx_test; /* 0x3014 */
- u32 err; /* 0x3018 */
- u32 err_int; /* 0x301C */
- u32 bp_ctrl; /* 0x3020 */
-};
-
-/* END OF TXMAC REGISTER ADDRESS MAP */
-
-/* START OF RXMAC REGISTER ADDRESS MAP */
-
-/*
- * structure for rxmac control reg in rxmac address map
- * located at address 0x4000
- *
- * 31-7: reserved
- * 6: rxmac_int_disable
- * 5: async_disable
- * 4: mif_disable
- * 3: wol_disable
- * 2: pkt_filter_disable
- * 1: mcif_disable
- * 0: rxmac_en
- */
-
-/*
- * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
- * located at address 0x4004
- * 31-16: crc
- * 15-12: reserved
- * 11: ignore_pp
- * 10: ignore_mp
- * 9: clr_intr
- * 8: ignore_link_chg
- * 7: ignore_uni
- * 6: ignore_multi
- * 5: ignore_broad
- * 4-0: valid_crc 4-0
- */
-
-/*
- * structure for CRC 1 and CRC 2 reg in rxmac address map
- * located at address 0x4008
- *
- * 31-16: crc2
- * 15-0: crc1
- */
-
-/*
- * structure for CRC 3 and CRC 4 reg in rxmac address map
- * located at address 0x400C
- *
- * 31-16: crc4
- * 15-0: crc3
- */
-
-/*
- * structure for Wake On Lan Source Address Lo reg in rxmac address map
- * located at address 0x4010
- *
- * 31-24: sa3
- * 23-16: sa4
- * 15-8: sa5
- * 7-0: sa6
- */
-
-#define ET_WOL_LO_SA3_SHIFT 24
-#define ET_WOL_LO_SA4_SHIFT 16
-#define ET_WOL_LO_SA5_SHIFT 8
-
-/*
- * structure for Wake On Lan Source Address Hi reg in rxmac address map
- * located at address 0x4014
- *
- * 31-16: reserved
- * 15-8: sa1
- * 7-0: sa2
- */
-
-#define ET_WOL_HI_SA1_SHIFT 8
-
-/*
- * structure for Wake On Lan mask reg in rxmac address map
- * located at address 0x4018 - 0x4064
- * Defined earlier (u32)
- */
-
-/*
- * structure for Unicast Paket Filter Address 1 reg in rxmac address map
- * located at address 0x4068
- *
- * 31-24: addr1_3
- * 23-16: addr1_4
- * 15-8: addr1_5
- * 7-0: addr1_6
- */
-
-#define ET_UNI_PF_ADDR1_3_SHIFT 24
-#define ET_UNI_PF_ADDR1_4_SHIFT 16
-#define ET_UNI_PF_ADDR1_5_SHIFT 8
-
-/*
- * structure for Unicast Paket Filter Address 2 reg in rxmac address map
- * located at address 0x406C
- *
- * 31-24: addr2_3
- * 23-16: addr2_4
- * 15-8: addr2_5
- * 7-0: addr2_6
- */
-
-#define ET_UNI_PF_ADDR2_3_SHIFT 24
-#define ET_UNI_PF_ADDR2_4_SHIFT 16
-#define ET_UNI_PF_ADDR2_5_SHIFT 8
-
-/*
- * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
- * located at address 0x4070
- *
- * 31-24: addr2_1
- * 23-16: addr2_2
- * 15-8: addr1_1
- * 7-0: addr1_2
- */
-
-#define ET_UNI_PF_ADDR2_1_SHIFT 24
-#define ET_UNI_PF_ADDR2_2_SHIFT 16
-#define ET_UNI_PF_ADDR1_1_SHIFT 8
-
-
-/*
- * structure for Multicast Hash reg in rxmac address map
- * located at address 0x4074 - 0x4080
- * Defined earlier (u32)
- */
-
-/*
- * structure for Packet Filter Control reg in rxmac address map
- * located at address 0x4084
- *
- * 31-23: unused
- * 22-16: min_pkt_size
- * 15-4: unused
- * 3: filter_frag_en
- * 2: filter_uni_en
- * 1: filter_multi_en
- * 0: filter_broad_en
- */
-
-/*
- * structure for Memory Controller Interface Control Max Segment reg in rxmac
- * address map. Located at address 0x4088
- *
- * 31-10: reserved
- * 9-2: max_size
- * 1: fc_en
- * 0: seg_en
- */
-
-/*
- * structure for Memory Controller Interface Water Mark reg in rxmac address
- * map. Located at address 0x408C
- *
- * 31-26: unused
- * 25-16: mark_hi
- * 15-10: unused
- * 9-0: mark_lo
- */
-
-/*
- * structure for Rx Queue Dialog reg in rxmac address map.
- * located at address 0x4090
- *
- * 31-26: reserved
- * 25-16: rd_ptr
- * 15-10: reserved
- * 9-0: wr_ptr
- */
-
-/*
- * structure for space available reg in rxmac address map.
- * located at address 0x4094
- *
- * 31-17: reserved
- * 16: space_avail_en
- * 15-10: reserved
- * 9-0: space_avail
- */
-
-/*
- * structure for management interface reg in rxmac address map.
- * located at address 0x4098
- *
- * 31-18: reserved
- * 17: drop_pkt_en
- * 16-0: drop_pkt_mask
- */
-
-/*
- * structure for Error reg in rxmac address map.
- * located at address 0x409C
- *
- * 31-4: unused
- * 3: mif
- * 2: async
- * 1: pkt_filter
- * 0: mcif
- */
-
-/*
- * Rx MAC Module of JAGCore Address Mapping
- */
-struct rxmac_regs { /* Location: */
- u32 ctrl; /* 0x4000 */
- u32 crc0; /* 0x4004 */
- u32 crc12; /* 0x4008 */
- u32 crc34; /* 0x400C */
- u32 sa_lo; /* 0x4010 */
- u32 sa_hi; /* 0x4014 */
- u32 mask0_word0; /* 0x4018 */
- u32 mask0_word1; /* 0x401C */
- u32 mask0_word2; /* 0x4020 */
- u32 mask0_word3; /* 0x4024 */
- u32 mask1_word0; /* 0x4028 */
- u32 mask1_word1; /* 0x402C */
- u32 mask1_word2; /* 0x4030 */
- u32 mask1_word3; /* 0x4034 */
- u32 mask2_word0; /* 0x4038 */
- u32 mask2_word1; /* 0x403C */
- u32 mask2_word2; /* 0x4040 */
- u32 mask2_word3; /* 0x4044 */
- u32 mask3_word0; /* 0x4048 */
- u32 mask3_word1; /* 0x404C */
- u32 mask3_word2; /* 0x4050 */
- u32 mask3_word3; /* 0x4054 */
- u32 mask4_word0; /* 0x4058 */
- u32 mask4_word1; /* 0x405C */
- u32 mask4_word2; /* 0x4060 */
- u32 mask4_word3; /* 0x4064 */
- u32 uni_pf_addr1; /* 0x4068 */
- u32 uni_pf_addr2; /* 0x406C */
- u32 uni_pf_addr3; /* 0x4070 */
- u32 multi_hash1; /* 0x4074 */
- u32 multi_hash2; /* 0x4078 */
- u32 multi_hash3; /* 0x407C */
- u32 multi_hash4; /* 0x4080 */
- u32 pf_ctrl; /* 0x4084 */
- u32 mcif_ctrl_max_seg; /* 0x4088 */
- u32 mcif_water_mark; /* 0x408C */
- u32 rxq_diag; /* 0x4090 */
- u32 space_avail; /* 0x4094 */
-
- u32 mif_ctrl; /* 0x4098 */
- u32 err_reg; /* 0x409C */
-};
-
-/* END OF RXMAC REGISTER ADDRESS MAP */
-
-
-/* START OF MAC REGISTER ADDRESS MAP */
-
-/*
- * structure for configuration #1 reg in mac address map.
- * located at address 0x5000
- *
- * 31: soft reset
- * 30: sim reset
- * 29-20: reserved
- * 19: reset rx mc
- * 18: reset tx mc
- * 17: reset rx func
- * 16: reset tx fnc
- * 15-9: reserved
- * 8: loopback
- * 7-6: reserved
- * 5: rx flow
- * 4: tx flow
- * 3: syncd rx en
- * 2: rx enable
- * 1: syncd tx en
- * 0: tx enable
- */
-
-#define CFG1_LOOPBACK 0x00000100
-#define CFG1_RX_FLOW 0x00000020
-#define CFG1_TX_FLOW 0x00000010
-#define CFG1_RX_ENABLE 0x00000004
-#define CFG1_TX_ENABLE 0x00000001
-#define CFG1_WAIT 0x0000000A /* RX & TX syncd */
-
-/*
- * structure for configuration #2 reg in mac address map.
- * located at address 0x5004
- * 31-16: reserved
- * 15-12: preamble
- * 11-10: reserved
- * 9-8: if mode
- * 7-6: reserved
- * 5: huge frame
- * 4: length check
- * 3: undefined
- * 2: pad crc
- * 1: crc enable
- * 0: full duplex
- */
-
-
-/*
- * structure for Interpacket gap reg in mac address map.
- * located at address 0x5008
- *
- * 31: reserved
- * 30-24: non B2B ipg 1
- * 23: undefined
- * 22-16: non B2B ipg 2
- * 15-8: Min ifg enforce
- * 7-0: B2B ipg
- *
- * structure for half duplex reg in mac address map.
- * located at address 0x500C
- * 31-24: reserved
- * 23-20: Alt BEB trunc
- * 19: Alt BEB enable
- * 18: BP no backoff
- * 17: no backoff
- * 16: excess defer
- * 15-12: re-xmit max
- * 11-10: reserved
- * 9-0: collision window
- */
-
-/*
- * structure for Maximum Frame Length reg in mac address map.
- * located at address 0x5010: bits 0-15 hold the length.
- */
-
-/*
- * structure for Reserve 1 reg in mac address map.
- * located at address 0x5014 - 0x5018
- * Defined earlier (u32)
- */
-
-/*
- * structure for Test reg in mac address map.
- * located at address 0x501C
- * test: bits 0-2, rest unused
- */
-
-/*
- * structure for MII Management Configuration reg in mac address map.
- * located at address 0x5020
- *
- * 31: reset MII mgmt
- * 30-6: unused
- * 5: scan auto increment
- * 4: preamble suppress
- * 3: undefined
- * 2-0: mgmt clock reset
- */
-
-/*
- * structure for MII Management Command reg in mac address map.
- * located at address 0x5024
- * bit 1: scan cycle
- * bit 0: read cycle
- */
-
-/*
- * structure for MII Management Address reg in mac address map.
- * located at address 0x5028
- * 31-13: reserved
- * 12-8: phy addr
- * 7-5: reserved
- * 4-0: register
- */
-
-#define MII_ADDR(phy, reg) ((phy) << 8 | (reg))
-
-/*
- * structure for MII Management Control reg in mac address map.
- * located at address 0x502C
- * 31-16: reserved
- * 15-0: phy control
- */
-
-/*
- * structure for MII Management Status reg in mac address map.
- * located at address 0x5030
- * 31-16: reserved
- * 15-0: phy control
- */
-
-/*
- * structure for MII Management Indicators reg in mac address map.
- * located at address 0x5034
- * 31-3: reserved
- * 2: not valid
- * 1: scanning
- * 0: busy
- */
-
-#define MGMT_BUSY 0x00000001 /* busy */
-#define MGMT_WAIT 0x00000005 /* busy | not valid */
-
-/*
- * structure for Interface Control reg in mac address map.
- * located at address 0x5038
- *
- * 31: reset if module
- * 30-28: reserved
- * 27: tbi mode
- * 26: ghd mode
- * 25: lhd mode
- * 24: phy mode
- * 23: reset per mii
- * 22-17: reserved
- * 16: speed
- * 15: reset pe100x
- * 14-11: reserved
- * 10: force quiet
- * 9: no cipher
- * 8: disable link fail
- * 7: reset gpsi
- * 6-1: reserved
- * 0: enable jabber protection
- */
-
-/*
- * structure for Interface Status reg in mac address map.
- * located at address 0x503C
- *
- * 31-10: reserved
- * 9: excess_defer
- * 8: clash
- * 7: phy_jabber
- * 6: phy_link_ok
- * 5: phy_full_duplex
- * 4: phy_speed
- * 3: pe100x_link_fail
- * 2: pe10t_loss_carrier
- * 1: pe10t_sqe_error
- * 0: pe10t_jabber
- */
-
-/*
- * structure for Mac Station Address, Part 1 reg in mac address map.
- * located at address 0x5040
- *
- * 31-24: Octet6
- * 23-16: Octet5
- * 15-8: Octet4
- * 7-0: Octet3
- */
-
-#define ET_MAC_STATION_ADDR1_OC6_SHIFT 24
-#define ET_MAC_STATION_ADDR1_OC5_SHIFT 16
-#define ET_MAC_STATION_ADDR1_OC4_SHIFT 8
-
-/*
- * structure for Mac Station Address, Part 2 reg in mac address map.
- * located at address 0x5044
- *
- * 31-24: Octet2
- * 23-16: Octet1
- * 15-0: reserved
- */
-
-#define ET_MAC_STATION_ADDR2_OC2_SHIFT 24
-#define ET_MAC_STATION_ADDR2_OC1_SHIFT 16
-
-/*
- * MAC Module of JAGCore Address Mapping
- */
-struct mac_regs { /* Location: */
- u32 cfg1; /* 0x5000 */
- u32 cfg2; /* 0x5004 */
- u32 ipg; /* 0x5008 */
- u32 hfdp; /* 0x500C */
- u32 max_fm_len; /* 0x5010 */
- u32 rsv1; /* 0x5014 */
- u32 rsv2; /* 0x5018 */
- u32 mac_test; /* 0x501C */
- u32 mii_mgmt_cfg; /* 0x5020 */
- u32 mii_mgmt_cmd; /* 0x5024 */
- u32 mii_mgmt_addr; /* 0x5028 */
- u32 mii_mgmt_ctrl; /* 0x502C */
- u32 mii_mgmt_stat; /* 0x5030 */
- u32 mii_mgmt_indicator; /* 0x5034 */
- u32 if_ctrl; /* 0x5038 */
- u32 if_stat; /* 0x503C */
- u32 station_addr_1; /* 0x5040 */
- u32 station_addr_2; /* 0x5044 */
-};
-
-/* END OF MAC REGISTER ADDRESS MAP */
-
-/* START OF MAC STAT REGISTER ADDRESS MAP */
-
-/*
- * structure for Carry Register One and it's Mask Register reg located in mac
- * stat address map address 0x6130 and 0x6138.
- *
- * 31: tr64
- * 30: tr127
- * 29: tr255
- * 28: tr511
- * 27: tr1k
- * 26: trmax
- * 25: trmgv
- * 24-17: unused
- * 16: rbyt
- * 15: rpkt
- * 14: rfcs
- * 13: rmca
- * 12: rbca
- * 11: rxcf
- * 10: rxpf
- * 9: rxuo
- * 8: raln
- * 7: rflr
- * 6: rcde
- * 5: rcse
- * 4: rund
- * 3: rovr
- * 2: rfrg
- * 1: rjbr
- * 0: rdrp
- */
-
-/*
- * structure for Carry Register Two Mask Register reg in mac stat address map.
- * located at address 0x613C
- *
- * 31-20: unused
- * 19: tjbr
- * 18: tfcs
- * 17: txcf
- * 16: tovr
- * 15: tund
- * 14: trfg
- * 13: tbyt
- * 12: tpkt
- * 11: tmca
- * 10: tbca
- * 9: txpf
- * 8: tdfr
- * 7: tedf
- * 6: tscl
- * 5: tmcl
- * 4: tlcl
- * 3: txcl
- * 2: tncl
- * 1: tpfh
- * 0: tdrp
- */
-
-/*
- * MAC STATS Module of JAGCore Address Mapping
- */
-struct macstat_regs { /* Location: */
- u32 pad[32]; /* 0x6000 - 607C */
-
- /* Tx/Rx 0-64 Byte Frame Counter */
- u32 txrx_0_64_byte_frames; /* 0x6080 */
-
- /* Tx/Rx 65-127 Byte Frame Counter */
- u32 txrx_65_127_byte_frames; /* 0x6084 */
-
- /* Tx/Rx 128-255 Byte Frame Counter */
- u32 txrx_128_255_byte_frames; /* 0x6088 */
-
- /* Tx/Rx 256-511 Byte Frame Counter */
- u32 txrx_256_511_byte_frames; /* 0x608C */
-
- /* Tx/Rx 512-1023 Byte Frame Counter */
- u32 txrx_512_1023_byte_frames; /* 0x6090 */
-
- /* Tx/Rx 1024-1518 Byte Frame Counter */
- u32 txrx_1024_1518_byte_frames; /* 0x6094 */
-
- /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
- u32 txrx_1519_1522_gvln_frames; /* 0x6098 */
-
- /* Rx Byte Counter */
- u32 rx_bytes; /* 0x609C */
-
- /* Rx Packet Counter */
- u32 rx_packets; /* 0x60A0 */
-
- /* Rx FCS Error Counter */
- u32 rx_fcs_errs; /* 0x60A4 */
-
- /* Rx Multicast Packet Counter */
- u32 rx_multicast_packets; /* 0x60A8 */
-
- /* Rx Broadcast Packet Counter */
- u32 rx_broadcast_packets; /* 0x60AC */
-
- /* Rx Control Frame Packet Counter */
- u32 rx_control_frames; /* 0x60B0 */
-
- /* Rx Pause Frame Packet Counter */
- u32 rx_pause_frames; /* 0x60B4 */
-
- /* Rx Unknown OP Code Counter */
- u32 rx_unknown_opcodes; /* 0x60B8 */
-
- /* Rx Alignment Error Counter */
- u32 rx_align_errs; /* 0x60BC */
-
- /* Rx Frame Length Error Counter */
- u32 rx_frame_len_errs; /* 0x60C0 */
-
- /* Rx Code Error Counter */
- u32 rx_code_errs; /* 0x60C4 */
-
- /* Rx Carrier Sense Error Counter */
- u32 rx_carrier_sense_errs; /* 0x60C8 */
-
- /* Rx Undersize Packet Counter */
- u32 rx_undersize_packets; /* 0x60CC */
-
- /* Rx Oversize Packet Counter */
- u32 rx_oversize_packets; /* 0x60D0 */
-
- /* Rx Fragment Counter */
- u32 rx_fragment_packets; /* 0x60D4 */
-
- /* Rx Jabber Counter */
- u32 rx_jabbers; /* 0x60D8 */
-
- /* Rx Drop */
- u32 rx_drops; /* 0x60DC */
-
- /* Tx Byte Counter */
- u32 tx_bytes; /* 0x60E0 */
-
- /* Tx Packet Counter */
- u32 tx_packets; /* 0x60E4 */
-
- /* Tx Multicast Packet Counter */
- u32 tx_multicast_packets; /* 0x60E8 */
-
- /* Tx Broadcast Packet Counter */
- u32 tx_broadcast_packets; /* 0x60EC */
-
- /* Tx Pause Control Frame Counter */
- u32 tx_pause_frames; /* 0x60F0 */
-
- /* Tx Deferral Packet Counter */
- u32 tx_deferred; /* 0x60F4 */
-
- /* Tx Excessive Deferral Packet Counter */
- u32 tx_excessive_deferred; /* 0x60F8 */
-
- /* Tx Single Collision Packet Counter */
- u32 tx_single_collisions; /* 0x60FC */
-
- /* Tx Multiple Collision Packet Counter */
- u32 tx_multiple_collisions; /* 0x6100 */
-
- /* Tx Late Collision Packet Counter */
- u32 tx_late_collisions; /* 0x6104 */
-
- /* Tx Excessive Collision Packet Counter */
- u32 tx_excessive_collisions; /* 0x6108 */
-
- /* Tx Total Collision Packet Counter */
- u32 tx_total_collisions; /* 0x610C */
-
- /* Tx Pause Frame Honored Counter */
- u32 tx_pause_honored_frames; /* 0x6110 */
-
- /* Tx Drop Frame Counter */
- u32 tx_drops; /* 0x6114 */
-
- /* Tx Jabber Frame Counter */
- u32 tx_jabbers; /* 0x6118 */
-
- /* Tx FCS Error Counter */
- u32 tx_fcs_errs; /* 0x611C */
-
- /* Tx Control Frame Counter */
- u32 tx_control_frames; /* 0x6120 */
-
- /* Tx Oversize Frame Counter */
- u32 tx_oversize_frames; /* 0x6124 */
-
- /* Tx Undersize Frame Counter */
- u32 tx_undersize_frames; /* 0x6128 */
-
- /* Tx Fragments Frame Counter */
- u32 tx_fragments; /* 0x612C */
-
- /* Carry Register One Register */
- u32 carry_reg1; /* 0x6130 */
-
- /* Carry Register Two Register */
- u32 carry_reg2; /* 0x6134 */
-
- /* Carry Register One Mask Register */
- u32 carry_reg1_mask; /* 0x6138 */
-
- /* Carry Register Two Mask Register */
- u32 carry_reg2_mask; /* 0x613C */
-};
-
-/* END OF MAC STAT REGISTER ADDRESS MAP */
-
-
-/* START OF MMC REGISTER ADDRESS MAP */
-
-/*
- * Main Memory Controller Control reg in mmc address map.
- * located at address 0x7000
- */
-
-#define ET_MMC_ENABLE 1
-#define ET_MMC_ARB_DISABLE 2
-#define ET_MMC_RXMAC_DISABLE 4
-#define ET_MMC_TXMAC_DISABLE 8
-#define ET_MMC_TXDMA_DISABLE 16
-#define ET_MMC_RXDMA_DISABLE 32
-#define ET_MMC_FORCE_CE 64
-
-/*
- * Main Memory Controller Host Memory Access Address reg in mmc
- * address map. Located at address 0x7004. Top 16 bits hold the address bits
- */
-
-#define ET_SRAM_REQ_ACCESS 1
-#define ET_SRAM_WR_ACCESS 2
-#define ET_SRAM_IS_CTRL 4
-
-/*
- * structure for Main Memory Controller Host Memory Access Data reg in mmc
- * address map. Located at address 0x7008 - 0x7014
- * Defined earlier (u32)
- */
-
-/*
- * Memory Control Module of JAGCore Address Mapping
- */
-struct mmc_regs { /* Location: */
- u32 mmc_ctrl; /* 0x7000 */
- u32 sram_access; /* 0x7004 */
- u32 sram_word1; /* 0x7008 */
- u32 sram_word2; /* 0x700C */
- u32 sram_word3; /* 0x7010 */
- u32 sram_word4; /* 0x7014 */
-};
-
-/* END OF MMC REGISTER ADDRESS MAP */
-
-
-/*
- * JAGCore Address Mapping
- */
-struct address_map {
- struct global_regs global;
- /* unused section of global address map */
- u8 unused_global[4096 - sizeof(struct global_regs)];
- struct txdma_regs txdma;
- /* unused section of txdma address map */
- u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
- struct rxdma_regs rxdma;
- /* unused section of rxdma address map */
- u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
- struct txmac_regs txmac;
- /* unused section of txmac address map */
- u8 unused_txmac[4096 - sizeof(struct txmac_regs)];
- struct rxmac_regs rxmac;
- /* unused section of rxmac address map */
- u8 unused_rxmac[4096 - sizeof(struct rxmac_regs)];
- struct mac_regs mac;
- /* unused section of mac address map */
- u8 unused_mac[4096 - sizeof(struct mac_regs)];
- struct macstat_regs macstat;
- /* unused section of mac stat address map */
- u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
- struct mmc_regs mmc;
- /* unused section of mmc address map */
- u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
- /* unused section of address map */
- u8 unused_[1015808];
-
- u8 unused_exp_rom[4096]; /* MGS-size TBD */
- u8 unused__[524288]; /* unused section of address map */
-};
-
-#endif /* _ET1310_ADDRESS_MAP_H_ */
diff --git a/drivers/staging/et131x/et1310_phy.h b/drivers/staging/et131x/et1310_phy.h
index 2803bdf..feb5761 100644
--- a/drivers/staging/et131x/et1310_phy.h
+++ b/drivers/staging/et131x/et1310_phy.h
@@ -61,8 +61,6 @@
#ifndef _ET1310_PHY_H_
#define _ET1310_PHY_H_
-#include "et1310_address_map.h"
-
/*
* Defines for generic MII registers 0x00 -> 0x0F can be found in
* include/linux/mii.h
diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h
index a19fab9..b3b1bc9 100644
--- a/drivers/staging/et131x/et1310_rx.h
+++ b/drivers/staging/et131x/et1310_rx.h
@@ -61,8 +61,6 @@
#ifndef __ET1310_RX_H__
#define __ET1310_RX_H__
-#include "et1310_address_map.h"
-
#define USE_FBR0 true
#ifdef USE_FBR0
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index cad271b..60ff3bc 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -85,7 +85,6 @@
#include "et1310_phy.h"
#include "et131x_adapter.h"
-#include "et1310_address_map.h"
#include "et1310_tx.h"
#include "et1310_rx.h"
#include "et131x.h"
diff --git a/drivers/staging/et131x/et131x.h b/drivers/staging/et131x/et131x.h
index 115d307..8f61a72 100644
--- a/drivers/staging/et131x/et131x.h
+++ b/drivers/staging/et131x/et131x.h
@@ -77,3 +77,1373 @@
#define LBCIF_STATUS_CHECKSUM_ERROR 0x40
#define LBCIF_STATUS_EEPROM_PRESENT 0x80
+/* START OF GLOBAL REGISTER ADDRESS MAP */
+
+/*
+ * 10bit registers
+ *
+ * Tx queue start address reg in global address map at address 0x0000
+ * tx queue end address reg in global address map at address 0x0004
+ * rx queue start address reg in global address map at address 0x0008
+ * rx queue end address reg in global address map at address 0x000C
+ */
+
+/*
+ * structure for power management control status reg in global address map
+ * located at address 0x0010
+ * jagcore_rx_rdy bit 9
+ * jagcore_tx_rdy bit 8
+ * phy_lped_en bit 7
+ * phy_sw_coma bit 6
+ * rxclk_gate bit 5
+ * txclk_gate bit 4
+ * sysclk_gate bit 3
+ * jagcore_rx_en bit 2
+ * jagcore_tx_en bit 1
+ * gigephy_en bit 0
+ */
+
+#define ET_PM_PHY_SW_COMA 0x40
+#define ET_PMCSR_INIT 0x38
+
+/*
+ * Interrupt status reg at address 0x0018
+ */
+
+#define ET_INTR_TXDMA_ISR 0x00000008
+#define ET_INTR_TXDMA_ERR 0x00000010
+#define ET_INTR_RXDMA_XFR_DONE 0x00000020
+#define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
+#define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
+#define ET_INTR_RXDMA_STAT_LOW 0x00000100
+#define ET_INTR_RXDMA_ERR 0x00000200
+#define ET_INTR_WATCHDOG 0x00004000
+#define ET_INTR_WOL 0x00008000
+#define ET_INTR_PHY 0x00010000
+#define ET_INTR_TXMAC 0x00020000
+#define ET_INTR_RXMAC 0x00040000
+#define ET_INTR_MAC_STAT 0x00080000
+#define ET_INTR_SLV_TIMEOUT 0x00100000
+
+/*
+ * Interrupt mask register at address 0x001C
+ * Interrupt alias clear mask reg at address 0x0020
+ * Interrupt status alias reg at address 0x0024
+ *
+ * Same masks as above
+ */
+
+/*
+ * Software reset reg at address 0x0028
+ * 0: txdma_sw_reset
+ * 1: rxdma_sw_reset
+ * 2: txmac_sw_reset
+ * 3: rxmac_sw_reset
+ * 4: mac_sw_reset
+ * 5: mac_stat_sw_reset
+ * 6: mmc_sw_reset
+ *31: selfclr_disable
+ */
+
+/*
+ * SLV Timer reg at address 0x002C (low 24 bits)
+ */
+
+/*
+ * MSI Configuration reg at address 0x0030
+ */
+
+#define ET_MSI_VECTOR 0x0000001F
+#define ET_MSI_TC 0x00070000
+
+/*
+ * Loopback reg located at address 0x0034
+ */
+
+#define ET_LOOP_MAC 0x00000001
+#define ET_LOOP_DMA 0x00000002
+
+/*
+ * GLOBAL Module of JAGCore Address Mapping
+ * Located at address 0x0000
+ */
+struct global_regs { /* Location: */
+ u32 txq_start_addr; /* 0x0000 */
+ u32 txq_end_addr; /* 0x0004 */
+ u32 rxq_start_addr; /* 0x0008 */
+ u32 rxq_end_addr; /* 0x000C */
+ u32 pm_csr; /* 0x0010 */
+ u32 unused; /* 0x0014 */
+ u32 int_status; /* 0x0018 */
+ u32 int_mask; /* 0x001C */
+ u32 int_alias_clr_en; /* 0x0020 */
+ u32 int_status_alias; /* 0x0024 */
+ u32 sw_reset; /* 0x0028 */
+ u32 slv_timer; /* 0x002C */
+ u32 msi_config; /* 0x0030 */
+ u32 loopback; /* 0x0034 */
+ u32 watchdog_timer; /* 0x0038 */
+};
+
+
+/* START OF TXDMA REGISTER ADDRESS MAP */
+
+/*
+ * txdma control status reg at address 0x1000
+ */
+
+#define ET_TXDMA_CSR_HALT 0x00000001
+#define ET_TXDMA_DROP_TLP 0x00000002
+#define ET_TXDMA_CACHE_THRS 0x000000F0
+#define ET_TXDMA_CACHE_SHIFT 4
+#define ET_TXDMA_SNGL_EPKT 0x00000100
+#define ET_TXDMA_CLASS 0x00001E00
+
+/*
+ * structure for txdma packet ring base address hi reg in txdma address map
+ * located at address 0x1004
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for txdma packet ring base address low reg in txdma address map
+ * located at address 0x1008
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for txdma packet ring number of descriptor reg in txdma address
+ * map. Located at address 0x100C
+ *
+ * 31-10: unused
+ * 9-0: pr ndes
+ */
+
+#define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */
+#define ET_DMA12_WRAP 0x1000
+#define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */
+#define ET_DMA10_WRAP 0x0400
+#define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */
+#define ET_DMA4_WRAP 0x0010
+
+#define INDEX12(x) ((x) & ET_DMA12_MASK)
+#define INDEX10(x) ((x) & ET_DMA10_MASK)
+#define INDEX4(x) ((x) & ET_DMA4_MASK)
+
+extern inline void add_10bit(u32 *v, int n)
+{
+ *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
+}
+
+extern inline void add_12bit(u32 *v, int n)
+{
+ *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
+}
+
+/*
+ * 10bit DMA with wrap
+ * txdma tx queue write address reg in txdma address map at 0x1010
+ * txdma tx queue write address external reg in txdma address map at 0x1014
+ * txdma tx queue read address reg in txdma address map at 0x1018
+ *
+ * u32
+ * txdma status writeback address hi reg in txdma address map at0x101C
+ * txdma status writeback address lo reg in txdma address map at 0x1020
+ *
+ * 10bit DMA with wrap
+ * txdma service request reg in txdma address map at 0x1024
+ * structure for txdma service complete reg in txdma address map at 0x1028
+ *
+ * 4bit DMA with wrap
+ * txdma tx descriptor cache read index reg in txdma address map at 0x102C
+ * txdma tx descriptor cache write index reg in txdma address map at 0x1030
+ *
+ * txdma error reg in txdma address map at address 0x1034
+ * 0: PyldResend
+ * 1: PyldRewind
+ * 4: DescrResend
+ * 5: DescrRewind
+ * 8: WrbkResend
+ * 9: WrbkRewind
+ */
+
+/*
+ * Tx DMA Module of JAGCore Address Mapping
+ * Located at address 0x1000
+ */
+struct txdma_regs { /* Location: */
+ u32 csr; /* 0x1000 */
+ u32 pr_base_hi; /* 0x1004 */
+ u32 pr_base_lo; /* 0x1008 */
+ u32 pr_num_des; /* 0x100C */
+ u32 txq_wr_addr; /* 0x1010 */
+ u32 txq_wr_addr_ext; /* 0x1014 */
+ u32 txq_rd_addr; /* 0x1018 */
+ u32 dma_wb_base_hi; /* 0x101C */
+ u32 dma_wb_base_lo; /* 0x1020 */
+ u32 service_request; /* 0x1024 */
+ u32 service_complete; /* 0x1028 */
+ u32 cache_rd_index; /* 0x102C */
+ u32 cache_wr_index; /* 0x1030 */
+ u32 tx_dma_error; /* 0x1034 */
+ u32 desc_abort_cnt; /* 0x1038 */
+ u32 payload_abort_cnt; /* 0x103c */
+ u32 writeback_abort_cnt; /* 0x1040 */
+ u32 desc_timeout_cnt; /* 0x1044 */
+ u32 payload_timeout_cnt; /* 0x1048 */
+ u32 writeback_timeout_cnt; /* 0x104c */
+ u32 desc_error_cnt; /* 0x1050 */
+ u32 payload_error_cnt; /* 0x1054 */
+ u32 writeback_error_cnt; /* 0x1058 */
+ u32 dropped_tlp_cnt; /* 0x105c */
+ u32 new_service_complete; /* 0x1060 */
+ u32 ethernet_packet_cnt; /* 0x1064 */
+};
+
+/* END OF TXDMA REGISTER ADDRESS MAP */
+
+
+/* START OF RXDMA REGISTER ADDRESS MAP */
+
+/*
+ * structure for control status reg in rxdma address map
+ * Located at address 0x2000
+ *
+ * CSR
+ * 0: halt
+ * 1-3: tc
+ * 4: fbr_big_endian
+ * 5: psr_big_endian
+ * 6: pkt_big_endian
+ * 7: dma_big_endian
+ * 8-9: fbr0_size
+ * 10: fbr0_enable
+ * 11-12: fbr1_size
+ * 13: fbr1_enable
+ * 14: unused
+ * 15: pkt_drop_disable
+ * 16: pkt_done_flush
+ * 17: halt_status
+ * 18-31: unused
+ */
+
+
+/*
+ * structure for dma writeback lo reg in rxdma address map
+ * located at address 0x2004
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for dma writeback hi reg in rxdma address map
+ * located at address 0x2008
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for number of packets done reg in rxdma address map
+ * located at address 0x200C
+ *
+ * 31-8: unused
+ * 7-0: num done
+ */
+
+/*
+ * structure for max packet time reg in rxdma address map
+ * located at address 0x2010
+ *
+ * 31-18: unused
+ * 17-0: time done
+ */
+
+/*
+ * structure for rx queue read address reg in rxdma address map
+ * located at address 0x2014
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for rx queue read address external reg in rxdma address map
+ * located at address 0x2018
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for rx queue write address reg in rxdma address map
+ * located at address 0x201C
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for packet status ring base address lo reg in rxdma address map
+ * located at address 0x2020
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for packet status ring base address hi reg in rxdma address map
+ * located at address 0x2024
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for packet status ring number of descriptors reg in rxdma address
+ * map. Located at address 0x2028
+ *
+ * 31-12: unused
+ * 11-0: psr ndes
+ */
+
+/*
+ * structure for packet status ring available offset reg in rxdma address map
+ * located at address 0x202C
+ *
+ * 31-13: unused
+ * 12: psr avail wrap
+ * 11-0: psr avail
+ */
+
+/*
+ * structure for packet status ring full offset reg in rxdma address map
+ * located at address 0x2030
+ *
+ * 31-13: unused
+ * 12: psr full wrap
+ * 11-0: psr full
+ */
+
+/*
+ * structure for packet status ring access index reg in rxdma address map
+ * located at address 0x2034
+ *
+ * 31-5: unused
+ * 4-0: psr_ai
+ */
+
+/*
+ * structure for packet status ring minimum descriptors reg in rxdma address
+ * map. Located at address 0x2038
+ *
+ * 31-12: unused
+ * 11-0: psr_min
+ */
+
+/*
+ * structure for free buffer ring base lo address reg in rxdma address map
+ * located at address 0x203C
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for free buffer ring base hi address reg in rxdma address map
+ * located at address 0x2040
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for free buffer ring number of descriptors reg in rxdma address
+ * map. Located at address 0x2044
+ *
+ * 31-10: unused
+ * 9-0: fbr ndesc
+ */
+
+/*
+ * structure for free buffer ring 0 available offset reg in rxdma address map
+ * located at address 0x2048
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for free buffer ring 0 full offset reg in rxdma address map
+ * located at address 0x204C
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for free buffer cache 0 full offset reg in rxdma address map
+ * located at address 0x2050
+ *
+ * 31-5: unused
+ * 4-0: fbc rdi
+ */
+
+/*
+ * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
+ * located at address 0x2054
+ *
+ * 31-10: unused
+ * 9-0: fbr min
+ */
+
+/*
+ * structure for free buffer ring 1 base address lo reg in rxdma address map
+ * located at address 0x2058 - 0x205C
+ * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
+ */
+
+/*
+ * structure for free buffer ring 1 number of descriptors reg in rxdma address
+ * map. Located at address 0x2060
+ * Defined earlier (RXDMA_FBR_NUM_DES_t)
+ */
+
+/*
+ * structure for free buffer ring 1 available offset reg in rxdma address map
+ * located at address 0x2064
+ * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
+ */
+
+/*
+ * structure for free buffer ring 1 full offset reg in rxdma address map
+ * located at address 0x2068
+ * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
+ */
+
+/*
+ * structure for free buffer cache 1 read index reg in rxdma address map
+ * located at address 0x206C
+ * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
+ */
+
+/*
+ * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
+ * located at address 0x2070
+ * Defined Earlier (RXDMA_FBR_MIN_DES_t)
+ */
+
+/*
+ * Rx DMA Module of JAGCore Address Mapping
+ * Located at address 0x2000
+ */
+struct rxdma_regs { /* Location: */
+ u32 csr; /* 0x2000 */
+ u32 dma_wb_base_lo; /* 0x2004 */
+ u32 dma_wb_base_hi; /* 0x2008 */
+ u32 num_pkt_done; /* 0x200C */
+ u32 max_pkt_time; /* 0x2010 */
+ u32 rxq_rd_addr; /* 0x2014 */
+ u32 rxq_rd_addr_ext; /* 0x2018 */
+ u32 rxq_wr_addr; /* 0x201C */
+ u32 psr_base_lo; /* 0x2020 */
+ u32 psr_base_hi; /* 0x2024 */
+ u32 psr_num_des; /* 0x2028 */
+ u32 psr_avail_offset; /* 0x202C */
+ u32 psr_full_offset; /* 0x2030 */
+ u32 psr_access_index; /* 0x2034 */
+ u32 psr_min_des; /* 0x2038 */
+ u32 fbr0_base_lo; /* 0x203C */
+ u32 fbr0_base_hi; /* 0x2040 */
+ u32 fbr0_num_des; /* 0x2044 */
+ u32 fbr0_avail_offset; /* 0x2048 */
+ u32 fbr0_full_offset; /* 0x204C */
+ u32 fbr0_rd_index; /* 0x2050 */
+ u32 fbr0_min_des; /* 0x2054 */
+ u32 fbr1_base_lo; /* 0x2058 */
+ u32 fbr1_base_hi; /* 0x205C */
+ u32 fbr1_num_des; /* 0x2060 */
+ u32 fbr1_avail_offset; /* 0x2064 */
+ u32 fbr1_full_offset; /* 0x2068 */
+ u32 fbr1_rd_index; /* 0x206C */
+ u32 fbr1_min_des; /* 0x2070 */
+};
+
+/* END OF RXDMA REGISTER ADDRESS MAP */
+
+
+/* START OF TXMAC REGISTER ADDRESS MAP */
+
+/*
+ * structure for control reg in txmac address map
+ * located at address 0x3000
+ *
+ * bits
+ * 31-8: unused
+ * 7: cklseg_disable
+ * 6: ckbcnt_disable
+ * 5: cksegnum
+ * 4: async_disable
+ * 3: fc_disable
+ * 2: mcif_disable
+ * 1: mif_disable
+ * 0: txmac_en
+ */
+
+/*
+ * structure for shadow pointer reg in txmac address map
+ * located at address 0x3004
+ * 31-27: reserved
+ * 26-16: txq rd ptr
+ * 15-11: reserved
+ * 10-0: txq wr ptr
+ */
+
+/*
+ * structure for error count reg in txmac address map
+ * located at address 0x3008
+ *
+ * 31-12: unused
+ * 11-8: reserved
+ * 7-4: txq_underrun
+ * 3-0: fifo_underrun
+ */
+
+/*
+ * structure for max fill reg in txmac address map
+ * located at address 0x300C
+ * 31-12: unused
+ * 11-0: max fill
+ */
+
+/*
+ * structure for cf parameter reg in txmac address map
+ * located at address 0x3010
+ * 31-16: cfep
+ * 15-0: cfpt
+ */
+
+/*
+ * structure for tx test reg in txmac address map
+ * located at address 0x3014
+ * 31-17: unused
+ * 16: reserved1
+ * 15: txtest_en
+ * 14-11: unused
+ * 10-0: txq test pointer
+ */
+
+/*
+ * structure for error reg in txmac address map
+ * located at address 0x3018
+ *
+ * 31-9: unused
+ * 8: fifo_underrun
+ * 7-6: unused
+ * 5: ctrl2_err
+ * 4: txq_underrun
+ * 3: bcnt_err
+ * 2: lseg_err
+ * 1: segnum_err
+ * 0: seg0_err
+ */
+
+/*
+ * structure for error interrupt reg in txmac address map
+ * located at address 0x301C
+ *
+ * 31-9: unused
+ * 8: fifo_underrun
+ * 7-6: unused
+ * 5: ctrl2_err
+ * 4: txq_underrun
+ * 3: bcnt_err
+ * 2: lseg_err
+ * 1: segnum_err
+ * 0: seg0_err
+ */
+
+/*
+ * structure for error interrupt reg in txmac address map
+ * located at address 0x3020
+ *
+ * 31-2: unused
+ * 1: bp_req
+ * 0: bp_xonxoff
+ */
+
+/*
+ * Tx MAC Module of JAGCore Address Mapping
+ */
+struct txmac_regs { /* Location: */
+ u32 ctl; /* 0x3000 */
+ u32 shadow_ptr; /* 0x3004 */
+ u32 err_cnt; /* 0x3008 */
+ u32 max_fill; /* 0x300C */
+ u32 cf_param; /* 0x3010 */
+ u32 tx_test; /* 0x3014 */
+ u32 err; /* 0x3018 */
+ u32 err_int; /* 0x301C */
+ u32 bp_ctrl; /* 0x3020 */
+};
+
+/* END OF TXMAC REGISTER ADDRESS MAP */
+
+/* START OF RXMAC REGISTER ADDRESS MAP */
+
+/*
+ * structure for rxmac control reg in rxmac address map
+ * located at address 0x4000
+ *
+ * 31-7: reserved
+ * 6: rxmac_int_disable
+ * 5: async_disable
+ * 4: mif_disable
+ * 3: wol_disable
+ * 2: pkt_filter_disable
+ * 1: mcif_disable
+ * 0: rxmac_en
+ */
+
+/*
+ * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
+ * located at address 0x4004
+ * 31-16: crc
+ * 15-12: reserved
+ * 11: ignore_pp
+ * 10: ignore_mp
+ * 9: clr_intr
+ * 8: ignore_link_chg
+ * 7: ignore_uni
+ * 6: ignore_multi
+ * 5: ignore_broad
+ * 4-0: valid_crc 4-0
+ */
+
+/*
+ * structure for CRC 1 and CRC 2 reg in rxmac address map
+ * located at address 0x4008
+ *
+ * 31-16: crc2
+ * 15-0: crc1
+ */
+
+/*
+ * structure for CRC 3 and CRC 4 reg in rxmac address map
+ * located at address 0x400C
+ *
+ * 31-16: crc4
+ * 15-0: crc3
+ */
+
+/*
+ * structure for Wake On Lan Source Address Lo reg in rxmac address map
+ * located at address 0x4010
+ *
+ * 31-24: sa3
+ * 23-16: sa4
+ * 15-8: sa5
+ * 7-0: sa6
+ */
+
+#define ET_WOL_LO_SA3_SHIFT 24
+#define ET_WOL_LO_SA4_SHIFT 16
+#define ET_WOL_LO_SA5_SHIFT 8
+
+/*
+ * structure for Wake On Lan Source Address Hi reg in rxmac address map
+ * located at address 0x4014
+ *
+ * 31-16: reserved
+ * 15-8: sa1
+ * 7-0: sa2
+ */
+
+#define ET_WOL_HI_SA1_SHIFT 8
+
+/*
+ * structure for Wake On Lan mask reg in rxmac address map
+ * located at address 0x4018 - 0x4064
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for Unicast Paket Filter Address 1 reg in rxmac address map
+ * located at address 0x4068
+ *
+ * 31-24: addr1_3
+ * 23-16: addr1_4
+ * 15-8: addr1_5
+ * 7-0: addr1_6
+ */
+
+#define ET_UNI_PF_ADDR1_3_SHIFT 24
+#define ET_UNI_PF_ADDR1_4_SHIFT 16
+#define ET_UNI_PF_ADDR1_5_SHIFT 8
+
+/*
+ * structure for Unicast Paket Filter Address 2 reg in rxmac address map
+ * located at address 0x406C
+ *
+ * 31-24: addr2_3
+ * 23-16: addr2_4
+ * 15-8: addr2_5
+ * 7-0: addr2_6
+ */
+
+#define ET_UNI_PF_ADDR2_3_SHIFT 24
+#define ET_UNI_PF_ADDR2_4_SHIFT 16
+#define ET_UNI_PF_ADDR2_5_SHIFT 8
+
+/*
+ * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
+ * located at address 0x4070
+ *
+ * 31-24: addr2_1
+ * 23-16: addr2_2
+ * 15-8: addr1_1
+ * 7-0: addr1_2
+ */
+
+#define ET_UNI_PF_ADDR2_1_SHIFT 24
+#define ET_UNI_PF_ADDR2_2_SHIFT 16
+#define ET_UNI_PF_ADDR1_1_SHIFT 8
+
+
+/*
+ * structure for Multicast Hash reg in rxmac address map
+ * located at address 0x4074 - 0x4080
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for Packet Filter Control reg in rxmac address map
+ * located at address 0x4084
+ *
+ * 31-23: unused
+ * 22-16: min_pkt_size
+ * 15-4: unused
+ * 3: filter_frag_en
+ * 2: filter_uni_en
+ * 1: filter_multi_en
+ * 0: filter_broad_en
+ */
+
+/*
+ * structure for Memory Controller Interface Control Max Segment reg in rxmac
+ * address map. Located at address 0x4088
+ *
+ * 31-10: reserved
+ * 9-2: max_size
+ * 1: fc_en
+ * 0: seg_en
+ */
+
+/*
+ * structure for Memory Controller Interface Water Mark reg in rxmac address
+ * map. Located at address 0x408C
+ *
+ * 31-26: unused
+ * 25-16: mark_hi
+ * 15-10: unused
+ * 9-0: mark_lo
+ */
+
+/*
+ * structure for Rx Queue Dialog reg in rxmac address map.
+ * located at address 0x4090
+ *
+ * 31-26: reserved
+ * 25-16: rd_ptr
+ * 15-10: reserved
+ * 9-0: wr_ptr
+ */
+
+/*
+ * structure for space available reg in rxmac address map.
+ * located at address 0x4094
+ *
+ * 31-17: reserved
+ * 16: space_avail_en
+ * 15-10: reserved
+ * 9-0: space_avail
+ */
+
+/*
+ * structure for management interface reg in rxmac address map.
+ * located at address 0x4098
+ *
+ * 31-18: reserved
+ * 17: drop_pkt_en
+ * 16-0: drop_pkt_mask
+ */
+
+/*
+ * structure for Error reg in rxmac address map.
+ * located at address 0x409C
+ *
+ * 31-4: unused
+ * 3: mif
+ * 2: async
+ * 1: pkt_filter
+ * 0: mcif
+ */
+
+/*
+ * Rx MAC Module of JAGCore Address Mapping
+ */
+struct rxmac_regs { /* Location: */
+ u32 ctrl; /* 0x4000 */
+ u32 crc0; /* 0x4004 */
+ u32 crc12; /* 0x4008 */
+ u32 crc34; /* 0x400C */
+ u32 sa_lo; /* 0x4010 */
+ u32 sa_hi; /* 0x4014 */
+ u32 mask0_word0; /* 0x4018 */
+ u32 mask0_word1; /* 0x401C */
+ u32 mask0_word2; /* 0x4020 */
+ u32 mask0_word3; /* 0x4024 */
+ u32 mask1_word0; /* 0x4028 */
+ u32 mask1_word1; /* 0x402C */
+ u32 mask1_word2; /* 0x4030 */
+ u32 mask1_word3; /* 0x4034 */
+ u32 mask2_word0; /* 0x4038 */
+ u32 mask2_word1; /* 0x403C */
+ u32 mask2_word2; /* 0x4040 */
+ u32 mask2_word3; /* 0x4044 */
+ u32 mask3_word0; /* 0x4048 */
+ u32 mask3_word1; /* 0x404C */
+ u32 mask3_word2; /* 0x4050 */
+ u32 mask3_word3; /* 0x4054 */
+ u32 mask4_word0; /* 0x4058 */
+ u32 mask4_word1; /* 0x405C */
+ u32 mask4_word2; /* 0x4060 */
+ u32 mask4_word3; /* 0x4064 */
+ u32 uni_pf_addr1; /* 0x4068 */
+ u32 uni_pf_addr2; /* 0x406C */
+ u32 uni_pf_addr3; /* 0x4070 */
+ u32 multi_hash1; /* 0x4074 */
+ u32 multi_hash2; /* 0x4078 */
+ u32 multi_hash3; /* 0x407C */
+ u32 multi_hash4; /* 0x4080 */
+ u32 pf_ctrl; /* 0x4084 */
+ u32 mcif_ctrl_max_seg; /* 0x4088 */
+ u32 mcif_water_mark; /* 0x408C */
+ u32 rxq_diag; /* 0x4090 */
+ u32 space_avail; /* 0x4094 */
+
+ u32 mif_ctrl; /* 0x4098 */
+ u32 err_reg; /* 0x409C */
+};
+
+/* END OF RXMAC REGISTER ADDRESS MAP */
+
+
+/* START OF MAC REGISTER ADDRESS MAP */
+
+/*
+ * structure for configuration #1 reg in mac address map.
+ * located at address 0x5000
+ *
+ * 31: soft reset
+ * 30: sim reset
+ * 29-20: reserved
+ * 19: reset rx mc
+ * 18: reset tx mc
+ * 17: reset rx func
+ * 16: reset tx fnc
+ * 15-9: reserved
+ * 8: loopback
+ * 7-6: reserved
+ * 5: rx flow
+ * 4: tx flow
+ * 3: syncd rx en
+ * 2: rx enable
+ * 1: syncd tx en
+ * 0: tx enable
+ */
+
+#define CFG1_LOOPBACK 0x00000100
+#define CFG1_RX_FLOW 0x00000020
+#define CFG1_TX_FLOW 0x00000010
+#define CFG1_RX_ENABLE 0x00000004
+#define CFG1_TX_ENABLE 0x00000001
+#define CFG1_WAIT 0x0000000A /* RX & TX syncd */
+
+/*
+ * structure for configuration #2 reg in mac address map.
+ * located at address 0x5004
+ * 31-16: reserved
+ * 15-12: preamble
+ * 11-10: reserved
+ * 9-8: if mode
+ * 7-6: reserved
+ * 5: huge frame
+ * 4: length check
+ * 3: undefined
+ * 2: pad crc
+ * 1: crc enable
+ * 0: full duplex
+ */
+
+
+/*
+ * structure for Interpacket gap reg in mac address map.
+ * located at address 0x5008
+ *
+ * 31: reserved
+ * 30-24: non B2B ipg 1
+ * 23: undefined
+ * 22-16: non B2B ipg 2
+ * 15-8: Min ifg enforce
+ * 7-0: B2B ipg
+ *
+ * structure for half duplex reg in mac address map.
+ * located at address 0x500C
+ * 31-24: reserved
+ * 23-20: Alt BEB trunc
+ * 19: Alt BEB enable
+ * 18: BP no backoff
+ * 17: no backoff
+ * 16: excess defer
+ * 15-12: re-xmit max
+ * 11-10: reserved
+ * 9-0: collision window
+ */
+
+/*
+ * structure for Maximum Frame Length reg in mac address map.
+ * located at address 0x5010: bits 0-15 hold the length.
+ */
+
+/*
+ * structure for Reserve 1 reg in mac address map.
+ * located at address 0x5014 - 0x5018
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for Test reg in mac address map.
+ * located at address 0x501C
+ * test: bits 0-2, rest unused
+ */
+
+/*
+ * structure for MII Management Configuration reg in mac address map.
+ * located at address 0x5020
+ *
+ * 31: reset MII mgmt
+ * 30-6: unused
+ * 5: scan auto increment
+ * 4: preamble suppress
+ * 3: undefined
+ * 2-0: mgmt clock reset
+ */
+
+/*
+ * structure for MII Management Command reg in mac address map.
+ * located at address 0x5024
+ * bit 1: scan cycle
+ * bit 0: read cycle
+ */
+
+/*
+ * structure for MII Management Address reg in mac address map.
+ * located at address 0x5028
+ * 31-13: reserved
+ * 12-8: phy addr
+ * 7-5: reserved
+ * 4-0: register
+ */
+
+#define MII_ADDR(phy, reg) ((phy) << 8 | (reg))
+
+/*
+ * structure for MII Management Control reg in mac address map.
+ * located at address 0x502C
+ * 31-16: reserved
+ * 15-0: phy control
+ */
+
+/*
+ * structure for MII Management Status reg in mac address map.
+ * located at address 0x5030
+ * 31-16: reserved
+ * 15-0: phy control
+ */
+
+/*
+ * structure for MII Management Indicators reg in mac address map.
+ * located at address 0x5034
+ * 31-3: reserved
+ * 2: not valid
+ * 1: scanning
+ * 0: busy
+ */
+
+#define MGMT_BUSY 0x00000001 /* busy */
+#define MGMT_WAIT 0x00000005 /* busy | not valid */
+
+/*
+ * structure for Interface Control reg in mac address map.
+ * located at address 0x5038
+ *
+ * 31: reset if module
+ * 30-28: reserved
+ * 27: tbi mode
+ * 26: ghd mode
+ * 25: lhd mode
+ * 24: phy mode
+ * 23: reset per mii
+ * 22-17: reserved
+ * 16: speed
+ * 15: reset pe100x
+ * 14-11: reserved
+ * 10: force quiet
+ * 9: no cipher
+ * 8: disable link fail
+ * 7: reset gpsi
+ * 6-1: reserved
+ * 0: enable jabber protection
+ */
+
+/*
+ * structure for Interface Status reg in mac address map.
+ * located at address 0x503C
+ *
+ * 31-10: reserved
+ * 9: excess_defer
+ * 8: clash
+ * 7: phy_jabber
+ * 6: phy_link_ok
+ * 5: phy_full_duplex
+ * 4: phy_speed
+ * 3: pe100x_link_fail
+ * 2: pe10t_loss_carrier
+ * 1: pe10t_sqe_error
+ * 0: pe10t_jabber
+ */
+
+/*
+ * structure for Mac Station Address, Part 1 reg in mac address map.
+ * located at address 0x5040
+ *
+ * 31-24: Octet6
+ * 23-16: Octet5
+ * 15-8: Octet4
+ * 7-0: Octet3
+ */
+
+#define ET_MAC_STATION_ADDR1_OC6_SHIFT 24
+#define ET_MAC_STATION_ADDR1_OC5_SHIFT 16
+#define ET_MAC_STATION_ADDR1_OC4_SHIFT 8
+
+/*
+ * structure for Mac Station Address, Part 2 reg in mac address map.
+ * located at address 0x5044
+ *
+ * 31-24: Octet2
+ * 23-16: Octet1
+ * 15-0: reserved
+ */
+
+#define ET_MAC_STATION_ADDR2_OC2_SHIFT 24
+#define ET_MAC_STATION_ADDR2_OC1_SHIFT 16
+
+/*
+ * MAC Module of JAGCore Address Mapping
+ */
+struct mac_regs { /* Location: */
+ u32 cfg1; /* 0x5000 */
+ u32 cfg2; /* 0x5004 */
+ u32 ipg; /* 0x5008 */
+ u32 hfdp; /* 0x500C */
+ u32 max_fm_len; /* 0x5010 */
+ u32 rsv1; /* 0x5014 */
+ u32 rsv2; /* 0x5018 */
+ u32 mac_test; /* 0x501C */
+ u32 mii_mgmt_cfg; /* 0x5020 */
+ u32 mii_mgmt_cmd; /* 0x5024 */
+ u32 mii_mgmt_addr; /* 0x5028 */
+ u32 mii_mgmt_ctrl; /* 0x502C */
+ u32 mii_mgmt_stat; /* 0x5030 */
+ u32 mii_mgmt_indicator; /* 0x5034 */
+ u32 if_ctrl; /* 0x5038 */
+ u32 if_stat; /* 0x503C */
+ u32 station_addr_1; /* 0x5040 */
+ u32 station_addr_2; /* 0x5044 */
+};
+
+/* END OF MAC REGISTER ADDRESS MAP */
+
+/* START OF MAC STAT REGISTER ADDRESS MAP */
+
+/*
+ * structure for Carry Register One and it's Mask Register reg located in mac
+ * stat address map address 0x6130 and 0x6138.
+ *
+ * 31: tr64
+ * 30: tr127
+ * 29: tr255
+ * 28: tr511
+ * 27: tr1k
+ * 26: trmax
+ * 25: trmgv
+ * 24-17: unused
+ * 16: rbyt
+ * 15: rpkt
+ * 14: rfcs
+ * 13: rmca
+ * 12: rbca
+ * 11: rxcf
+ * 10: rxpf
+ * 9: rxuo
+ * 8: raln
+ * 7: rflr
+ * 6: rcde
+ * 5: rcse
+ * 4: rund
+ * 3: rovr
+ * 2: rfrg
+ * 1: rjbr
+ * 0: rdrp
+ */
+
+/*
+ * structure for Carry Register Two Mask Register reg in mac stat address map.
+ * located at address 0x613C
+ *
+ * 31-20: unused
+ * 19: tjbr
+ * 18: tfcs
+ * 17: txcf
+ * 16: tovr
+ * 15: tund
+ * 14: trfg
+ * 13: tbyt
+ * 12: tpkt
+ * 11: tmca
+ * 10: tbca
+ * 9: txpf
+ * 8: tdfr
+ * 7: tedf
+ * 6: tscl
+ * 5: tmcl
+ * 4: tlcl
+ * 3: txcl
+ * 2: tncl
+ * 1: tpfh
+ * 0: tdrp
+ */
+
+/*
+ * MAC STATS Module of JAGCore Address Mapping
+ */
+struct macstat_regs { /* Location: */
+ u32 pad[32]; /* 0x6000 - 607C */
+
+ /* Tx/Rx 0-64 Byte Frame Counter */
+ u32 txrx_0_64_byte_frames; /* 0x6080 */
+
+ /* Tx/Rx 65-127 Byte Frame Counter */
+ u32 txrx_65_127_byte_frames; /* 0x6084 */
+
+ /* Tx/Rx 128-255 Byte Frame Counter */
+ u32 txrx_128_255_byte_frames; /* 0x6088 */
+
+ /* Tx/Rx 256-511 Byte Frame Counter */
+ u32 txrx_256_511_byte_frames; /* 0x608C */
+
+ /* Tx/Rx 512-1023 Byte Frame Counter */
+ u32 txrx_512_1023_byte_frames; /* 0x6090 */
+
+ /* Tx/Rx 1024-1518 Byte Frame Counter */
+ u32 txrx_1024_1518_byte_frames; /* 0x6094 */
+
+ /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
+ u32 txrx_1519_1522_gvln_frames; /* 0x6098 */
+
+ /* Rx Byte Counter */
+ u32 rx_bytes; /* 0x609C */
+
+ /* Rx Packet Counter */
+ u32 rx_packets; /* 0x60A0 */
+
+ /* Rx FCS Error Counter */
+ u32 rx_fcs_errs; /* 0x60A4 */
+
+ /* Rx Multicast Packet Counter */
+ u32 rx_multicast_packets; /* 0x60A8 */
+
+ /* Rx Broadcast Packet Counter */
+ u32 rx_broadcast_packets; /* 0x60AC */
+
+ /* Rx Control Frame Packet Counter */
+ u32 rx_control_frames; /* 0x60B0 */
+
+ /* Rx Pause Frame Packet Counter */
+ u32 rx_pause_frames; /* 0x60B4 */
+
+ /* Rx Unknown OP Code Counter */
+ u32 rx_unknown_opcodes; /* 0x60B8 */
+
+ /* Rx Alignment Error Counter */
+ u32 rx_align_errs; /* 0x60BC */
+
+ /* Rx Frame Length Error Counter */
+ u32 rx_frame_len_errs; /* 0x60C0 */
+
+ /* Rx Code Error Counter */
+ u32 rx_code_errs; /* 0x60C4 */
+
+ /* Rx Carrier Sense Error Counter */
+ u32 rx_carrier_sense_errs; /* 0x60C8 */
+
+ /* Rx Undersize Packet Counter */
+ u32 rx_undersize_packets; /* 0x60CC */
+
+ /* Rx Oversize Packet Counter */
+ u32 rx_oversize_packets; /* 0x60D0 */
+
+ /* Rx Fragment Counter */
+ u32 rx_fragment_packets; /* 0x60D4 */
+
+ /* Rx Jabber Counter */
+ u32 rx_jabbers; /* 0x60D8 */
+
+ /* Rx Drop */
+ u32 rx_drops; /* 0x60DC */
+
+ /* Tx Byte Counter */
+ u32 tx_bytes; /* 0x60E0 */
+
+ /* Tx Packet Counter */
+ u32 tx_packets; /* 0x60E4 */
+
+ /* Tx Multicast Packet Counter */
+ u32 tx_multicast_packets; /* 0x60E8 */
+
+ /* Tx Broadcast Packet Counter */
+ u32 tx_broadcast_packets; /* 0x60EC */
+
+ /* Tx Pause Control Frame Counter */
+ u32 tx_pause_frames; /* 0x60F0 */
+
+ /* Tx Deferral Packet Counter */
+ u32 tx_deferred; /* 0x60F4 */
+
+ /* Tx Excessive Deferral Packet Counter */
+ u32 tx_excessive_deferred; /* 0x60F8 */
+
+ /* Tx Single Collision Packet Counter */
+ u32 tx_single_collisions; /* 0x60FC */
+
+ /* Tx Multiple Collision Packet Counter */
+ u32 tx_multiple_collisions; /* 0x6100 */
+
+ /* Tx Late Collision Packet Counter */
+ u32 tx_late_collisions; /* 0x6104 */
+
+ /* Tx Excessive Collision Packet Counter */
+ u32 tx_excessive_collisions; /* 0x6108 */
+
+ /* Tx Total Collision Packet Counter */
+ u32 tx_total_collisions; /* 0x610C */
+
+ /* Tx Pause Frame Honored Counter */
+ u32 tx_pause_honored_frames; /* 0x6110 */
+
+ /* Tx Drop Frame Counter */
+ u32 tx_drops; /* 0x6114 */
+
+ /* Tx Jabber Frame Counter */
+ u32 tx_jabbers; /* 0x6118 */
+
+ /* Tx FCS Error Counter */
+ u32 tx_fcs_errs; /* 0x611C */
+
+ /* Tx Control Frame Counter */
+ u32 tx_control_frames; /* 0x6120 */
+
+ /* Tx Oversize Frame Counter */
+ u32 tx_oversize_frames; /* 0x6124 */
+
+ /* Tx Undersize Frame Counter */
+ u32 tx_undersize_frames; /* 0x6128 */
+
+ /* Tx Fragments Frame Counter */
+ u32 tx_fragments; /* 0x612C */
+
+ /* Carry Register One Register */
+ u32 carry_reg1; /* 0x6130 */
+
+ /* Carry Register Two Register */
+ u32 carry_reg2; /* 0x6134 */
+
+ /* Carry Register One Mask Register */
+ u32 carry_reg1_mask; /* 0x6138 */
+
+ /* Carry Register Two Mask Register */
+ u32 carry_reg2_mask; /* 0x613C */
+};
+
+/* END OF MAC STAT REGISTER ADDRESS MAP */
+
+/* START OF MMC REGISTER ADDRESS MAP */
+
+/*
+ * Main Memory Controller Control reg in mmc address map.
+ * located at address 0x7000
+ */
+
+#define ET_MMC_ENABLE 1
+#define ET_MMC_ARB_DISABLE 2
+#define ET_MMC_RXMAC_DISABLE 4
+#define ET_MMC_TXMAC_DISABLE 8
+#define ET_MMC_TXDMA_DISABLE 16
+#define ET_MMC_RXDMA_DISABLE 32
+#define ET_MMC_FORCE_CE 64
+
+/*
+ * Main Memory Controller Host Memory Access Address reg in mmc
+ * address map. Located at address 0x7004. Top 16 bits hold the address bits
+ */
+
+#define ET_SRAM_REQ_ACCESS 1
+#define ET_SRAM_WR_ACCESS 2
+#define ET_SRAM_IS_CTRL 4
+
+/*
+ * structure for Main Memory Controller Host Memory Access Data reg in mmc
+ * address map. Located at address 0x7008 - 0x7014
+ * Defined earlier (u32)
+ */
+
+/*
+ * Memory Control Module of JAGCore Address Mapping
+ */
+struct mmc_regs { /* Location: */
+ u32 mmc_ctrl; /* 0x7000 */
+ u32 sram_access; /* 0x7004 */
+ u32 sram_word1; /* 0x7008 */
+ u32 sram_word2; /* 0x700C */
+ u32 sram_word3; /* 0x7010 */
+ u32 sram_word4; /* 0x7014 */
+};
+
+/* END OF MMC REGISTER ADDRESS MAP */
+
+
+/*
+ * JAGCore Address Mapping
+ */
+struct address_map {
+ struct global_regs global;
+ /* unused section of global address map */
+ u8 unused_global[4096 - sizeof(struct global_regs)];
+ struct txdma_regs txdma;
+ /* unused section of txdma address map */
+ u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
+ struct rxdma_regs rxdma;
+ /* unused section of rxdma address map */
+ u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
+ struct txmac_regs txmac;
+ /* unused section of txmac address map */
+ u8 unused_txmac[4096 - sizeof(struct txmac_regs)];
+ struct rxmac_regs rxmac;
+ /* unused section of rxmac address map */
+ u8 unused_rxmac[4096 - sizeof(struct rxmac_regs)];
+ struct mac_regs mac;
+ /* unused section of mac address map */
+ u8 unused_mac[4096 - sizeof(struct mac_regs)];
+ struct macstat_regs macstat;
+ /* unused section of mac stat address map */
+ u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
+ struct mmc_regs mmc;
+ /* unused section of mmc address map */
+ u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
+ /* unused section of address map */
+ u8 unused_[1015808];
+
+ u8 unused_exp_rom[4096]; /* MGS-size TBD */
+ u8 unused__[524288]; /* unused section of address map */
+};
diff --git a/drivers/staging/et131x/et131x_adapter.h b/drivers/staging/et131x/et131x_adapter.h
index b062e6d..74efdb0 100644
--- a/drivers/staging/et131x/et131x_adapter.h
+++ b/drivers/staging/et131x/et131x_adapter.h
@@ -61,7 +61,6 @@
#ifndef __ET131X_ADAPTER_H__
#define __ET131X_ADAPTER_H__
-#include "et1310_address_map.h"
#include "et1310_tx.h"
#include "et1310_rx.h"
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: move et1310_phy.h contents into et131x.h
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
2011-10-19 23:00 ` staging: et131x: Move non-register defines " Mark Einon
2011-10-19 23:00 ` staging: et131x: move et1310_address_map.h contents into et131x.h Mark Einon
@ 2011-10-19 23:00 ` Mark Einon
2011-10-19 23:00 ` staging: et131x: move et131x_adapter.h contents into et131x.c Mark Einon
` (13 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:00 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
Move et1310_phy.h register defines into et131x.h and delete
et1310_phy.h
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/et1310_phy.h | 290 -----------------------------------
drivers/staging/et131x/et131x.c | 1 -
drivers/staging/et131x/et131x.h | 227 +++++++++++++++++++++++++++
3 files changed, 227 insertions(+), 291 deletions(-)
delete mode 100644 drivers/staging/et131x/et1310_phy.h
diff --git a/drivers/staging/et131x/et1310_phy.h b/drivers/staging/et131x/et1310_phy.h
deleted file mode 100644
index feb5761..0000000
--- a/drivers/staging/et131x/et1310_phy.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * Agere Systems Inc.
- * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- * http://www.agere.com
- *
- * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
- *
- *------------------------------------------------------------------------------
- *
- * et1310_phy.h - Defines, structs, enums, prototypes, etc. pertaining to the
- * PHY.
- *
- *------------------------------------------------------------------------------
- *
- * SOFTWARE LICENSE
- *
- * This software is provided subject to the following terms and conditions,
- * which you should read carefully before using the software. Using this
- * software indicates your acceptance of these terms and conditions. If you do
- * not agree with these terms and conditions, do not use the software.
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- *
- * Redistribution and use in source or binary forms, with or without
- * modifications, are permitted provided that the following conditions are met:
- *
- * . Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following Disclaimer as comments in the code as
- * well as in the documentation and/or other materials provided with the
- * distribution.
- *
- * . Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following Disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * . Neither the name of Agere Systems Inc. nor the names of the contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * Disclaimer
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
- * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
- * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGE.
- *
- */
-
-#ifndef _ET1310_PHY_H_
-#define _ET1310_PHY_H_
-
-/*
- * Defines for generic MII registers 0x00 -> 0x0F can be found in
- * include/linux/mii.h
- */
-
-/* some defines for modem registers that seem to be 'reserved' */
-#define PHY_INDEX_REG 0x10
-#define PHY_DATA_REG 0x11
-#define PHY_MPHY_CONTROL_REG 0x12
-
-/* defines for specified registers */
-#define PHY_LOOPBACK_CONTROL 0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
- /* TRU_VMI_LOOPBACK_CONTROL_2_REG 20 */
-#define PHY_REGISTER_MGMT_CONTROL 0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG 21 */
-#define PHY_CONFIG 0x16 /* TRU_VMI_CONFIGURATION_REG 22 */
-#define PHY_PHY_CONTROL 0x17 /* TRU_VMI_PHY_CONTROL_REG 23 */
-#define PHY_INTERRUPT_MASK 0x18 /* TRU_VMI_INTERRUPT_MASK_REG 24 */
-#define PHY_INTERRUPT_STATUS 0x19 /* TRU_VMI_INTERRUPT_STATUS_REG 25 */
-#define PHY_PHY_STATUS 0x1A /* TRU_VMI_PHY_STATUS_REG 26 */
-#define PHY_LED_1 0x1B /* TRU_VMI_LED_CONTROL_1_REG 27 */
-#define PHY_LED_2 0x1C /* TRU_VMI_LED_CONTROL_2_REG 28 */
- /* TRU_VMI_LINK_CONTROL_REG 29 */
- /* TRU_VMI_TIMING_CONTROL_REG */
-
-/* MI Register 10: Gigabit basic mode status reg(Reg 0x0A) */
-#define ET_1000BT_MSTR_SLV 0x4000
-
-/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
-
-/* MI Register 19: Loopback Control Reg(0x13)
- * 15: mii_en
- * 14: pcs_en
- * 13: pmd_en
- * 12: all_digital_en
- * 11: replica_en
- * 10: line_driver_en
- * 9-0: reserved
- */
-
-/* MI Register 20: Reserved Reg(0x14) */
-
-/* MI Register 21: Management Interface Control Reg(0x15)
- * 15-11: reserved
- * 10-4: mi_error_count
- * 3: reserved
- * 2: ignore_10g_fr
- * 1: reserved
- * 0: preamble_supress_en
- */
-
-/* MI Register 22: PHY Configuration Reg(0x16)
- * 15: crs_tx_en
- * 14: reserved
- * 13-12: tx_fifo_depth
- * 11-10: speed_downshift
- * 9: pbi_detect
- * 8: tbi_rate
- * 7: alternate_np
- * 6: group_mdio_en
- * 5: tx_clock_en
- * 4: sys_clock_en
- * 3: reserved
- * 2-0: mac_if_mode
- */
-
-#define ET_PHY_CONFIG_TX_FIFO_DEPTH 0x3000
-
-#define ET_PHY_CONFIG_FIFO_DEPTH_8 0x0000
-#define ET_PHY_CONFIG_FIFO_DEPTH_16 0x1000
-#define ET_PHY_CONFIG_FIFO_DEPTH_32 0x2000
-#define ET_PHY_CONFIG_FIFO_DEPTH_64 0x3000
-
-/* MI Register 23: PHY CONTROL Reg(0x17)
- * 15: reserved
- * 14: tdr_en
- * 13: reserved
- * 12-11: downshift_attempts
- * 10-6: reserved
- * 5: jabber_10baseT
- * 4: sqe_10baseT
- * 3: tp_loopback_10baseT
- * 2: preamble_gen_en
- * 1: reserved
- * 0: force_int
- */
-
-/* MI Register 24: Interrupt Mask Reg(0x18)
- * 15-10: reserved
- * 9: mdio_sync_lost
- * 8: autoneg_status
- * 7: hi_bit_err
- * 6: np_rx
- * 5: err_counter_full
- * 4: fifo_over_underflow
- * 3: rx_status
- * 2: link_status
- * 1: automatic_speed
- * 0: int_en
- */
-
-#define ET_PHY_INT_MASK_AUTONEGSTAT 0x0100
-#define ET_PHY_INT_MASK_LINKSTAT 0x0004
-#define ET_PHY_INT_MASK_ENABLE 0x0001
-
-/* MI Register 25: Interrupt Status Reg(0x19)
- * 15-10: reserved
- * 9: mdio_sync_lost
- * 8: autoneg_status
- * 7: hi_bit_err
- * 6: np_rx
- * 5: err_counter_full
- * 4: fifo_over_underflow
- * 3: rx_status
- * 2: link_status
- * 1: automatic_speed
- * 0: int_en
- */
-
-/* MI Register 26: PHY Status Reg(0x1A)
- * 15: reserved
- * 14-13: autoneg_fault
- * 12: autoneg_status
- * 11: mdi_x_status
- * 10: polarity_status
- * 9-8: speed_status
- * 7: duplex_status
- * 6: link_status
- * 5: tx_status
- * 4: rx_status
- * 3: collision_status
- * 2: autoneg_en
- * 1: pause_en
- * 0: asymmetric_dir
- */
-#define ET_PHY_AUTONEG_STATUS 0x1000
-#define ET_PHY_POLARITY_STATUS 0x0400
-#define ET_PHY_SPEED_STATUS 0x0300
-#define ET_PHY_DUPLEX_STATUS 0x0080
-#define ET_PHY_LSTATUS 0x0040
-#define ET_PHY_AUTONEG_ENABLE 0x0020
-
-/* MI Register 27: LED Control Reg 1(0x1B)
- * 15-14: reserved
- * 13-12: led_dup_indicate
- * 11-10: led_10baseT
- * 9-8: led_collision
- * 7-4: reserved
- * 3-2: pulse_dur
- * 1: pulse_stretch1
- * 0: pulse_stretch0
- */
-
-/* MI Register 28: LED Control Reg 2(0x1C)
- * 15-12: led_link
- * 11-8: led_tx_rx
- * 7-4: led_100BaseTX
- * 3-0: led_1000BaseT
- */
-#define ET_LED2_LED_LINK 0xF000
-#define ET_LED2_LED_TXRX 0x0F00
-#define ET_LED2_LED_100TX 0x00F0
-#define ET_LED2_LED_1000T 0x000F
-
-/* defines for LED control reg 2 values */
-#define LED_VAL_1000BT 0x0
-#define LED_VAL_100BTX 0x1
-#define LED_VAL_10BT 0x2
-#define LED_VAL_1000BT_100BTX 0x3 /* 1000BT on, 100BTX blink */
-#define LED_VAL_LINKON 0x4
-#define LED_VAL_TX 0x5
-#define LED_VAL_RX 0x6
-#define LED_VAL_TXRX 0x7 /* TX or RX */
-#define LED_VAL_DUPLEXFULL 0x8
-#define LED_VAL_COLLISION 0x9
-#define LED_VAL_LINKON_ACTIVE 0xA /* Link on, activity blink */
-#define LED_VAL_LINKON_RECV 0xB /* Link on, receive blink */
-#define LED_VAL_DUPLEXFULL_COLLISION 0xC /* Duplex on, collision blink */
-#define LED_VAL_BLINK 0xD
-#define LED_VAL_ON 0xE
-#define LED_VAL_OFF 0xF
-
-#define LED_LINK_SHIFT 12
-#define LED_TXRX_SHIFT 8
-#define LED_100TX_SHIFT 4
-
-/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
-
-/* Defines for PHY access routines */
-
-/* Define bit operation flags */
-#define TRUEPHY_BIT_CLEAR 0
-#define TRUEPHY_BIT_SET 1
-#define TRUEPHY_BIT_READ 2
-
-/* Define read/write operation flags */
-#ifndef TRUEPHY_READ
-#define TRUEPHY_READ 0
-#define TRUEPHY_WRITE 1
-#define TRUEPHY_MASK 2
-#endif
-
-/* Define master/slave configuration values */
-#define TRUEPHY_CFG_SLAVE 0
-#define TRUEPHY_CFG_MASTER 1
-
-/* Define MDI/MDI-X settings */
-#define TRUEPHY_MDI 0
-#define TRUEPHY_MDIX 1
-#define TRUEPHY_AUTO_MDI_MDIX 2
-
-/* Define 10Base-T link polarities */
-#define TRUEPHY_POLARITY_NORMAL 0
-#define TRUEPHY_POLARITY_INVERTED 1
-
-/* Define auto-negotiation results */
-#define TRUEPHY_ANEG_NOT_COMPLETE 0
-#define TRUEPHY_ANEG_COMPLETE 1
-#define TRUEPHY_ANEG_DISABLED 2
-
-/* Define duplex advertisement flags */
-#define TRUEPHY_ADV_DUPLEX_NONE 0x00
-#define TRUEPHY_ADV_DUPLEX_FULL 0x01
-#define TRUEPHY_ADV_DUPLEX_HALF 0x02
-#define TRUEPHY_ADV_DUPLEX_BOTH \
- (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)
-
-#endif /* _ET1310_PHY_H_ */
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 60ff3bc..271ae31 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -83,7 +83,6 @@
#include <linux/random.h>
#include <linux/phy.h>
-#include "et1310_phy.h"
#include "et131x_adapter.h"
#include "et1310_tx.h"
#include "et1310_rx.h"
diff --git a/drivers/staging/et131x/et131x.h b/drivers/staging/et131x/et131x.h
index 8f61a72..84b274d 100644
--- a/drivers/staging/et131x/et131x.h
+++ b/drivers/staging/et131x/et131x.h
@@ -1447,3 +1447,230 @@ struct address_map {
u8 unused_exp_rom[4096]; /* MGS-size TBD */
u8 unused__[524288]; /* unused section of address map */
};
+
+/*
+ * Defines for generic MII registers 0x00 -> 0x0F can be found in
+ * include/linux/mii.h
+ */
+
+/* some defines for modem registers that seem to be 'reserved' */
+#define PHY_INDEX_REG 0x10
+#define PHY_DATA_REG 0x11
+#define PHY_MPHY_CONTROL_REG 0x12
+
+/* defines for specified registers */
+#define PHY_LOOPBACK_CONTROL 0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
+ /* TRU_VMI_LOOPBACK_CONTROL_2_REG 20 */
+#define PHY_REGISTER_MGMT_CONTROL 0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG 21 */
+#define PHY_CONFIG 0x16 /* TRU_VMI_CONFIGURATION_REG 22 */
+#define PHY_PHY_CONTROL 0x17 /* TRU_VMI_PHY_CONTROL_REG 23 */
+#define PHY_INTERRUPT_MASK 0x18 /* TRU_VMI_INTERRUPT_MASK_REG 24 */
+#define PHY_INTERRUPT_STATUS 0x19 /* TRU_VMI_INTERRUPT_STATUS_REG 25 */
+#define PHY_PHY_STATUS 0x1A /* TRU_VMI_PHY_STATUS_REG 26 */
+#define PHY_LED_1 0x1B /* TRU_VMI_LED_CONTROL_1_REG 27 */
+#define PHY_LED_2 0x1C /* TRU_VMI_LED_CONTROL_2_REG 28 */
+ /* TRU_VMI_LINK_CONTROL_REG 29 */
+ /* TRU_VMI_TIMING_CONTROL_REG */
+
+/* MI Register 10: Gigabit basic mode status reg(Reg 0x0A) */
+#define ET_1000BT_MSTR_SLV 0x4000
+
+/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
+
+/* MI Register 19: Loopback Control Reg(0x13)
+ * 15: mii_en
+ * 14: pcs_en
+ * 13: pmd_en
+ * 12: all_digital_en
+ * 11: replica_en
+ * 10: line_driver_en
+ * 9-0: reserved
+ */
+
+/* MI Register 20: Reserved Reg(0x14) */
+
+/* MI Register 21: Management Interface Control Reg(0x15)
+ * 15-11: reserved
+ * 10-4: mi_error_count
+ * 3: reserved
+ * 2: ignore_10g_fr
+ * 1: reserved
+ * 0: preamble_supress_en
+ */
+
+/* MI Register 22: PHY Configuration Reg(0x16)
+ * 15: crs_tx_en
+ * 14: reserved
+ * 13-12: tx_fifo_depth
+ * 11-10: speed_downshift
+ * 9: pbi_detect
+ * 8: tbi_rate
+ * 7: alternate_np
+ * 6: group_mdio_en
+ * 5: tx_clock_en
+ * 4: sys_clock_en
+ * 3: reserved
+ * 2-0: mac_if_mode
+ */
+
+#define ET_PHY_CONFIG_TX_FIFO_DEPTH 0x3000
+
+#define ET_PHY_CONFIG_FIFO_DEPTH_8 0x0000
+#define ET_PHY_CONFIG_FIFO_DEPTH_16 0x1000
+#define ET_PHY_CONFIG_FIFO_DEPTH_32 0x2000
+#define ET_PHY_CONFIG_FIFO_DEPTH_64 0x3000
+
+/* MI Register 23: PHY CONTROL Reg(0x17)
+ * 15: reserved
+ * 14: tdr_en
+ * 13: reserved
+ * 12-11: downshift_attempts
+ * 10-6: reserved
+ * 5: jabber_10baseT
+ * 4: sqe_10baseT
+ * 3: tp_loopback_10baseT
+ * 2: preamble_gen_en
+ * 1: reserved
+ * 0: force_int
+ */
+
+/* MI Register 24: Interrupt Mask Reg(0x18)
+ * 15-10: reserved
+ * 9: mdio_sync_lost
+ * 8: autoneg_status
+ * 7: hi_bit_err
+ * 6: np_rx
+ * 5: err_counter_full
+ * 4: fifo_over_underflow
+ * 3: rx_status
+ * 2: link_status
+ * 1: automatic_speed
+ * 0: int_en
+ */
+
+#define ET_PHY_INT_MASK_AUTONEGSTAT 0x0100
+#define ET_PHY_INT_MASK_LINKSTAT 0x0004
+#define ET_PHY_INT_MASK_ENABLE 0x0001
+
+/* MI Register 25: Interrupt Status Reg(0x19)
+ * 15-10: reserved
+ * 9: mdio_sync_lost
+ * 8: autoneg_status
+ * 7: hi_bit_err
+ * 6: np_rx
+ * 5: err_counter_full
+ * 4: fifo_over_underflow
+ * 3: rx_status
+ * 2: link_status
+ * 1: automatic_speed
+ * 0: int_en
+ */
+
+/* MI Register 26: PHY Status Reg(0x1A)
+ * 15: reserved
+ * 14-13: autoneg_fault
+ * 12: autoneg_status
+ * 11: mdi_x_status
+ * 10: polarity_status
+ * 9-8: speed_status
+ * 7: duplex_status
+ * 6: link_status
+ * 5: tx_status
+ * 4: rx_status
+ * 3: collision_status
+ * 2: autoneg_en
+ * 1: pause_en
+ * 0: asymmetric_dir
+ */
+#define ET_PHY_AUTONEG_STATUS 0x1000
+#define ET_PHY_POLARITY_STATUS 0x0400
+#define ET_PHY_SPEED_STATUS 0x0300
+#define ET_PHY_DUPLEX_STATUS 0x0080
+#define ET_PHY_LSTATUS 0x0040
+#define ET_PHY_AUTONEG_ENABLE 0x0020
+
+/* MI Register 27: LED Control Reg 1(0x1B)
+ * 15-14: reserved
+ * 13-12: led_dup_indicate
+ * 11-10: led_10baseT
+ * 9-8: led_collision
+ * 7-4: reserved
+ * 3-2: pulse_dur
+ * 1: pulse_stretch1
+ * 0: pulse_stretch0
+ */
+
+/* MI Register 28: LED Control Reg 2(0x1C)
+ * 15-12: led_link
+ * 11-8: led_tx_rx
+ * 7-4: led_100BaseTX
+ * 3-0: led_1000BaseT
+ */
+#define ET_LED2_LED_LINK 0xF000
+#define ET_LED2_LED_TXRX 0x0F00
+#define ET_LED2_LED_100TX 0x00F0
+#define ET_LED2_LED_1000T 0x000F
+
+/* defines for LED control reg 2 values */
+#define LED_VAL_1000BT 0x0
+#define LED_VAL_100BTX 0x1
+#define LED_VAL_10BT 0x2
+#define LED_VAL_1000BT_100BTX 0x3 /* 1000BT on, 100BTX blink */
+#define LED_VAL_LINKON 0x4
+#define LED_VAL_TX 0x5
+#define LED_VAL_RX 0x6
+#define LED_VAL_TXRX 0x7 /* TX or RX */
+#define LED_VAL_DUPLEXFULL 0x8
+#define LED_VAL_COLLISION 0x9
+#define LED_VAL_LINKON_ACTIVE 0xA /* Link on, activity blink */
+#define LED_VAL_LINKON_RECV 0xB /* Link on, receive blink */
+#define LED_VAL_DUPLEXFULL_COLLISION 0xC /* Duplex on, collision blink */
+#define LED_VAL_BLINK 0xD
+#define LED_VAL_ON 0xE
+#define LED_VAL_OFF 0xF
+
+#define LED_LINK_SHIFT 12
+#define LED_TXRX_SHIFT 8
+#define LED_100TX_SHIFT 4
+
+/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
+
+/* Defines for PHY access routines */
+
+/* Define bit operation flags */
+#define TRUEPHY_BIT_CLEAR 0
+#define TRUEPHY_BIT_SET 1
+#define TRUEPHY_BIT_READ 2
+
+/* Define read/write operation flags */
+#ifndef TRUEPHY_READ
+#define TRUEPHY_READ 0
+#define TRUEPHY_WRITE 1
+#define TRUEPHY_MASK 2
+#endif
+
+/* Define master/slave configuration values */
+#define TRUEPHY_CFG_SLAVE 0
+#define TRUEPHY_CFG_MASTER 1
+
+/* Define MDI/MDI-X settings */
+#define TRUEPHY_MDI 0
+#define TRUEPHY_MDIX 1
+#define TRUEPHY_AUTO_MDI_MDIX 2
+
+/* Define 10Base-T link polarities */
+#define TRUEPHY_POLARITY_NORMAL 0
+#define TRUEPHY_POLARITY_INVERTED 1
+
+/* Define auto-negotiation results */
+#define TRUEPHY_ANEG_NOT_COMPLETE 0
+#define TRUEPHY_ANEG_COMPLETE 1
+#define TRUEPHY_ANEG_DISABLED 2
+
+/* Define duplex advertisement flags */
+#define TRUEPHY_ADV_DUPLEX_NONE 0x00
+#define TRUEPHY_ADV_DUPLEX_FULL 0x01
+#define TRUEPHY_ADV_DUPLEX_HALF 0x02
+#define TRUEPHY_ADV_DUPLEX_BOTH \
+ (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)
+
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: move et131x_adapter.h contents into et131x.c
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
` (2 preceding siblings ...)
2011-10-19 23:00 ` staging: et131x: move et1310_phy.h " Mark Einon
@ 2011-10-19 23:00 ` Mark Einon
2011-10-19 23:00 ` staging: et131x: move et131x_defs.h " Mark Einon
` (12 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:00 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
Move et131x_adapter.h contents into et131x.c and delete et131x_adapter.h
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/et131x.c | 152 +++++++++++++++++++++-
drivers/staging/et131x/et131x_adapter.h | 217 -------------------------------
2 files changed, 151 insertions(+), 218 deletions(-)
delete mode 100644 drivers/staging/et131x/et131x_adapter.h
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 271ae31..e88c277 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -83,7 +83,6 @@
#include <linux/random.h>
#include <linux/phy.h>
-#include "et131x_adapter.h"
#include "et1310_tx.h"
#include "et1310_rx.h"
#include "et131x.h"
@@ -125,6 +124,157 @@ MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver "
#define INT_MASK_ENABLE 0xfffebf17
#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
+/* ADAPTER defines */
+/*
+ * Do not change these values: if changed, then change also in respective
+ * TXdma and Rxdma engines
+ */
+#define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
+#define NUM_TCB 64
+
+/*
+ * These values are all superseded by registry entries to facilitate tuning.
+ * Once the desired performance has been achieved, the optimal registry values
+ * should be re-populated to these #defines:
+ */
+#define NUM_TRAFFIC_CLASSES 1
+
+#define TX_ERROR_PERIOD 1000
+
+#define LO_MARK_PERCENT_FOR_PSR 15
+#define LO_MARK_PERCENT_FOR_RX 15
+
+/* RFD (Receive Frame Descriptor) */
+struct rfd {
+ struct list_head list_node;
+ struct sk_buff *skb;
+ u32 len; /* total size of receive frame */
+ u16 bufferindex;
+ u8 ringindex;
+};
+
+/* Flow Control */
+#define FLOW_BOTH 0
+#define FLOW_TXONLY 1
+#define FLOW_RXONLY 2
+#define FLOW_NONE 3
+
+/* Struct to define some device statistics */
+struct ce_stats {
+ /* MIB II variables
+ *
+ * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
+ * MUST have 32, then we'll need another way to perform atomic
+ * operations
+ */
+ u32 unicast_pkts_rcvd;
+ atomic_t unicast_pkts_xmtd;
+ u32 multicast_pkts_rcvd;
+ atomic_t multicast_pkts_xmtd;
+ u32 broadcast_pkts_rcvd;
+ atomic_t broadcast_pkts_xmtd;
+ u32 rcvd_pkts_dropped;
+
+ /* Tx Statistics. */
+ u32 tx_underflows;
+
+ u32 tx_collisions;
+ u32 tx_excessive_collisions;
+ u32 tx_first_collisions;
+ u32 tx_late_collisions;
+ u32 tx_max_pkt_errs;
+ u32 tx_deferred;
+
+ /* Rx Statistics. */
+ u32 rx_overflows;
+
+ u32 rx_length_errs;
+ u32 rx_align_errs;
+ u32 rx_crc_errs;
+ u32 rx_code_violations;
+ u32 rx_other_errs;
+
+ u32 synchronous_iterations;
+ u32 interrupt_status;
+};
+
+/* The private adapter structure */
+struct et131x_adapter {
+ struct net_device *netdev;
+ struct pci_dev *pdev;
+ struct mii_bus *mii_bus;
+ struct phy_device *phydev;
+ struct work_struct task;
+
+ /* Flags that indicate current state of the adapter */
+ u32 flags;
+
+ /* local link state, to determine if a state change has occurred */
+ int link;
+
+ /* Configuration */
+ u8 rom_addr[ETH_ALEN];
+ u8 addr[ETH_ALEN];
+ bool has_eeprom;
+ u8 eeprom_data[2];
+
+ /* Spinlocks */
+ spinlock_t lock;
+
+ spinlock_t tcb_send_qlock;
+ spinlock_t tcb_ready_qlock;
+ spinlock_t send_hw_lock;
+
+ spinlock_t rcv_lock;
+ spinlock_t rcv_pend_lock;
+ spinlock_t fbr_lock;
+
+ spinlock_t phy_lock;
+
+ /* Packet Filter and look ahead size */
+ u32 packet_filter;
+
+ /* multicast list */
+ u32 multicast_addr_count;
+ u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN];
+
+ /* Pointer to the device's PCI register space */
+ struct address_map __iomem *regs;
+
+ /* Registry parameters */
+ u8 wanted_flow; /* Flow we want for 802.3x flow control */
+ u32 registry_jumbo_packet; /* Max supported ethernet packet size */
+
+ /* Derived from the registry: */
+ u8 flowcontrol; /* flow control validated by the far-end */
+
+ /* Minimize init-time */
+ struct timer_list error_timer;
+
+ /* variable putting the phy into coma mode when boot up with no cable
+ * plugged in after 5 seconds
+ */
+ u8 boot_coma;
+
+ /* Next two used to save power information at power down. This
+ * information will be used during power up to set up parts of Power
+ * Management in JAGCore
+ */
+ u16 pdown_speed;
+ u8 pdown_duplex;
+
+ /* Tx Memory Variables */
+ struct tx_ring tx_ring;
+
+ /* Rx Memory Variables */
+ struct rx_ring rx_ring;
+
+ /* Stats */
+ struct ce_stats stats;
+
+ struct net_device_stats net_stats;
+};
+
void et131x_error_timer_handler(unsigned long data);
void et131x_enable_interrupts(struct et131x_adapter *adapter);
void et131x_disable_interrupts(struct et131x_adapter *adapter);
diff --git a/drivers/staging/et131x/et131x_adapter.h b/drivers/staging/et131x/et131x_adapter.h
deleted file mode 100644
index 74efdb0..0000000
--- a/drivers/staging/et131x/et131x_adapter.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * Agere Systems Inc.
- * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- * http://www.agere.com
- *
- * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
- *
- *------------------------------------------------------------------------------
- *
- * et131x_adapter.h - Header which includes the private adapter structure, along
- * with related support structures, macros, definitions, etc.
- *
- *------------------------------------------------------------------------------
- *
- * SOFTWARE LICENSE
- *
- * This software is provided subject to the following terms and conditions,
- * which you should read carefully before using the software. Using this
- * software indicates your acceptance of these terms and conditions. If you do
- * not agree with these terms and conditions, do not use the software.
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- *
- * Redistribution and use in source or binary forms, with or without
- * modifications, are permitted provided that the following conditions are met:
- *
- * . Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following Disclaimer as comments in the code as
- * well as in the documentation and/or other materials provided with the
- * distribution.
- *
- * . Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following Disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * . Neither the name of Agere Systems Inc. nor the names of the contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * Disclaimer
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
- * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
- * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGE.
- *
- */
-
-#ifndef __ET131X_ADAPTER_H__
-#define __ET131X_ADAPTER_H__
-
-#include "et1310_tx.h"
-#include "et1310_rx.h"
-
-/*
- * Do not change these values: if changed, then change also in respective
- * TXdma and Rxdma engines
- */
-#define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
-#define NUM_TCB 64
-
-/*
- * These values are all superseded by registry entries to facilitate tuning.
- * Once the desired performance has been achieved, the optimal registry values
- * should be re-populated to these #defines:
- */
-#define NUM_TRAFFIC_CLASSES 1
-
-#define TX_ERROR_PERIOD 1000
-
-#define LO_MARK_PERCENT_FOR_PSR 15
-#define LO_MARK_PERCENT_FOR_RX 15
-
-/* RFD (Receive Frame Descriptor) */
-struct rfd {
- struct list_head list_node;
- struct sk_buff *skb;
- u32 len; /* total size of receive frame */
- u16 bufferindex;
- u8 ringindex;
-};
-
-/* Flow Control */
-#define FLOW_BOTH 0
-#define FLOW_TXONLY 1
-#define FLOW_RXONLY 2
-#define FLOW_NONE 3
-
-/* Struct to define some device statistics */
-struct ce_stats {
- /* MIB II variables
- *
- * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
- * MUST have 32, then we'll need another way to perform atomic
- * operations
- */
- u32 unicast_pkts_rcvd;
- atomic_t unicast_pkts_xmtd;
- u32 multicast_pkts_rcvd;
- atomic_t multicast_pkts_xmtd;
- u32 broadcast_pkts_rcvd;
- atomic_t broadcast_pkts_xmtd;
- u32 rcvd_pkts_dropped;
-
- /* Tx Statistics. */
- u32 tx_underflows;
-
- u32 tx_collisions;
- u32 tx_excessive_collisions;
- u32 tx_first_collisions;
- u32 tx_late_collisions;
- u32 tx_max_pkt_errs;
- u32 tx_deferred;
-
- /* Rx Statistics. */
- u32 rx_overflows;
-
- u32 rx_length_errs;
- u32 rx_align_errs;
- u32 rx_crc_errs;
- u32 rx_code_violations;
- u32 rx_other_errs;
-
- u32 synchronous_iterations;
- u32 interrupt_status;
-};
-
-/* The private adapter structure */
-struct et131x_adapter {
- struct net_device *netdev;
- struct pci_dev *pdev;
- struct mii_bus *mii_bus;
- struct phy_device *phydev;
- struct work_struct task;
-
- /* Flags that indicate current state of the adapter */
- u32 flags;
-
- /* local link state, to determine if a state change has occurred */
- int link;
-
- /* Configuration */
- u8 rom_addr[ETH_ALEN];
- u8 addr[ETH_ALEN];
- bool has_eeprom;
- u8 eeprom_data[2];
-
- /* Spinlocks */
- spinlock_t lock;
-
- spinlock_t tcb_send_qlock;
- spinlock_t tcb_ready_qlock;
- spinlock_t send_hw_lock;
-
- spinlock_t rcv_lock;
- spinlock_t rcv_pend_lock;
- spinlock_t fbr_lock;
-
- spinlock_t phy_lock;
-
- /* Packet Filter and look ahead size */
- u32 packet_filter;
-
- /* multicast list */
- u32 multicast_addr_count;
- u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN];
-
- /* Pointer to the device's PCI register space */
- struct address_map __iomem *regs;
-
- /* Registry parameters */
- u8 wanted_flow; /* Flow we want for 802.3x flow control */
- u32 registry_jumbo_packet; /* Max supported ethernet packet size */
-
- /* Derived from the registry: */
- u8 flowcontrol; /* flow control validated by the far-end */
-
- /* Minimize init-time */
- struct timer_list error_timer;
-
- /* variable putting the phy into coma mode when boot up with no cable
- * plugged in after 5 seconds
- */
- u8 boot_coma;
-
- /* Next two used to save power information at power down. This
- * information will be used during power up to set up parts of Power
- * Management in JAGCore
- */
- u16 pdown_speed;
- u8 pdown_duplex;
-
- /* Tx Memory Variables */
- struct tx_ring tx_ring;
-
- /* Rx Memory Variables */
- struct rx_ring rx_ring;
-
- /* Stats */
- struct ce_stats stats;
-
- struct net_device_stats net_stats;
-};
-
-#endif /* __ET131X_ADAPTER_H__ */
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: move et131x_defs.h contents into et131x.c
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
` (3 preceding siblings ...)
2011-10-19 23:00 ` staging: et131x: move et131x_adapter.h contents into et131x.c Mark Einon
@ 2011-10-19 23:00 ` Mark Einon
2011-10-19 23:00 ` staging: et131x: move et1310_rx.h " Mark Einon
` (11 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:00 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
Move et131x_defs.h contents into et131x.c and delete et131x_defs.h
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/et131x.c | 66 +++++++++++++++++-
drivers/staging/et131x/et131x_defs.h | 128 ----------------------------------
2 files changed, 64 insertions(+), 130 deletions(-)
delete mode 100644 drivers/staging/et131x/et131x_defs.h
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index e88c277..402ab7f 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -53,8 +53,6 @@
*
*/
-#include "et131x_defs.h"
-
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/module.h>
@@ -124,6 +122,70 @@ MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver "
#define INT_MASK_ENABLE 0xfffebf17
#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
+/* General defines */
+/* Packet and header sizes */
+#define NIC_MIN_PACKET_SIZE 60
+
+/* Multicast list size */
+#define NIC_MAX_MCAST_LIST 128
+
+/* Supported Filters */
+#define ET131X_PACKET_TYPE_DIRECTED 0x0001
+#define ET131X_PACKET_TYPE_MULTICAST 0x0002
+#define ET131X_PACKET_TYPE_BROADCAST 0x0004
+#define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
+#define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
+
+/* Tx Timeout */
+#define ET131X_TX_TIMEOUT (1 * HZ)
+#define NIC_SEND_HANG_THRESHOLD 0
+
+/* MP_TCB flags */
+#define fMP_DEST_MULTI 0x00000001
+#define fMP_DEST_BROAD 0x00000002
+
+/* MP_ADAPTER flags */
+#define fMP_ADAPTER_RECV_LOOKASIDE 0x00000004
+#define fMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
+#define fMP_ADAPTER_SECONDARY 0x00000010
+
+/* MP_SHARED flags */
+#define fMP_ADAPTER_SHUTDOWN 0x00100000
+#define fMP_ADAPTER_LOWER_POWER 0x00200000
+
+#define fMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
+#define fMP_ADAPTER_RESET_IN_PROGRESS 0x01000000
+#define fMP_ADAPTER_NO_CABLE 0x02000000
+#define fMP_ADAPTER_HARDWARE_ERROR 0x04000000
+#define fMP_ADAPTER_REMOVE_IN_PROGRESS 0x08000000
+#define fMP_ADAPTER_HALT_IN_PROGRESS 0x10000000
+
+#define fMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
+#define fMP_ADAPTER_NOT_READY_MASK 0x3ff00000
+
+/* Some offsets in PCI config space that are actually used. */
+#define ET1310_PCI_MAX_PYLD 0x4C
+#define ET1310_PCI_MAC_ADDRESS 0xA4
+#define ET1310_PCI_EEPROM_STATUS 0xB2
+#define ET1310_PCI_ACK_NACK 0xC0
+#define ET1310_PCI_REPLAY 0xC2
+#define ET1310_PCI_L0L1LATENCY 0xCF
+
+/* PCI Vendor/Product IDs */
+#define ET131X_PCI_VENDOR_ID 0x11C1 /* Agere Systems */
+#define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
+#define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
+
+/* Define order of magnitude converter */
+#define NANO_IN_A_MICRO 1000
+
+#define PARM_RX_NUM_BUFS_DEF 4
+#define PARM_RX_TIME_INT_DEF 10
+#define PARM_RX_MEM_END_DEF 0x2bc
+#define PARM_TX_TIME_INT_DEF 40
+#define PARM_TX_NUM_BUFS_DEF 4
+#define PARM_DMA_CACHE_DEF 0
+
/* ADAPTER defines */
/*
* Do not change these values: if changed, then change also in respective
diff --git a/drivers/staging/et131x/et131x_defs.h b/drivers/staging/et131x/et131x_defs.h
deleted file mode 100644
index 872a5af..0000000
--- a/drivers/staging/et131x/et131x_defs.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Agere Systems Inc.
- * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- * http://www.agere.com
- *
- * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
- *
- *------------------------------------------------------------------------------
- *
- * et131x_defs.h - Defines, structs, enums, prototypes, etc. to assist with OS
- * compatibility
- *
- *------------------------------------------------------------------------------
- *
- * SOFTWARE LICENSE
- *
- * This software is provided subject to the following terms and conditions,
- * which you should read carefully before using the software. Using this
- * software indicates your acceptance of these terms and conditions. If you do
- * not agree with these terms and conditions, do not use the software.
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- *
- * Redistribution and use in source or binary forms, with or without
- * modifications, are permitted provided that the following conditions are met:
- *
- * . Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following Disclaimer as comments in the code as
- * well as in the documentation and/or other materials provided with the
- * distribution.
- *
- * . Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following Disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * . Neither the name of Agere Systems Inc. nor the names of the contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * Disclaimer
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
- * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
- * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGE.
- *
- */
-
-#ifndef __ET131X_DEFS_H__
-#define __ET131X_DEFS_H__
-
-/* Packet and header sizes */
-#define NIC_MIN_PACKET_SIZE 60
-
-/* Multicast list size */
-#define NIC_MAX_MCAST_LIST 128
-
-/* Supported Filters */
-#define ET131X_PACKET_TYPE_DIRECTED 0x0001
-#define ET131X_PACKET_TYPE_MULTICAST 0x0002
-#define ET131X_PACKET_TYPE_BROADCAST 0x0004
-#define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
-#define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
-
-/* Tx Timeout */
-#define ET131X_TX_TIMEOUT (1 * HZ)
-#define NIC_SEND_HANG_THRESHOLD 0
-
-/* MP_TCB flags */
-#define fMP_DEST_MULTI 0x00000001
-#define fMP_DEST_BROAD 0x00000002
-
-/* MP_ADAPTER flags */
-#define fMP_ADAPTER_RECV_LOOKASIDE 0x00000004
-#define fMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
-#define fMP_ADAPTER_SECONDARY 0x00000010
-
-/* MP_SHARED flags */
-#define fMP_ADAPTER_SHUTDOWN 0x00100000
-#define fMP_ADAPTER_LOWER_POWER 0x00200000
-
-#define fMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
-#define fMP_ADAPTER_RESET_IN_PROGRESS 0x01000000
-#define fMP_ADAPTER_NO_CABLE 0x02000000
-#define fMP_ADAPTER_HARDWARE_ERROR 0x04000000
-#define fMP_ADAPTER_REMOVE_IN_PROGRESS 0x08000000
-#define fMP_ADAPTER_HALT_IN_PROGRESS 0x10000000
-
-#define fMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
-#define fMP_ADAPTER_NOT_READY_MASK 0x3ff00000
-
-/* Some offsets in PCI config space that are actually used. */
-#define ET1310_PCI_MAX_PYLD 0x4C
-#define ET1310_PCI_MAC_ADDRESS 0xA4
-#define ET1310_PCI_EEPROM_STATUS 0xB2
-#define ET1310_PCI_ACK_NACK 0xC0
-#define ET1310_PCI_REPLAY 0xC2
-#define ET1310_PCI_L0L1LATENCY 0xCF
-
-/* PCI Vendor/Product IDs */
-#define ET131X_PCI_VENDOR_ID 0x11C1 /* Agere Systems */
-#define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
-#define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
-
-/* Define order of magnitude converter */
-#define NANO_IN_A_MICRO 1000
-
-#define PARM_RX_NUM_BUFS_DEF 4
-#define PARM_RX_TIME_INT_DEF 10
-#define PARM_RX_MEM_END_DEF 0x2bc
-#define PARM_TX_TIME_INT_DEF 40
-#define PARM_TX_NUM_BUFS_DEF 4
-#define PARM_DMA_CACHE_DEF 0
-
-
-#endif /* __ET131X_DEFS_H__ */
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: move et1310_rx.h contents into et131x.c
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
` (4 preceding siblings ...)
2011-10-19 23:00 ` staging: et131x: move et131x_defs.h " Mark Einon
@ 2011-10-19 23:00 ` Mark Einon
2011-10-19 23:00 ` staging: et131x: move et1310_tx.h " Mark Einon
` (10 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:00 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
Move et1310_rx.h contents into et131x.c and delete et1310_rx.h
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/et1310_rx.h | 243 ------------------------------------
drivers/staging/et131x/et131x.c | 181 ++++++++++++++++++++++++++-
2 files changed, 180 insertions(+), 244 deletions(-)
delete mode 100644 drivers/staging/et131x/et1310_rx.h
diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h
deleted file mode 100644
index b3b1bc9..0000000
--- a/drivers/staging/et131x/et1310_rx.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Agere Systems Inc.
- * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- * http://www.agere.com
- *
- * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
- *
- *------------------------------------------------------------------------------
- *
- * et1310_rx.h - Defines, structs, enums, prototypes, etc. pertaining to data
- * reception.
- *
- *------------------------------------------------------------------------------
- *
- * SOFTWARE LICENSE
- *
- * This software is provided subject to the following terms and conditions,
- * which you should read carefully before using the software. Using this
- * software indicates your acceptance of these terms and conditions. If you do
- * not agree with these terms and conditions, do not use the software.
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- *
- * Redistribution and use in source or binary forms, with or without
- * modifications, are permitted provided that the following conditions are met:
- *
- * . Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following Disclaimer as comments in the code as
- * well as in the documentation and/or other materials provided with the
- * distribution.
- *
- * . Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following Disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * . Neither the name of Agere Systems Inc. nor the names of the contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * Disclaimer
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
- * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
- * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGE.
- *
- */
-
-#ifndef __ET1310_RX_H__
-#define __ET1310_RX_H__
-
-#define USE_FBR0 true
-
-#ifdef USE_FBR0
-/* #define FBR0_BUFFER_SIZE 256 */
-#endif
-
-/* #define FBR1_BUFFER_SIZE 2048 */
-
-#define FBR_CHUNKS 32
-
-#define MAX_DESC_PER_RING_RX 1024
-
-/* number of RFDs - default and min */
-#ifdef USE_FBR0
-#define RFD_LOW_WATER_MARK 40
-#define NIC_MIN_NUM_RFD 64
-#define NIC_DEFAULT_NUM_RFD 1024
-#else
-#define RFD_LOW_WATER_MARK 20
-#define NIC_MIN_NUM_RFD 64
-#define NIC_DEFAULT_NUM_RFD 256
-#endif
-
-#define NUM_PACKETS_HANDLED 256
-
-#define ALCATEL_BAD_STATUS 0xe47f0000
-#define ALCATEL_MULTICAST_PKT 0x01000000
-#define ALCATEL_BROADCAST_PKT 0x02000000
-
-/* typedefs for Free Buffer Descriptors */
-struct fbr_desc {
- u32 addr_lo;
- u32 addr_hi;
- u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
-};
-
-/* Packet Status Ring Descriptors
- *
- * Word 0:
- *
- * top 16 bits are from the Alcatel Status Word as enumerated in
- * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
- *
- * 0: hp hash pass
- * 1: ipa IP checksum assist
- * 2: ipp IP checksum pass
- * 3: tcpa TCP checksum assist
- * 4: tcpp TCP checksum pass
- * 5: wol WOL Event
- * 6: rxmac_error RXMAC Error Indicator
- * 7: drop Drop packet
- * 8: ft Frame Truncated
- * 9: jp Jumbo Packet
- * 10: vp VLAN Packet
- * 11-15: unused
- * 16: asw_prev_pkt_dropped e.g. IFG too small on previous
- * 17: asw_RX_DV_event short receive event detected
- * 18: asw_false_carrier_event bad carrier since last good packet
- * 19: asw_code_err one or more nibbles signalled as errors
- * 20: asw_CRC_err CRC error
- * 21: asw_len_chk_err frame length field incorrect
- * 22: asw_too_long frame length > 1518 bytes
- * 23: asw_OK valid CRC + no code error
- * 24: asw_multicast has a multicast address
- * 25: asw_broadcast has a broadcast address
- * 26: asw_dribble_nibble spurious bits after EOP
- * 27: asw_control_frame is a control frame
- * 28: asw_pause_frame is a pause frame
- * 29: asw_unsupported_op unsupported OP code
- * 30: asw_VLAN_tag VLAN tag detected
- * 31: asw_long_evt Rx long event
- *
- * Word 1:
- * 0-15: length length in bytes
- * 16-25: bi Buffer Index
- * 26-27: ri Ring Index
- * 28-31: reserved
- */
-
-struct pkt_stat_desc {
- u32 word0;
- u32 word1;
-};
-
-/* Typedefs for the RX DMA status word */
-
-/*
- * rx status word 0 holds part of the status bits of the Rx DMA engine
- * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
- * which contains the Free Buffer ring 0 and 1 available offset.
- *
- * bit 0-9 FBR1 offset
- * bit 10 Wrap flag for FBR1
- * bit 16-25 FBR0 offset
- * bit 26 Wrap flag for FBR0
- */
-
-/*
- * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
- * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
- * which contains the Packet Status Ring available offset.
- *
- * bit 0-15 reserved
- * bit 16-27 PSRoffset
- * bit 28 PSRwrap
- * bit 29-31 unused
- */
-
-/*
- * struct rx_status_block is a structure representing the status of the Rx
- * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
- */
-struct rx_status_block {
- u32 word0;
- u32 word1;
-};
-
-/*
- * Structure for look-up table holding free buffer ring pointers
- */
-struct fbr_lookup {
- void *virt[MAX_DESC_PER_RING_RX];
- void *buffer1[MAX_DESC_PER_RING_RX];
- void *buffer2[MAX_DESC_PER_RING_RX];
- u32 bus_high[MAX_DESC_PER_RING_RX];
- u32 bus_low[MAX_DESC_PER_RING_RX];
-};
-
-/*
- * struct rx_ring is the sructure representing the adaptor's local
- * reference(s) to the rings
- */
-struct rx_ring {
-#ifdef USE_FBR0
- void *fbr0_ring_virtaddr;
- dma_addr_t fbr0_ring_physaddr;
- void *fbr0_mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
- dma_addr_t fbr0_mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
- uint64_t fbr0_real_physaddr;
- uint64_t fbr0_offset;
- u32 local_fbr0_full;
- u32 fbr0_num_entries;
- u32 fbr0_buffsize;
-#endif
- void *fbr1_ring_virtaddr;
- dma_addr_t fbr1_ring_physaddr;
- void *fbr1_mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
- dma_addr_t fbr1_mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
- uint64_t fbr1_real_physaddr;
- uint64_t fbr1_offset;
- struct fbr_lookup *fbr[2]; /* One per ring */
- u32 local_fbr1_full;
- u32 fbr1_num_entries;
- u32 fbr1_buffsize;
-
- void *ps_ring_virtaddr;
- dma_addr_t ps_ring_physaddr;
- u32 local_psr_full;
- u32 psr_num_entries;
-
- struct rx_status_block *rx_status_block;
- dma_addr_t rx_status_bus;
-
- struct list_head recv_buff_pool;
-
- /* RECV */
- struct list_head recv_list;
- u32 num_ready_recv;
-
- u32 num_rfd;
-
- bool unfinished_receives;
-
- struct list_head recv_packet_pool;
-
- /* lookaside lists */
- struct kmem_cache *recv_lookaside;
-};
-
-#endif /* __ET1310_RX_H__ */
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 402ab7f..484a626 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -82,7 +82,6 @@
#include <linux/phy.h>
#include "et1310_tx.h"
-#include "et1310_rx.h"
#include "et131x.h"
MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
@@ -186,6 +185,186 @@ MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver "
#define PARM_TX_NUM_BUFS_DEF 4
#define PARM_DMA_CACHE_DEF 0
+/* RX defines */
+#define USE_FBR0 true
+
+#ifdef USE_FBR0
+/* #define FBR0_BUFFER_SIZE 256 */
+#endif
+
+/* #define FBR1_BUFFER_SIZE 2048 */
+
+#define FBR_CHUNKS 32
+
+#define MAX_DESC_PER_RING_RX 1024
+
+/* number of RFDs - default and min */
+#ifdef USE_FBR0
+#define RFD_LOW_WATER_MARK 40
+#define NIC_MIN_NUM_RFD 64
+#define NIC_DEFAULT_NUM_RFD 1024
+#else
+#define RFD_LOW_WATER_MARK 20
+#define NIC_MIN_NUM_RFD 64
+#define NIC_DEFAULT_NUM_RFD 256
+#endif
+
+#define NUM_PACKETS_HANDLED 256
+
+#define ALCATEL_BAD_STATUS 0xe47f0000
+#define ALCATEL_MULTICAST_PKT 0x01000000
+#define ALCATEL_BROADCAST_PKT 0x02000000
+
+/* typedefs for Free Buffer Descriptors */
+struct fbr_desc {
+ u32 addr_lo;
+ u32 addr_hi;
+ u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
+};
+
+/* Packet Status Ring Descriptors
+ *
+ * Word 0:
+ *
+ * top 16 bits are from the Alcatel Status Word as enumerated in
+ * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
+ *
+ * 0: hp hash pass
+ * 1: ipa IP checksum assist
+ * 2: ipp IP checksum pass
+ * 3: tcpa TCP checksum assist
+ * 4: tcpp TCP checksum pass
+ * 5: wol WOL Event
+ * 6: rxmac_error RXMAC Error Indicator
+ * 7: drop Drop packet
+ * 8: ft Frame Truncated
+ * 9: jp Jumbo Packet
+ * 10: vp VLAN Packet
+ * 11-15: unused
+ * 16: asw_prev_pkt_dropped e.g. IFG too small on previous
+ * 17: asw_RX_DV_event short receive event detected
+ * 18: asw_false_carrier_event bad carrier since last good packet
+ * 19: asw_code_err one or more nibbles signalled as errors
+ * 20: asw_CRC_err CRC error
+ * 21: asw_len_chk_err frame length field incorrect
+ * 22: asw_too_long frame length > 1518 bytes
+ * 23: asw_OK valid CRC + no code error
+ * 24: asw_multicast has a multicast address
+ * 25: asw_broadcast has a broadcast address
+ * 26: asw_dribble_nibble spurious bits after EOP
+ * 27: asw_control_frame is a control frame
+ * 28: asw_pause_frame is a pause frame
+ * 29: asw_unsupported_op unsupported OP code
+ * 30: asw_VLAN_tag VLAN tag detected
+ * 31: asw_long_evt Rx long event
+ *
+ * Word 1:
+ * 0-15: length length in bytes
+ * 16-25: bi Buffer Index
+ * 26-27: ri Ring Index
+ * 28-31: reserved
+ */
+
+struct pkt_stat_desc {
+ u32 word0;
+ u32 word1;
+};
+
+/* Typedefs for the RX DMA status word */
+
+/*
+ * rx status word 0 holds part of the status bits of the Rx DMA engine
+ * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
+ * which contains the Free Buffer ring 0 and 1 available offset.
+ *
+ * bit 0-9 FBR1 offset
+ * bit 10 Wrap flag for FBR1
+ * bit 16-25 FBR0 offset
+ * bit 26 Wrap flag for FBR0
+ */
+
+/*
+ * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
+ * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
+ * which contains the Packet Status Ring available offset.
+ *
+ * bit 0-15 reserved
+ * bit 16-27 PSRoffset
+ * bit 28 PSRwrap
+ * bit 29-31 unused
+ */
+
+/*
+ * struct rx_status_block is a structure representing the status of the Rx
+ * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
+ */
+struct rx_status_block {
+ u32 word0;
+ u32 word1;
+};
+
+/*
+ * Structure for look-up table holding free buffer ring pointers
+ */
+struct fbr_lookup {
+ void *virt[MAX_DESC_PER_RING_RX];
+ void *buffer1[MAX_DESC_PER_RING_RX];
+ void *buffer2[MAX_DESC_PER_RING_RX];
+ u32 bus_high[MAX_DESC_PER_RING_RX];
+ u32 bus_low[MAX_DESC_PER_RING_RX];
+};
+
+/*
+ * struct rx_ring is the sructure representing the adaptor's local
+ * reference(s) to the rings
+ */
+struct rx_ring {
+#ifdef USE_FBR0
+ void *fbr0_ring_virtaddr;
+ dma_addr_t fbr0_ring_physaddr;
+ void *fbr0_mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
+ dma_addr_t fbr0_mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
+ uint64_t fbr0_real_physaddr;
+ uint64_t fbr0_offset;
+ u32 local_fbr0_full;
+ u32 fbr0_num_entries;
+ u32 fbr0_buffsize;
+#endif
+ void *fbr1_ring_virtaddr;
+ dma_addr_t fbr1_ring_physaddr;
+ void *fbr1_mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
+ dma_addr_t fbr1_mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
+ uint64_t fbr1_real_physaddr;
+ uint64_t fbr1_offset;
+ struct fbr_lookup *fbr[2]; /* One per ring */
+ u32 local_fbr1_full;
+ u32 fbr1_num_entries;
+ u32 fbr1_buffsize;
+
+ void *ps_ring_virtaddr;
+ dma_addr_t ps_ring_physaddr;
+ u32 local_psr_full;
+ u32 psr_num_entries;
+
+ struct rx_status_block *rx_status_block;
+ dma_addr_t rx_status_bus;
+
+ struct list_head recv_buff_pool;
+
+ /* RECV */
+ struct list_head recv_list;
+ u32 num_ready_recv;
+
+ u32 num_rfd;
+
+ bool unfinished_receives;
+
+ struct list_head recv_packet_pool;
+
+ /* lookaside lists */
+ struct kmem_cache *recv_lookaside;
+};
+
/* ADAPTER defines */
/*
* Do not change these values: if changed, then change also in respective
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: move et1310_tx.h contents into et131x.c
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
` (5 preceding siblings ...)
2011-10-19 23:00 ` staging: et131x: move et1310_rx.h " Mark Einon
@ 2011-10-19 23:00 ` Mark Einon
2011-10-19 23:00 ` staging: et131x: Update TODO list - remove 'put driver into single file' Mark Einon
` (9 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:00 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
Move et1310_tx.h contents into et131x.c and delete et1310_tx.h
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/et1310_tx.h | 150 ------------------------------------
drivers/staging/et131x/et131x.c | 87 ++++++++++++++++++++-
2 files changed, 86 insertions(+), 151 deletions(-)
delete mode 100644 drivers/staging/et131x/et1310_tx.h
diff --git a/drivers/staging/et131x/et1310_tx.h b/drivers/staging/et131x/et1310_tx.h
deleted file mode 100644
index 82d06e9..0000000
--- a/drivers/staging/et131x/et1310_tx.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * Agere Systems Inc.
- * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- * http://www.agere.com
- *
- *------------------------------------------------------------------------------
- *
- * et1310_tx.h - Defines, structs, enums, prototypes, etc. pertaining to data
- * transmission.
- *
- *------------------------------------------------------------------------------
- *
- * SOFTWARE LICENSE
- *
- * This software is provided subject to the following terms and conditions,
- * which you should read carefully before using the software. Using this
- * software indicates your acceptance of these terms and conditions. If you do
- * not agree with these terms and conditions, do not use the software.
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- *
- * Redistribution and use in source or binary forms, with or without
- * modifications, are permitted provided that the following conditions are met:
- *
- * . Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following Disclaimer as comments in the code as
- * well as in the documentation and/or other materials provided with the
- * distribution.
- *
- * . Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following Disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * . Neither the name of Agere Systems Inc. nor the names of the contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * Disclaimer
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
- * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
- * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGE.
- *
- */
-
-#ifndef __ET1310_TX_H__
-#define __ET1310_TX_H__
-
-
-/* Typedefs for Tx Descriptor Ring */
-
-/*
- * word 2 of the control bits in the Tx Descriptor ring for the ET-1310
- *
- * 0-15: length of packet
- * 16-27: VLAN tag
- * 28: VLAN CFI
- * 29-31: VLAN priority
- *
- * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
- *
- * 0: last packet in the sequence
- * 1: first packet in the sequence
- * 2: interrupt the processor when this pkt sent
- * 3: Control word - no packet data
- * 4: Issue half-duplex backpressure : XON/XOFF
- * 5: send pause frame
- * 6: Tx frame has error
- * 7: append CRC
- * 8: MAC override
- * 9: pad packet
- * 10: Packet is a Huge packet
- * 11: append VLAN tag
- * 12: IP checksum assist
- * 13: TCP checksum assist
- * 14: UDP checksum assist
- */
-
-/* struct tx_desc represents each descriptor on the ring */
-struct tx_desc {
- u32 addr_hi;
- u32 addr_lo;
- u32 len_vlan; /* control words how to xmit the */
- u32 flags; /* data (detailed above) */
-};
-
-/*
- * The status of the Tx DMA engine it sits in free memory, and is pointed to
- * by 0x101c / 0x1020. This is a DMA10 type
- */
-
-/* TCB (Transmit Control Block: Host Side) */
-struct tcb {
- struct tcb *next; /* Next entry in ring */
- u32 flags; /* Our flags for the packet */
- u32 count; /* Used to spot stuck/lost packets */
- u32 stale; /* Used to spot stuck/lost packets */
- struct sk_buff *skb; /* Network skb we are tied to */
- u32 index; /* Ring indexes */
- u32 index_start;
-};
-
-/* Structure representing our local reference(s) to the ring */
-struct tx_ring {
- /* TCB (Transmit Control Block) memory and lists */
- struct tcb *tcb_ring;
-
- /* List of TCBs that are ready to be used */
- struct tcb *tcb_qhead;
- struct tcb *tcb_qtail;
-
- /* list of TCBs that are currently being sent. NOTE that access to all
- * three of these (including used) are controlled via the
- * TCBSendQLock. This lock should be secured prior to incementing /
- * decrementing used, or any queue manipulation on send_head /
- * tail
- */
- struct tcb *send_head;
- struct tcb *send_tail;
- int used;
-
- /* The actual descriptor ring */
- struct tx_desc *tx_desc_ring;
- dma_addr_t tx_desc_ring_pa;
-
- /* send_idx indicates where we last wrote to in the descriptor ring. */
- u32 send_idx;
-
- /* The location of the write-back status block */
- u32 *tx_status;
- dma_addr_t tx_status_pa;
-
- /* Packets since the last IRQ: used for interrupt coalescing */
- int since_irq;
-};
-
-#endif /* __ET1310_TX_H__ */
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 484a626..9596102 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -81,7 +81,6 @@
#include <linux/random.h>
#include <linux/phy.h>
-#include "et1310_tx.h"
#include "et131x.h"
MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
@@ -365,6 +364,92 @@ struct rx_ring {
struct kmem_cache *recv_lookaside;
};
+/* TX defines */
+/*
+ * word 2 of the control bits in the Tx Descriptor ring for the ET-1310
+ *
+ * 0-15: length of packet
+ * 16-27: VLAN tag
+ * 28: VLAN CFI
+ * 29-31: VLAN priority
+ *
+ * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
+ *
+ * 0: last packet in the sequence
+ * 1: first packet in the sequence
+ * 2: interrupt the processor when this pkt sent
+ * 3: Control word - no packet data
+ * 4: Issue half-duplex backpressure : XON/XOFF
+ * 5: send pause frame
+ * 6: Tx frame has error
+ * 7: append CRC
+ * 8: MAC override
+ * 9: pad packet
+ * 10: Packet is a Huge packet
+ * 11: append VLAN tag
+ * 12: IP checksum assist
+ * 13: TCP checksum assist
+ * 14: UDP checksum assist
+ */
+
+/* struct tx_desc represents each descriptor on the ring */
+struct tx_desc {
+ u32 addr_hi;
+ u32 addr_lo;
+ u32 len_vlan; /* control words how to xmit the */
+ u32 flags; /* data (detailed above) */
+};
+
+/*
+ * The status of the Tx DMA engine it sits in free memory, and is pointed to
+ * by 0x101c / 0x1020. This is a DMA10 type
+ */
+
+/* TCB (Transmit Control Block: Host Side) */
+struct tcb {
+ struct tcb *next; /* Next entry in ring */
+ u32 flags; /* Our flags for the packet */
+ u32 count; /* Used to spot stuck/lost packets */
+ u32 stale; /* Used to spot stuck/lost packets */
+ struct sk_buff *skb; /* Network skb we are tied to */
+ u32 index; /* Ring indexes */
+ u32 index_start;
+};
+
+/* Structure representing our local reference(s) to the ring */
+struct tx_ring {
+ /* TCB (Transmit Control Block) memory and lists */
+ struct tcb *tcb_ring;
+
+ /* List of TCBs that are ready to be used */
+ struct tcb *tcb_qhead;
+ struct tcb *tcb_qtail;
+
+ /* list of TCBs that are currently being sent. NOTE that access to all
+ * three of these (including used) are controlled via the
+ * TCBSendQLock. This lock should be secured prior to incementing /
+ * decrementing used, or any queue manipulation on send_head /
+ * tail
+ */
+ struct tcb *send_head;
+ struct tcb *send_tail;
+ int used;
+
+ /* The actual descriptor ring */
+ struct tx_desc *tx_desc_ring;
+ dma_addr_t tx_desc_ring_pa;
+
+ /* send_idx indicates where we last wrote to in the descriptor ring. */
+ u32 send_idx;
+
+ /* The location of the write-back status block */
+ u32 *tx_status;
+ dma_addr_t tx_status_pa;
+
+ /* Packets since the last IRQ: used for interrupt coalescing */
+ int since_irq;
+};
+
/* ADAPTER defines */
/*
* Do not change these values: if changed, then change also in respective
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: Update TODO list - remove 'put driver into single file'
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
` (6 preceding siblings ...)
2011-10-19 23:00 ` staging: et131x: move et1310_tx.h " Mark Einon
@ 2011-10-19 23:00 ` Mark Einon
2011-10-19 23:01 ` staging: et131x: Moving two extern inline functions to .c file Mark Einon
` (8 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:00 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
Driver now resides in a single file with a separate header with
registers, updated the README TODO list.
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/README | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/drivers/staging/et131x/README b/drivers/staging/et131x/README
index c67f83e..a7b33dc 100644
--- a/drivers/staging/et131x/README
+++ b/drivers/staging/et131x/README
@@ -8,7 +8,6 @@ Note, the powermanagement options were removed from the vendor provided
driver as they did not build properly at the time.
TODO:
- - Put the driver into a single file, with a .h for the registers layout.
- rx_ring.fbr{0, 1} can probably share a common structure
- Use of kmem_cache seems a bit unusual
- Use dma_alloc_... in place of pci_alloc_...
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: Moving two extern inline functions to .c file
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
` (7 preceding siblings ...)
2011-10-19 23:00 ` staging: et131x: Update TODO list - remove 'put driver into single file' Mark Einon
@ 2011-10-19 23:01 ` Mark Einon
2011-10-19 23:01 ` staging: et131x: Make rx_ring.fbr{0,1} share a common structure Mark Einon
` (7 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:01 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
Two helper functions for adding 10bit/12bit umbers with wrapping are
defined in the header. Moved them to the driver .c file.
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/et131x.c | 11 +++++++++++
drivers/staging/et131x/et131x.h | 10 ----------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 9596102..14f54e4 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -2666,6 +2666,17 @@ void et131x_rx_dma_enable(struct et131x_adapter *adapter)
}
}
+
+static inline void add_10bit(u32 *v, int n)
+{
+ *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
+}
+
+static inline void add_12bit(u32 *v, int n)
+{
+ *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
+}
+
/**
* nic_rx_pkts - Checks the hardware for available packets
* @adapter: pointer to our adapter
diff --git a/drivers/staging/et131x/et131x.h b/drivers/staging/et131x/et131x.h
index 84b274d..7eed3c8 100644
--- a/drivers/staging/et131x/et131x.h
+++ b/drivers/staging/et131x/et131x.h
@@ -230,16 +230,6 @@ struct global_regs { /* Location: */
#define INDEX10(x) ((x) & ET_DMA10_MASK)
#define INDEX4(x) ((x) & ET_DMA4_MASK)
-extern inline void add_10bit(u32 *v, int n)
-{
- *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
-}
-
-extern inline void add_12bit(u32 *v, int n)
-{
- *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
-}
-
/*
* 10bit DMA with wrap
* txdma tx queue write address reg in txdma address map at 0x1010
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: Make rx_ring.fbr{0,1} share a common structure
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
` (8 preceding siblings ...)
2011-10-19 23:01 ` staging: et131x: Moving two extern inline functions to .c file Mark Einon
@ 2011-10-19 23:01 ` Mark Einon
2011-10-19 23:01 ` staging: et131x: Fix issues when USE_FBR0 is not defined Mark Einon
` (6 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:01 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
Sharing a common structure by moving common structure items into
fbr_lookup.
TODO - Currently will not work if USE_FBR0 = 0 as FBR1 uses fbr[1]
which is removed in this case
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/et131x.c | 293 +++++++++++++++++++--------------------
1 files changed, 140 insertions(+), 153 deletions(-)
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 14f54e4..0bc3e04 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -185,13 +185,7 @@ MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver "
#define PARM_DMA_CACHE_DEF 0
/* RX defines */
-#define USE_FBR0 true
-
-#ifdef USE_FBR0
-/* #define FBR0_BUFFER_SIZE 256 */
-#endif
-
-/* #define FBR1_BUFFER_SIZE 2048 */
+#define USE_FBR0 1
#define FBR_CHUNKS 32
@@ -200,14 +194,16 @@ MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver "
/* number of RFDs - default and min */
#ifdef USE_FBR0
#define RFD_LOW_WATER_MARK 40
-#define NIC_MIN_NUM_RFD 64
#define NIC_DEFAULT_NUM_RFD 1024
+#define NUM_FBRS 2
#else
#define RFD_LOW_WATER_MARK 20
-#define NIC_MIN_NUM_RFD 64
#define NIC_DEFAULT_NUM_RFD 256
+#define NUM_FBRS 1
#endif
+#define NIC_MIN_NUM_RFD 64
+
#define NUM_PACKETS_HANDLED 256
#define ALCATEL_BAD_STATUS 0xe47f0000
@@ -303,14 +299,24 @@ struct rx_status_block {
};
/*
- * Structure for look-up table holding free buffer ring pointers
+ * Structure for look-up table holding free buffer ring pointers, addresses
+ * and state.
*/
struct fbr_lookup {
- void *virt[MAX_DESC_PER_RING_RX];
- void *buffer1[MAX_DESC_PER_RING_RX];
- void *buffer2[MAX_DESC_PER_RING_RX];
- u32 bus_high[MAX_DESC_PER_RING_RX];
- u32 bus_low[MAX_DESC_PER_RING_RX];
+ void *virt[MAX_DESC_PER_RING_RX];
+ void *buffer1[MAX_DESC_PER_RING_RX];
+ void *buffer2[MAX_DESC_PER_RING_RX];
+ u32 bus_high[MAX_DESC_PER_RING_RX];
+ u32 bus_low[MAX_DESC_PER_RING_RX];
+ void *ring_virtaddr;
+ dma_addr_t ring_physaddr;
+ void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
+ dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
+ uint64_t real_physaddr;
+ uint64_t offset;
+ u32 local_full;
+ u32 num_entries;
+ u32 buffsize;
};
/*
@@ -318,27 +324,7 @@ struct fbr_lookup {
* reference(s) to the rings
*/
struct rx_ring {
-#ifdef USE_FBR0
- void *fbr0_ring_virtaddr;
- dma_addr_t fbr0_ring_physaddr;
- void *fbr0_mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
- dma_addr_t fbr0_mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
- uint64_t fbr0_real_physaddr;
- uint64_t fbr0_offset;
- u32 local_fbr0_full;
- u32 fbr0_num_entries;
- u32 fbr0_buffsize;
-#endif
- void *fbr1_ring_virtaddr;
- dma_addr_t fbr1_ring_physaddr;
- void *fbr1_mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
- dma_addr_t fbr1_mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
- uint64_t fbr1_real_physaddr;
- uint64_t fbr1_offset;
- struct fbr_lookup *fbr[2]; /* One per ring */
- u32 local_fbr1_full;
- u32 fbr1_num_entries;
- u32 fbr1_buffsize;
+ struct fbr_lookup *fbr[NUM_FBRS];
void *ps_ring_virtaddr;
dma_addr_t ps_ring_physaddr;
@@ -1945,40 +1931,40 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
if (adapter->registry_jumbo_packet < 2048) {
#ifdef USE_FBR0
- rx_ring->fbr0_buffsize = 256;
- rx_ring->fbr0_num_entries = 512;
+ rx_ring->fbr[0]->buffsize = 256;
+ rx_ring->fbr[0]->num_entries = 512;
#endif
- rx_ring->fbr1_buffsize = 2048;
- rx_ring->fbr1_num_entries = 512;
+ rx_ring->fbr[1]->buffsize = 2048;
+ rx_ring->fbr[1]->num_entries = 512;
} else if (adapter->registry_jumbo_packet < 4096) {
#ifdef USE_FBR0
- rx_ring->fbr0_buffsize = 512;
- rx_ring->fbr0_num_entries = 1024;
+ rx_ring->fbr[0]->buffsize = 512;
+ rx_ring->fbr[0]->num_entries = 1024;
#endif
- rx_ring->fbr1_buffsize = 4096;
- rx_ring->fbr1_num_entries = 512;
+ rx_ring->fbr[1]->buffsize = 4096;
+ rx_ring->fbr[1]->num_entries = 512;
} else {
#ifdef USE_FBR0
- rx_ring->fbr0_buffsize = 1024;
- rx_ring->fbr0_num_entries = 768;
+ rx_ring->fbr[0]->buffsize = 1024;
+ rx_ring->fbr[0]->num_entries = 768;
#endif
- rx_ring->fbr1_buffsize = 16384;
- rx_ring->fbr1_num_entries = 128;
+ rx_ring->fbr[1]->buffsize = 16384;
+ rx_ring->fbr[1]->num_entries = 128;
}
#ifdef USE_FBR0
- adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr0_num_entries +
- adapter->rx_ring.fbr1_num_entries;
+ adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr[0]->num_entries +
+ adapter->rx_ring.fbr[1]->num_entries;
#else
- adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr1_num_entries;
+ adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr[1]->num_entries;
#endif
/* Allocate an area of memory for Free Buffer Ring 1 */
- bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr1_num_entries) + 0xfff;
- rx_ring->fbr1_ring_virtaddr = pci_alloc_consistent(adapter->pdev,
+ bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries) + 0xfff;
+ rx_ring->fbr[1]->ring_virtaddr = pci_alloc_consistent(adapter->pdev,
bufsize,
- &rx_ring->fbr1_ring_physaddr);
- if (!rx_ring->fbr1_ring_virtaddr) {
+ &rx_ring->fbr[1]->ring_physaddr);
+ if (!rx_ring->fbr[1]->ring_virtaddr) {
dev_err(&adapter->pdev->dev,
"Cannot alloc memory for Free Buffer Ring 1\n");
return -ENOMEM;
@@ -1991,24 +1977,24 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
* are ever returned, make sure the high part is retrieved here
* before storing the adjusted address.
*/
- rx_ring->fbr1_real_physaddr = rx_ring->fbr1_ring_physaddr;
+ rx_ring->fbr[1]->real_physaddr = rx_ring->fbr[1]->ring_physaddr;
/* Align Free Buffer Ring 1 on a 4K boundary */
et131x_align_allocated_memory(adapter,
- &rx_ring->fbr1_real_physaddr,
- &rx_ring->fbr1_offset, 0x0FFF);
+ &rx_ring->fbr[1]->real_physaddr,
+ &rx_ring->fbr[1]->offset, 0x0FFF);
- rx_ring->fbr1_ring_virtaddr =
- (void *)((u8 *) rx_ring->fbr1_ring_virtaddr +
- rx_ring->fbr1_offset);
+ rx_ring->fbr[1]->ring_virtaddr =
+ (void *)((u8 *) rx_ring->fbr[1]->ring_virtaddr +
+ rx_ring->fbr[1]->offset);
#ifdef USE_FBR0
/* Allocate an area of memory for Free Buffer Ring 0 */
- bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr0_num_entries) + 0xfff;
- rx_ring->fbr0_ring_virtaddr = pci_alloc_consistent(adapter->pdev,
+ bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries) + 0xfff;
+ rx_ring->fbr[0]->ring_virtaddr = pci_alloc_consistent(adapter->pdev,
bufsize,
- &rx_ring->fbr0_ring_physaddr);
- if (!rx_ring->fbr0_ring_virtaddr) {
+ &rx_ring->fbr[0]->ring_physaddr);
+ if (!rx_ring->fbr[0]->ring_virtaddr) {
dev_err(&adapter->pdev->dev,
"Cannot alloc memory for Free Buffer Ring 0\n");
return -ENOMEM;
@@ -2021,18 +2007,18 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
* are ever returned, make sure the high part is retrieved here before
* storing the adjusted address.
*/
- rx_ring->fbr0_real_physaddr = rx_ring->fbr0_ring_physaddr;
+ rx_ring->fbr[0]->real_physaddr = rx_ring->fbr[0]->ring_physaddr;
/* Align Free Buffer Ring 0 on a 4K boundary */
et131x_align_allocated_memory(adapter,
- &rx_ring->fbr0_real_physaddr,
- &rx_ring->fbr0_offset, 0x0FFF);
+ &rx_ring->fbr[0]->real_physaddr,
+ &rx_ring->fbr[0]->offset, 0x0FFF);
- rx_ring->fbr0_ring_virtaddr =
- (void *)((u8 *) rx_ring->fbr0_ring_virtaddr +
- rx_ring->fbr0_offset);
+ rx_ring->fbr[0]->ring_virtaddr =
+ (void *)((u8 *) rx_ring->fbr[0]->ring_virtaddr +
+ rx_ring->fbr[0]->offset);
#endif
- for (i = 0; i < (rx_ring->fbr1_num_entries / FBR_CHUNKS); i++) {
+ for (i = 0; i < (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); i++) {
u64 fbr1_offset;
u64 fbr1_tmp_physaddr;
u32 fbr1_align;
@@ -2044,25 +2030,25 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
* the size of FBR0. By allocating N buffers at once, we
* reduce this overhead.
*/
- if (rx_ring->fbr1_buffsize > 4096)
+ if (rx_ring->fbr[1]->buffsize > 4096)
fbr1_align = 4096;
else
- fbr1_align = rx_ring->fbr1_buffsize;
+ fbr1_align = rx_ring->fbr[1]->buffsize;
fbr_chunksize =
- (FBR_CHUNKS * rx_ring->fbr1_buffsize) + fbr1_align - 1;
- rx_ring->fbr1_mem_virtaddrs[i] =
+ (FBR_CHUNKS * rx_ring->fbr[1]->buffsize) + fbr1_align - 1;
+ rx_ring->fbr[1]->mem_virtaddrs[i] =
pci_alloc_consistent(adapter->pdev, fbr_chunksize,
- &rx_ring->fbr1_mem_physaddrs[i]);
+ &rx_ring->fbr[1]->mem_physaddrs[i]);
- if (!rx_ring->fbr1_mem_virtaddrs[i]) {
+ if (!rx_ring->fbr[1]->mem_virtaddrs[i]) {
dev_err(&adapter->pdev->dev,
"Could not alloc memory\n");
return -ENOMEM;
}
/* See NOTE in "Save Physical Address" comment above */
- fbr1_tmp_physaddr = rx_ring->fbr1_mem_physaddrs[i];
+ fbr1_tmp_physaddr = rx_ring->fbr[1]->mem_physaddrs[i];
et131x_align_allocated_memory(adapter,
&fbr1_tmp_physaddr,
@@ -2075,8 +2061,8 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
* access later
*/
rx_ring->fbr[1]->virt[index] =
- (u8 *) rx_ring->fbr1_mem_virtaddrs[i] +
- (j * rx_ring->fbr1_buffsize) + fbr1_offset;
+ (u8 *) rx_ring->fbr[1]->mem_virtaddrs[i] +
+ (j * rx_ring->fbr[1]->buffsize) + fbr1_offset;
/* now store the physical address in the descriptor
* so the device can access it
@@ -2086,7 +2072,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
rx_ring->fbr[1]->bus_low[index] =
(u32) fbr1_tmp_physaddr;
- fbr1_tmp_physaddr += rx_ring->fbr1_buffsize;
+ fbr1_tmp_physaddr += rx_ring->fbr[1]->buffsize;
rx_ring->fbr[1]->buffer1[index] =
rx_ring->fbr[1]->virt[index];
@@ -2097,43 +2083,43 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
#ifdef USE_FBR0
/* Same for FBR0 (if in use) */
- for (i = 0; i < (rx_ring->fbr0_num_entries / FBR_CHUNKS); i++) {
+ for (i = 0; i < (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); i++) {
u64 fbr0_offset;
u64 fbr0_tmp_physaddr;
fbr_chunksize =
- ((FBR_CHUNKS + 1) * rx_ring->fbr0_buffsize) - 1;
- rx_ring->fbr0_mem_virtaddrs[i] =
+ ((FBR_CHUNKS + 1) * rx_ring->fbr[0]->buffsize) - 1;
+ rx_ring->fbr[0]->mem_virtaddrs[i] =
pci_alloc_consistent(adapter->pdev, fbr_chunksize,
- &rx_ring->fbr0_mem_physaddrs[i]);
+ &rx_ring->fbr[0]->mem_physaddrs[i]);
- if (!rx_ring->fbr0_mem_virtaddrs[i]) {
+ if (!rx_ring->fbr[0]->mem_virtaddrs[i]) {
dev_err(&adapter->pdev->dev,
"Could not alloc memory\n");
return -ENOMEM;
}
/* See NOTE in "Save Physical Address" comment above */
- fbr0_tmp_physaddr = rx_ring->fbr0_mem_physaddrs[i];
+ fbr0_tmp_physaddr = rx_ring->fbr[0]->mem_physaddrs[i];
et131x_align_allocated_memory(adapter,
&fbr0_tmp_physaddr,
&fbr0_offset,
- rx_ring->fbr0_buffsize - 1);
+ rx_ring->fbr[0]->buffsize - 1);
for (j = 0; j < FBR_CHUNKS; j++) {
u32 index = (i * FBR_CHUNKS) + j;
rx_ring->fbr[0]->virt[index] =
- (u8 *) rx_ring->fbr0_mem_virtaddrs[i] +
- (j * rx_ring->fbr0_buffsize) + fbr0_offset;
+ (u8 *) rx_ring->fbr[0]->mem_virtaddrs[i] +
+ (j * rx_ring->fbr[0]->buffsize) + fbr0_offset;
rx_ring->fbr[0]->bus_high[index] =
(u32) (fbr0_tmp_physaddr >> 32);
rx_ring->fbr[0]->bus_low[index] =
(u32) fbr0_tmp_physaddr;
- fbr0_tmp_physaddr += rx_ring->fbr0_buffsize;
+ fbr0_tmp_physaddr += rx_ring->fbr[0]->buffsize;
rx_ring->fbr[0]->buffer1[index] =
rx_ring->fbr[0]->virt[index];
@@ -2228,78 +2214,78 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
}
/* Free Free Buffer Ring 1 */
- if (rx_ring->fbr1_ring_virtaddr) {
+ if (rx_ring->fbr[1]->ring_virtaddr) {
/* First the packet memory */
for (index = 0; index <
- (rx_ring->fbr1_num_entries / FBR_CHUNKS); index++) {
- if (rx_ring->fbr1_mem_virtaddrs[index]) {
+ (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); index++) {
+ if (rx_ring->fbr[1]->mem_virtaddrs[index]) {
u32 fbr1_align;
- if (rx_ring->fbr1_buffsize > 4096)
+ if (rx_ring->fbr[1]->buffsize > 4096)
fbr1_align = 4096;
else
- fbr1_align = rx_ring->fbr1_buffsize;
+ fbr1_align = rx_ring->fbr[1]->buffsize;
bufsize =
- (rx_ring->fbr1_buffsize * FBR_CHUNKS) +
+ (rx_ring->fbr[1]->buffsize * FBR_CHUNKS) +
fbr1_align - 1;
pci_free_consistent(adapter->pdev,
bufsize,
- rx_ring->fbr1_mem_virtaddrs[index],
- rx_ring->fbr1_mem_physaddrs[index]);
+ rx_ring->fbr[1]->mem_virtaddrs[index],
+ rx_ring->fbr[1]->mem_physaddrs[index]);
- rx_ring->fbr1_mem_virtaddrs[index] = NULL;
+ rx_ring->fbr[1]->mem_virtaddrs[index] = NULL;
}
}
/* Now the FIFO itself */
- rx_ring->fbr1_ring_virtaddr = (void *)((u8 *)
- rx_ring->fbr1_ring_virtaddr - rx_ring->fbr1_offset);
+ rx_ring->fbr[1]->ring_virtaddr = (void *)((u8 *)
+ rx_ring->fbr[1]->ring_virtaddr - rx_ring->fbr[1]->offset);
- bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr1_num_entries)
+ bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries)
+ 0xfff;
pci_free_consistent(adapter->pdev, bufsize,
- rx_ring->fbr1_ring_virtaddr,
- rx_ring->fbr1_ring_physaddr);
+ rx_ring->fbr[1]->ring_virtaddr,
+ rx_ring->fbr[1]->ring_physaddr);
- rx_ring->fbr1_ring_virtaddr = NULL;
+ rx_ring->fbr[1]->ring_virtaddr = NULL;
}
#ifdef USE_FBR0
/* Now the same for Free Buffer Ring 0 */
- if (rx_ring->fbr0_ring_virtaddr) {
+ if (rx_ring->fbr[0]->ring_virtaddr) {
/* First the packet memory */
for (index = 0; index <
- (rx_ring->fbr0_num_entries / FBR_CHUNKS); index++) {
- if (rx_ring->fbr0_mem_virtaddrs[index]) {
+ (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); index++) {
+ if (rx_ring->fbr[0]->mem_virtaddrs[index]) {
bufsize =
- (rx_ring->fbr0_buffsize *
+ (rx_ring->fbr[0]->buffsize *
(FBR_CHUNKS + 1)) - 1;
pci_free_consistent(adapter->pdev,
bufsize,
- rx_ring->fbr0_mem_virtaddrs[index],
- rx_ring->fbr0_mem_physaddrs[index]);
+ rx_ring->fbr[0]->mem_virtaddrs[index],
+ rx_ring->fbr[0]->mem_physaddrs[index]);
- rx_ring->fbr0_mem_virtaddrs[index] = NULL;
+ rx_ring->fbr[0]->mem_virtaddrs[index] = NULL;
}
}
/* Now the FIFO itself */
- rx_ring->fbr0_ring_virtaddr = (void *)((u8 *)
- rx_ring->fbr0_ring_virtaddr - rx_ring->fbr0_offset);
+ rx_ring->fbr[0]->ring_virtaddr = (void *)((u8 *)
+ rx_ring->fbr[0]->ring_virtaddr - rx_ring->fbr[0]->offset);
- bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr0_num_entries)
+ bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries)
+ 0xfff;
pci_free_consistent(adapter->pdev,
bufsize,
- rx_ring->fbr0_ring_virtaddr,
- rx_ring->fbr0_ring_physaddr);
+ rx_ring->fbr[0]->ring_virtaddr,
+ rx_ring->fbr[0]->ring_physaddr);
- rx_ring->fbr0_ring_virtaddr = NULL;
+ rx_ring->fbr[0]->ring_virtaddr = NULL;
}
#endif
@@ -2445,8 +2431,8 @@ void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
rx_local->local_psr_full = 0;
/* Now's the best time to initialize FBR1 contents */
- fbr_entry = (struct fbr_desc *) rx_local->fbr1_ring_virtaddr;
- for (entry = 0; entry < rx_local->fbr1_num_entries; entry++) {
+ fbr_entry = (struct fbr_desc *) rx_local->fbr[1]->ring_virtaddr;
+ for (entry = 0; entry < rx_local->fbr[1]->num_entries; entry++) {
fbr_entry->addr_hi = rx_local->fbr[1]->bus_high[entry];
fbr_entry->addr_lo = rx_local->fbr[1]->bus_low[entry];
fbr_entry->word2 = entry;
@@ -2456,42 +2442,42 @@ void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
/* Set the address and parameters of Free buffer ring 1 (and 0 if
* required) into the 1310's registers
*/
- writel((u32) (rx_local->fbr1_real_physaddr >> 32),
+ writel((u32) (rx_local->fbr[1]->real_physaddr >> 32),
&rx_dma->fbr1_base_hi);
- writel((u32) rx_local->fbr1_real_physaddr, &rx_dma->fbr1_base_lo);
- writel(rx_local->fbr1_num_entries - 1, &rx_dma->fbr1_num_des);
+ writel((u32) rx_local->fbr[1]->real_physaddr, &rx_dma->fbr1_base_lo);
+ writel(rx_local->fbr[1]->num_entries - 1, &rx_dma->fbr1_num_des);
writel(ET_DMA10_WRAP, &rx_dma->fbr1_full_offset);
/* This variable tracks the free buffer ring 1 full position, so it
* has to match the above.
*/
- rx_local->local_fbr1_full = ET_DMA10_WRAP;
+ rx_local->fbr[1]->local_full = ET_DMA10_WRAP;
writel(
- ((rx_local->fbr1_num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
+ ((rx_local->fbr[1]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
&rx_dma->fbr1_min_des);
#ifdef USE_FBR0
/* Now's the best time to initialize FBR0 contents */
- fbr_entry = (struct fbr_desc *) rx_local->fbr0_ring_virtaddr;
- for (entry = 0; entry < rx_local->fbr0_num_entries; entry++) {
+ fbr_entry = (struct fbr_desc *) rx_local->fbr[0]->ring_virtaddr;
+ for (entry = 0; entry < rx_local->fbr[0]->num_entries; entry++) {
fbr_entry->addr_hi = rx_local->fbr[0]->bus_high[entry];
fbr_entry->addr_lo = rx_local->fbr[0]->bus_low[entry];
fbr_entry->word2 = entry;
fbr_entry++;
}
- writel((u32) (rx_local->fbr0_real_physaddr >> 32),
+ writel((u32) (rx_local->fbr[0]->real_physaddr >> 32),
&rx_dma->fbr0_base_hi);
- writel((u32) rx_local->fbr0_real_physaddr, &rx_dma->fbr0_base_lo);
- writel(rx_local->fbr0_num_entries - 1, &rx_dma->fbr0_num_des);
+ writel((u32) rx_local->fbr[0]->real_physaddr, &rx_dma->fbr0_base_lo);
+ writel(rx_local->fbr[0]->num_entries - 1, &rx_dma->fbr0_num_des);
writel(ET_DMA10_WRAP, &rx_dma->fbr0_full_offset);
/* This variable tracks the free buffer ring 0 full position, so it
* has to match the above.
*/
- rx_local->local_fbr0_full = ET_DMA10_WRAP;
+ rx_local->fbr[0]->local_full = ET_DMA10_WRAP;
writel(
- ((rx_local->fbr0_num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
+ ((rx_local->fbr[0]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
&rx_dma->fbr0_min_des);
#endif
@@ -2550,15 +2536,15 @@ static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
*/
if (
#ifdef USE_FBR0
- (ring_index == 0 && buff_index < rx_local->fbr0_num_entries) ||
+ (ring_index == 0 && buff_index < rx_local->fbr[0]->num_entries) ||
#endif
- (ring_index == 1 && buff_index < rx_local->fbr1_num_entries)) {
+ (ring_index == 1 && buff_index < rx_local->fbr[1]->num_entries)) {
spin_lock_irqsave(&adapter->fbr_lock, flags);
if (ring_index == 1) {
struct fbr_desc *next =
- (struct fbr_desc *) (rx_local->fbr1_ring_virtaddr) +
- INDEX10(rx_local->local_fbr1_full);
+ (struct fbr_desc *) (rx_local->fbr[1]->ring_virtaddr) +
+ INDEX10(rx_local->fbr[1]->local_full);
/* Handle the Free Buffer Ring advancement here. Write
* the PA / Buffer Index for the returned buffer into
@@ -2568,15 +2554,15 @@ static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
next->addr_lo = rx_local->fbr[1]->bus_low[buff_index];
next->word2 = buff_index;
- writel(bump_free_buff_ring(&rx_local->local_fbr1_full,
- rx_local->fbr1_num_entries - 1),
+ writel(bump_free_buff_ring(&rx_local->fbr[1]->local_full,
+ rx_local->fbr[1]->num_entries - 1),
&rx_dma->fbr1_full_offset);
}
#ifdef USE_FBR0
else {
struct fbr_desc *next = (struct fbr_desc *)
- rx_local->fbr0_ring_virtaddr +
- INDEX10(rx_local->local_fbr0_full);
+ rx_local->fbr[0]->ring_virtaddr +
+ INDEX10(rx_local->fbr[0]->local_full);
/* Handle the Free Buffer Ring advancement here. Write
* the PA / Buffer Index for the returned buffer into
@@ -2586,8 +2572,9 @@ static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
next->addr_lo = rx_local->fbr[0]->bus_low[buff_index];
next->word2 = buff_index;
- writel(bump_free_buff_ring(&rx_local->local_fbr0_full,
- rx_local->fbr0_num_entries - 1),
+ writel(bump_free_buff_ring(
+ &rx_local->fbr[0]->local_full,
+ rx_local->fbr[0]->num_entries - 1),
&rx_dma->fbr0_full_offset);
}
#endif
@@ -2637,19 +2624,19 @@ void et131x_rx_dma_enable(struct et131x_adapter *adapter)
/* Setup the receive dma configuration register for normal operation */
u32 csr = 0x2000; /* FBR1 enable */
- if (adapter->rx_ring.fbr1_buffsize == 4096)
+ if (adapter->rx_ring.fbr[1]->buffsize == 4096)
csr |= 0x0800;
- else if (adapter->rx_ring.fbr1_buffsize == 8192)
+ else if (adapter->rx_ring.fbr[1]->buffsize == 8192)
csr |= 0x1000;
- else if (adapter->rx_ring.fbr1_buffsize == 16384)
+ else if (adapter->rx_ring.fbr[1]->buffsize == 16384)
csr |= 0x1800;
#ifdef USE_FBR0
csr |= 0x0400; /* FBR0 enable */
- if (adapter->rx_ring.fbr0_buffsize == 256)
+ if (adapter->rx_ring.fbr[0]->buffsize == 256)
csr |= 0x0100;
- else if (adapter->rx_ring.fbr0_buffsize == 512)
+ else if (adapter->rx_ring.fbr[0]->buffsize == 512)
csr |= 0x0200;
- else if (adapter->rx_ring.fbr0_buffsize == 1024)
+ else if (adapter->rx_ring.fbr[0]->buffsize == 1024)
csr |= 0x0300;
#endif
writel(csr, &adapter->regs->rxdma.csr);
@@ -2750,11 +2737,11 @@ static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
#ifdef USE_FBR0
if (ring_index > 1 ||
(ring_index == 0 &&
- buff_index > rx_local->fbr0_num_entries - 1) ||
+ buff_index > rx_local->fbr[0]->num_entries - 1) ||
(ring_index == 1 &&
- buff_index > rx_local->fbr1_num_entries - 1))
+ buff_index > rx_local->fbr[1]->num_entries - 1))
#else
- if (ring_index != 1 || buff_index > rx_local->fbr1_num_entries - 1)
+ if (ring_index != 1 || buff_index > rx_local->fbr[1]->num_entries - 1)
#endif
{
/* Illegal buffer or ring index cannot be used by S/W*/
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: Fix issues when USE_FBR0 is not defined
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
` (9 preceding siblings ...)
2011-10-19 23:01 ` staging: et131x: Make rx_ring.fbr{0,1} share a common structure Mark Einon
@ 2011-10-19 23:01 ` Mark Einon
2011-10-19 23:01 ` staging: et131x: use dma_alloc... instead of pci_alloc Mark Einon
` (5 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:01 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
* Following on from making rx_ring.fbr use a common structure - reversed
the fbr[] array indicies so that index 1 = FBR0 and index 0 = FBR1,
which allows USE_FBR0 define to work.
* Also fixed up minor issues where indexes into the array were out of
bounds in some places.
* Removed rx_ring.fbr common stuct TODO item from README
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/README | 1 -
drivers/staging/et131x/et131x.c | 304 ++++++++++++++++++++-------------------
2 files changed, 158 insertions(+), 147 deletions(-)
diff --git a/drivers/staging/et131x/README b/drivers/staging/et131x/README
index a7b33dc..1e0fcf4 100644
--- a/drivers/staging/et131x/README
+++ b/drivers/staging/et131x/README
@@ -8,7 +8,6 @@ Note, the powermanagement options were removed from the vendor provided
driver as they did not build properly at the time.
TODO:
- - rx_ring.fbr{0, 1} can probably share a common structure
- Use of kmem_cache seems a bit unusual
- Use dma_alloc_... in place of pci_alloc_...
- It's too late stopping the tx queue when there is no room for the current packet. The condition should be detected for the next packet.
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 0bc3e04..0fbb77d 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -322,10 +322,14 @@ struct fbr_lookup {
/*
* struct rx_ring is the sructure representing the adaptor's local
* reference(s) to the rings
+ *
+ ******************************************************************************
+ * IMPORTANT NOTE :- fbr_lookup *fbr[NUM_FBRS] uses index 0 to refer to FBR1
+ * and index 1 to refer to FRB0
+ ******************************************************************************
*/
struct rx_ring {
struct fbr_lookup *fbr[NUM_FBRS];
-
void *ps_ring_virtaddr;
dma_addr_t ps_ring_physaddr;
u32 local_psr_full;
@@ -1907,9 +1911,9 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
/* Alloc memory for the lookup table */
#ifdef USE_FBR0
- rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
-#endif
rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
+#endif
+ rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
/* The first thing we will do is configure the sizes of the buffer
* rings. These will change based on jumbo packet support. Larger
@@ -1931,40 +1935,40 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
if (adapter->registry_jumbo_packet < 2048) {
#ifdef USE_FBR0
- rx_ring->fbr[0]->buffsize = 256;
- rx_ring->fbr[0]->num_entries = 512;
-#endif
- rx_ring->fbr[1]->buffsize = 2048;
+ rx_ring->fbr[1]->buffsize = 256;
rx_ring->fbr[1]->num_entries = 512;
+#endif
+ rx_ring->fbr[0]->buffsize = 2048;
+ rx_ring->fbr[0]->num_entries = 512;
} else if (adapter->registry_jumbo_packet < 4096) {
#ifdef USE_FBR0
- rx_ring->fbr[0]->buffsize = 512;
- rx_ring->fbr[0]->num_entries = 1024;
+ rx_ring->fbr[1]->buffsize = 512;
+ rx_ring->fbr[1]->num_entries = 1024;
#endif
- rx_ring->fbr[1]->buffsize = 4096;
- rx_ring->fbr[1]->num_entries = 512;
+ rx_ring->fbr[0]->buffsize = 4096;
+ rx_ring->fbr[0]->num_entries = 512;
} else {
#ifdef USE_FBR0
- rx_ring->fbr[0]->buffsize = 1024;
- rx_ring->fbr[0]->num_entries = 768;
+ rx_ring->fbr[1]->buffsize = 1024;
+ rx_ring->fbr[1]->num_entries = 768;
#endif
- rx_ring->fbr[1]->buffsize = 16384;
- rx_ring->fbr[1]->num_entries = 128;
+ rx_ring->fbr[0]->buffsize = 16384;
+ rx_ring->fbr[0]->num_entries = 128;
}
#ifdef USE_FBR0
- adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr[0]->num_entries +
- adapter->rx_ring.fbr[1]->num_entries;
+ adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr[1]->num_entries +
+ adapter->rx_ring.fbr[0]->num_entries;
#else
- adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr[1]->num_entries;
+ adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr[0]->num_entries;
#endif
/* Allocate an area of memory for Free Buffer Ring 1 */
- bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries) + 0xfff;
- rx_ring->fbr[1]->ring_virtaddr = pci_alloc_consistent(adapter->pdev,
+ bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries) + 0xfff;
+ rx_ring->fbr[0]->ring_virtaddr = pci_alloc_consistent(adapter->pdev,
bufsize,
- &rx_ring->fbr[1]->ring_physaddr);
- if (!rx_ring->fbr[1]->ring_virtaddr) {
+ &rx_ring->fbr[0]->ring_physaddr);
+ if (!rx_ring->fbr[0]->ring_virtaddr) {
dev_err(&adapter->pdev->dev,
"Cannot alloc memory for Free Buffer Ring 1\n");
return -ENOMEM;
@@ -1977,24 +1981,24 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
* are ever returned, make sure the high part is retrieved here
* before storing the adjusted address.
*/
- rx_ring->fbr[1]->real_physaddr = rx_ring->fbr[1]->ring_physaddr;
+ rx_ring->fbr[0]->real_physaddr = rx_ring->fbr[0]->ring_physaddr;
/* Align Free Buffer Ring 1 on a 4K boundary */
et131x_align_allocated_memory(adapter,
- &rx_ring->fbr[1]->real_physaddr,
- &rx_ring->fbr[1]->offset, 0x0FFF);
+ &rx_ring->fbr[0]->real_physaddr,
+ &rx_ring->fbr[0]->offset, 0x0FFF);
- rx_ring->fbr[1]->ring_virtaddr =
- (void *)((u8 *) rx_ring->fbr[1]->ring_virtaddr +
- rx_ring->fbr[1]->offset);
+ rx_ring->fbr[0]->ring_virtaddr =
+ (void *)((u8 *) rx_ring->fbr[0]->ring_virtaddr +
+ rx_ring->fbr[0]->offset);
#ifdef USE_FBR0
/* Allocate an area of memory for Free Buffer Ring 0 */
- bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries) + 0xfff;
- rx_ring->fbr[0]->ring_virtaddr = pci_alloc_consistent(adapter->pdev,
+ bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries) + 0xfff;
+ rx_ring->fbr[1]->ring_virtaddr = pci_alloc_consistent(adapter->pdev,
bufsize,
- &rx_ring->fbr[0]->ring_physaddr);
- if (!rx_ring->fbr[0]->ring_virtaddr) {
+ &rx_ring->fbr[1]->ring_physaddr);
+ if (!rx_ring->fbr[1]->ring_virtaddr) {
dev_err(&adapter->pdev->dev,
"Cannot alloc memory for Free Buffer Ring 0\n");
return -ENOMEM;
@@ -2007,18 +2011,18 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
* are ever returned, make sure the high part is retrieved here before
* storing the adjusted address.
*/
- rx_ring->fbr[0]->real_physaddr = rx_ring->fbr[0]->ring_physaddr;
+ rx_ring->fbr[1]->real_physaddr = rx_ring->fbr[1]->ring_physaddr;
/* Align Free Buffer Ring 0 on a 4K boundary */
et131x_align_allocated_memory(adapter,
- &rx_ring->fbr[0]->real_physaddr,
- &rx_ring->fbr[0]->offset, 0x0FFF);
+ &rx_ring->fbr[1]->real_physaddr,
+ &rx_ring->fbr[1]->offset, 0x0FFF);
- rx_ring->fbr[0]->ring_virtaddr =
- (void *)((u8 *) rx_ring->fbr[0]->ring_virtaddr +
- rx_ring->fbr[0]->offset);
+ rx_ring->fbr[1]->ring_virtaddr =
+ (void *)((u8 *) rx_ring->fbr[1]->ring_virtaddr +
+ rx_ring->fbr[1]->offset);
#endif
- for (i = 0; i < (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); i++) {
+ for (i = 0; i < (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); i++) {
u64 fbr1_offset;
u64 fbr1_tmp_physaddr;
u32 fbr1_align;
@@ -2030,25 +2034,25 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
* the size of FBR0. By allocating N buffers at once, we
* reduce this overhead.
*/
- if (rx_ring->fbr[1]->buffsize > 4096)
+ if (rx_ring->fbr[0]->buffsize > 4096)
fbr1_align = 4096;
else
- fbr1_align = rx_ring->fbr[1]->buffsize;
+ fbr1_align = rx_ring->fbr[0]->buffsize;
fbr_chunksize =
- (FBR_CHUNKS * rx_ring->fbr[1]->buffsize) + fbr1_align - 1;
- rx_ring->fbr[1]->mem_virtaddrs[i] =
+ (FBR_CHUNKS * rx_ring->fbr[0]->buffsize) + fbr1_align - 1;
+ rx_ring->fbr[0]->mem_virtaddrs[i] =
pci_alloc_consistent(adapter->pdev, fbr_chunksize,
- &rx_ring->fbr[1]->mem_physaddrs[i]);
+ &rx_ring->fbr[0]->mem_physaddrs[i]);
- if (!rx_ring->fbr[1]->mem_virtaddrs[i]) {
+ if (!rx_ring->fbr[0]->mem_virtaddrs[i]) {
dev_err(&adapter->pdev->dev,
"Could not alloc memory\n");
return -ENOMEM;
}
/* See NOTE in "Save Physical Address" comment above */
- fbr1_tmp_physaddr = rx_ring->fbr[1]->mem_physaddrs[i];
+ fbr1_tmp_physaddr = rx_ring->fbr[0]->mem_physaddrs[i];
et131x_align_allocated_memory(adapter,
&fbr1_tmp_physaddr,
@@ -2060,71 +2064,71 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
/* Save the Virtual address of this index for quick
* access later
*/
- rx_ring->fbr[1]->virt[index] =
- (u8 *) rx_ring->fbr[1]->mem_virtaddrs[i] +
- (j * rx_ring->fbr[1]->buffsize) + fbr1_offset;
+ rx_ring->fbr[0]->virt[index] =
+ (u8 *) rx_ring->fbr[0]->mem_virtaddrs[i] +
+ (j * rx_ring->fbr[0]->buffsize) + fbr1_offset;
/* now store the physical address in the descriptor
* so the device can access it
*/
- rx_ring->fbr[1]->bus_high[index] =
+ rx_ring->fbr[0]->bus_high[index] =
(u32) (fbr1_tmp_physaddr >> 32);
- rx_ring->fbr[1]->bus_low[index] =
+ rx_ring->fbr[0]->bus_low[index] =
(u32) fbr1_tmp_physaddr;
- fbr1_tmp_physaddr += rx_ring->fbr[1]->buffsize;
+ fbr1_tmp_physaddr += rx_ring->fbr[0]->buffsize;
- rx_ring->fbr[1]->buffer1[index] =
- rx_ring->fbr[1]->virt[index];
- rx_ring->fbr[1]->buffer2[index] =
- rx_ring->fbr[1]->virt[index] - 4;
+ rx_ring->fbr[0]->buffer1[index] =
+ rx_ring->fbr[0]->virt[index];
+ rx_ring->fbr[0]->buffer2[index] =
+ rx_ring->fbr[0]->virt[index] - 4;
}
}
#ifdef USE_FBR0
/* Same for FBR0 (if in use) */
- for (i = 0; i < (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); i++) {
+ for (i = 0; i < (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); i++) {
u64 fbr0_offset;
u64 fbr0_tmp_physaddr;
fbr_chunksize =
- ((FBR_CHUNKS + 1) * rx_ring->fbr[0]->buffsize) - 1;
- rx_ring->fbr[0]->mem_virtaddrs[i] =
+ ((FBR_CHUNKS + 1) * rx_ring->fbr[1]->buffsize) - 1;
+ rx_ring->fbr[1]->mem_virtaddrs[i] =
pci_alloc_consistent(adapter->pdev, fbr_chunksize,
- &rx_ring->fbr[0]->mem_physaddrs[i]);
+ &rx_ring->fbr[1]->mem_physaddrs[i]);
- if (!rx_ring->fbr[0]->mem_virtaddrs[i]) {
+ if (!rx_ring->fbr[1]->mem_virtaddrs[i]) {
dev_err(&adapter->pdev->dev,
"Could not alloc memory\n");
return -ENOMEM;
}
/* See NOTE in "Save Physical Address" comment above */
- fbr0_tmp_physaddr = rx_ring->fbr[0]->mem_physaddrs[i];
+ fbr0_tmp_physaddr = rx_ring->fbr[1]->mem_physaddrs[i];
et131x_align_allocated_memory(adapter,
&fbr0_tmp_physaddr,
&fbr0_offset,
- rx_ring->fbr[0]->buffsize - 1);
+ rx_ring->fbr[1]->buffsize - 1);
for (j = 0; j < FBR_CHUNKS; j++) {
u32 index = (i * FBR_CHUNKS) + j;
- rx_ring->fbr[0]->virt[index] =
- (u8 *) rx_ring->fbr[0]->mem_virtaddrs[i] +
- (j * rx_ring->fbr[0]->buffsize) + fbr0_offset;
+ rx_ring->fbr[1]->virt[index] =
+ (u8 *) rx_ring->fbr[1]->mem_virtaddrs[i] +
+ (j * rx_ring->fbr[1]->buffsize) + fbr0_offset;
- rx_ring->fbr[0]->bus_high[index] =
+ rx_ring->fbr[1]->bus_high[index] =
(u32) (fbr0_tmp_physaddr >> 32);
- rx_ring->fbr[0]->bus_low[index] =
+ rx_ring->fbr[1]->bus_low[index] =
(u32) fbr0_tmp_physaddr;
- fbr0_tmp_physaddr += rx_ring->fbr[0]->buffsize;
+ fbr0_tmp_physaddr += rx_ring->fbr[1]->buffsize;
- rx_ring->fbr[0]->buffer1[index] =
- rx_ring->fbr[0]->virt[index];
- rx_ring->fbr[0]->buffer2[index] =
- rx_ring->fbr[0]->virt[index] - 4;
+ rx_ring->fbr[1]->buffer1[index] =
+ rx_ring->fbr[1]->virt[index];
+ rx_ring->fbr[1]->buffer2[index] =
+ rx_ring->fbr[1]->virt[index] - 4;
}
}
#endif
@@ -2214,78 +2218,78 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
}
/* Free Free Buffer Ring 1 */
- if (rx_ring->fbr[1]->ring_virtaddr) {
+ if (rx_ring->fbr[0]->ring_virtaddr) {
/* First the packet memory */
for (index = 0; index <
- (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); index++) {
- if (rx_ring->fbr[1]->mem_virtaddrs[index]) {
+ (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); index++) {
+ if (rx_ring->fbr[0]->mem_virtaddrs[index]) {
u32 fbr1_align;
- if (rx_ring->fbr[1]->buffsize > 4096)
+ if (rx_ring->fbr[0]->buffsize > 4096)
fbr1_align = 4096;
else
- fbr1_align = rx_ring->fbr[1]->buffsize;
+ fbr1_align = rx_ring->fbr[0]->buffsize;
bufsize =
- (rx_ring->fbr[1]->buffsize * FBR_CHUNKS) +
+ (rx_ring->fbr[0]->buffsize * FBR_CHUNKS) +
fbr1_align - 1;
pci_free_consistent(adapter->pdev,
bufsize,
- rx_ring->fbr[1]->mem_virtaddrs[index],
- rx_ring->fbr[1]->mem_physaddrs[index]);
+ rx_ring->fbr[0]->mem_virtaddrs[index],
+ rx_ring->fbr[0]->mem_physaddrs[index]);
- rx_ring->fbr[1]->mem_virtaddrs[index] = NULL;
+ rx_ring->fbr[0]->mem_virtaddrs[index] = NULL;
}
}
/* Now the FIFO itself */
- rx_ring->fbr[1]->ring_virtaddr = (void *)((u8 *)
- rx_ring->fbr[1]->ring_virtaddr - rx_ring->fbr[1]->offset);
+ rx_ring->fbr[0]->ring_virtaddr = (void *)((u8 *)
+ rx_ring->fbr[0]->ring_virtaddr - rx_ring->fbr[0]->offset);
- bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries)
+ bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries)
+ 0xfff;
pci_free_consistent(adapter->pdev, bufsize,
- rx_ring->fbr[1]->ring_virtaddr,
- rx_ring->fbr[1]->ring_physaddr);
+ rx_ring->fbr[0]->ring_virtaddr,
+ rx_ring->fbr[0]->ring_physaddr);
- rx_ring->fbr[1]->ring_virtaddr = NULL;
+ rx_ring->fbr[0]->ring_virtaddr = NULL;
}
#ifdef USE_FBR0
/* Now the same for Free Buffer Ring 0 */
- if (rx_ring->fbr[0]->ring_virtaddr) {
+ if (rx_ring->fbr[1]->ring_virtaddr) {
/* First the packet memory */
for (index = 0; index <
- (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); index++) {
- if (rx_ring->fbr[0]->mem_virtaddrs[index]) {
+ (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); index++) {
+ if (rx_ring->fbr[1]->mem_virtaddrs[index]) {
bufsize =
- (rx_ring->fbr[0]->buffsize *
+ (rx_ring->fbr[1]->buffsize *
(FBR_CHUNKS + 1)) - 1;
pci_free_consistent(adapter->pdev,
bufsize,
- rx_ring->fbr[0]->mem_virtaddrs[index],
- rx_ring->fbr[0]->mem_physaddrs[index]);
+ rx_ring->fbr[1]->mem_virtaddrs[index],
+ rx_ring->fbr[1]->mem_physaddrs[index]);
- rx_ring->fbr[0]->mem_virtaddrs[index] = NULL;
+ rx_ring->fbr[1]->mem_virtaddrs[index] = NULL;
}
}
/* Now the FIFO itself */
- rx_ring->fbr[0]->ring_virtaddr = (void *)((u8 *)
- rx_ring->fbr[0]->ring_virtaddr - rx_ring->fbr[0]->offset);
+ rx_ring->fbr[1]->ring_virtaddr = (void *)((u8 *)
+ rx_ring->fbr[1]->ring_virtaddr - rx_ring->fbr[1]->offset);
- bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries)
+ bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries)
+ 0xfff;
pci_free_consistent(adapter->pdev,
bufsize,
- rx_ring->fbr[0]->ring_virtaddr,
- rx_ring->fbr[0]->ring_physaddr);
+ rx_ring->fbr[1]->ring_virtaddr,
+ rx_ring->fbr[1]->ring_physaddr);
- rx_ring->fbr[0]->ring_virtaddr = NULL;
+ rx_ring->fbr[1]->ring_virtaddr = NULL;
}
#endif
@@ -2322,10 +2326,10 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
/* Free the FBR Lookup Table */
#ifdef USE_FBR0
- kfree(rx_ring->fbr[0]);
+ kfree(rx_ring->fbr[1]);
#endif
- kfree(rx_ring->fbr[1]);
+ kfree(rx_ring->fbr[0]);
/* Reset Counters */
rx_ring->num_ready_recv = 0;
@@ -2431,10 +2435,10 @@ void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
rx_local->local_psr_full = 0;
/* Now's the best time to initialize FBR1 contents */
- fbr_entry = (struct fbr_desc *) rx_local->fbr[1]->ring_virtaddr;
- for (entry = 0; entry < rx_local->fbr[1]->num_entries; entry++) {
- fbr_entry->addr_hi = rx_local->fbr[1]->bus_high[entry];
- fbr_entry->addr_lo = rx_local->fbr[1]->bus_low[entry];
+ fbr_entry = (struct fbr_desc *) rx_local->fbr[0]->ring_virtaddr;
+ for (entry = 0; entry < rx_local->fbr[0]->num_entries; entry++) {
+ fbr_entry->addr_hi = rx_local->fbr[0]->bus_high[entry];
+ fbr_entry->addr_lo = rx_local->fbr[0]->bus_low[entry];
fbr_entry->word2 = entry;
fbr_entry++;
}
@@ -2442,42 +2446,42 @@ void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
/* Set the address and parameters of Free buffer ring 1 (and 0 if
* required) into the 1310's registers
*/
- writel((u32) (rx_local->fbr[1]->real_physaddr >> 32),
+ writel((u32) (rx_local->fbr[0]->real_physaddr >> 32),
&rx_dma->fbr1_base_hi);
- writel((u32) rx_local->fbr[1]->real_physaddr, &rx_dma->fbr1_base_lo);
- writel(rx_local->fbr[1]->num_entries - 1, &rx_dma->fbr1_num_des);
+ writel((u32) rx_local->fbr[0]->real_physaddr, &rx_dma->fbr1_base_lo);
+ writel(rx_local->fbr[0]->num_entries - 1, &rx_dma->fbr1_num_des);
writel(ET_DMA10_WRAP, &rx_dma->fbr1_full_offset);
/* This variable tracks the free buffer ring 1 full position, so it
* has to match the above.
*/
- rx_local->fbr[1]->local_full = ET_DMA10_WRAP;
+ rx_local->fbr[0]->local_full = ET_DMA10_WRAP;
writel(
- ((rx_local->fbr[1]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
+ ((rx_local->fbr[0]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
&rx_dma->fbr1_min_des);
#ifdef USE_FBR0
/* Now's the best time to initialize FBR0 contents */
- fbr_entry = (struct fbr_desc *) rx_local->fbr[0]->ring_virtaddr;
- for (entry = 0; entry < rx_local->fbr[0]->num_entries; entry++) {
- fbr_entry->addr_hi = rx_local->fbr[0]->bus_high[entry];
- fbr_entry->addr_lo = rx_local->fbr[0]->bus_low[entry];
+ fbr_entry = (struct fbr_desc *) rx_local->fbr[1]->ring_virtaddr;
+ for (entry = 0; entry < rx_local->fbr[1]->num_entries; entry++) {
+ fbr_entry->addr_hi = rx_local->fbr[1]->bus_high[entry];
+ fbr_entry->addr_lo = rx_local->fbr[1]->bus_low[entry];
fbr_entry->word2 = entry;
fbr_entry++;
}
- writel((u32) (rx_local->fbr[0]->real_physaddr >> 32),
+ writel((u32) (rx_local->fbr[1]->real_physaddr >> 32),
&rx_dma->fbr0_base_hi);
- writel((u32) rx_local->fbr[0]->real_physaddr, &rx_dma->fbr0_base_lo);
- writel(rx_local->fbr[0]->num_entries - 1, &rx_dma->fbr0_num_des);
+ writel((u32) rx_local->fbr[1]->real_physaddr, &rx_dma->fbr0_base_lo);
+ writel(rx_local->fbr[1]->num_entries - 1, &rx_dma->fbr0_num_des);
writel(ET_DMA10_WRAP, &rx_dma->fbr0_full_offset);
/* This variable tracks the free buffer ring 0 full position, so it
* has to match the above.
*/
- rx_local->fbr[0]->local_full = ET_DMA10_WRAP;
+ rx_local->fbr[1]->local_full = ET_DMA10_WRAP;
writel(
- ((rx_local->fbr[0]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
+ ((rx_local->fbr[1]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
&rx_dma->fbr0_min_des);
#endif
@@ -2536,45 +2540,45 @@ static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
*/
if (
#ifdef USE_FBR0
- (ring_index == 0 && buff_index < rx_local->fbr[0]->num_entries) ||
+ (ring_index == 0 && buff_index < rx_local->fbr[1]->num_entries) ||
#endif
- (ring_index == 1 && buff_index < rx_local->fbr[1]->num_entries)) {
+ (ring_index == 1 && buff_index < rx_local->fbr[0]->num_entries)) {
spin_lock_irqsave(&adapter->fbr_lock, flags);
if (ring_index == 1) {
struct fbr_desc *next =
- (struct fbr_desc *) (rx_local->fbr[1]->ring_virtaddr) +
- INDEX10(rx_local->fbr[1]->local_full);
+ (struct fbr_desc *) (rx_local->fbr[0]->ring_virtaddr) +
+ INDEX10(rx_local->fbr[0]->local_full);
/* Handle the Free Buffer Ring advancement here. Write
* the PA / Buffer Index for the returned buffer into
* the oldest (next to be freed)FBR entry
*/
- next->addr_hi = rx_local->fbr[1]->bus_high[buff_index];
- next->addr_lo = rx_local->fbr[1]->bus_low[buff_index];
+ next->addr_hi = rx_local->fbr[0]->bus_high[buff_index];
+ next->addr_lo = rx_local->fbr[0]->bus_low[buff_index];
next->word2 = buff_index;
- writel(bump_free_buff_ring(&rx_local->fbr[1]->local_full,
- rx_local->fbr[1]->num_entries - 1),
+ writel(bump_free_buff_ring(&rx_local->fbr[0]->local_full,
+ rx_local->fbr[0]->num_entries - 1),
&rx_dma->fbr1_full_offset);
}
#ifdef USE_FBR0
else {
struct fbr_desc *next = (struct fbr_desc *)
- rx_local->fbr[0]->ring_virtaddr +
- INDEX10(rx_local->fbr[0]->local_full);
+ rx_local->fbr[1]->ring_virtaddr +
+ INDEX10(rx_local->fbr[1]->local_full);
/* Handle the Free Buffer Ring advancement here. Write
* the PA / Buffer Index for the returned buffer into
* the oldest (next to be freed) FBR entry
*/
- next->addr_hi = rx_local->fbr[0]->bus_high[buff_index];
- next->addr_lo = rx_local->fbr[0]->bus_low[buff_index];
+ next->addr_hi = rx_local->fbr[1]->bus_high[buff_index];
+ next->addr_lo = rx_local->fbr[1]->bus_low[buff_index];
next->word2 = buff_index;
writel(bump_free_buff_ring(
- &rx_local->fbr[0]->local_full,
- rx_local->fbr[0]->num_entries - 1),
+ &rx_local->fbr[1]->local_full,
+ rx_local->fbr[1]->num_entries - 1),
&rx_dma->fbr0_full_offset);
}
#endif
@@ -2624,19 +2628,19 @@ void et131x_rx_dma_enable(struct et131x_adapter *adapter)
/* Setup the receive dma configuration register for normal operation */
u32 csr = 0x2000; /* FBR1 enable */
- if (adapter->rx_ring.fbr[1]->buffsize == 4096)
+ if (adapter->rx_ring.fbr[0]->buffsize == 4096)
csr |= 0x0800;
- else if (adapter->rx_ring.fbr[1]->buffsize == 8192)
+ else if (adapter->rx_ring.fbr[0]->buffsize == 8192)
csr |= 0x1000;
- else if (adapter->rx_ring.fbr[1]->buffsize == 16384)
+ else if (adapter->rx_ring.fbr[0]->buffsize == 16384)
csr |= 0x1800;
#ifdef USE_FBR0
csr |= 0x0400; /* FBR0 enable */
- if (adapter->rx_ring.fbr[0]->buffsize == 256)
+ if (adapter->rx_ring.fbr[1]->buffsize == 256)
csr |= 0x0100;
- else if (adapter->rx_ring.fbr[0]->buffsize == 512)
+ else if (adapter->rx_ring.fbr[1]->buffsize == 512)
csr |= 0x0200;
- else if (adapter->rx_ring.fbr[0]->buffsize == 1024)
+ else if (adapter->rx_ring.fbr[1]->buffsize == 1024)
csr |= 0x0300;
#endif
writel(csr, &adapter->regs->rxdma.csr);
@@ -2737,11 +2741,11 @@ static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
#ifdef USE_FBR0
if (ring_index > 1 ||
(ring_index == 0 &&
- buff_index > rx_local->fbr[0]->num_entries - 1) ||
+ buff_index > rx_local->fbr[1]->num_entries - 1) ||
(ring_index == 1 &&
- buff_index > rx_local->fbr[1]->num_entries - 1))
+ buff_index > rx_local->fbr[0]->num_entries - 1))
#else
- if (ring_index != 1 || buff_index > rx_local->fbr[1]->num_entries - 1)
+ if (ring_index != 1 || buff_index > rx_local->fbr[0]->num_entries - 1)
#endif
{
/* Illegal buffer or ring index cannot be used by S/W*/
@@ -2800,7 +2804,11 @@ static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
ET131X_PACKET_TYPE_PROMISCUOUS)
&& !(adapter->packet_filter &
ET131X_PACKET_TYPE_ALL_MULTICAST)) {
- buf = rx_local->fbr[ring_index]->
+ /*
+ * Note - ring_index for fbr[] array is reversed
+ * 1 for FBR0 etc
+ */
+ buf = rx_local->fbr[(ring_index == 0 ? 1 : 0)]->
virt[buff_index];
/* Loop through our list to see if the
@@ -2865,8 +2873,12 @@ static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
adapter->net_stats.rx_bytes += rfd->len;
+ /*
+ * Note - ring_index for fbr[] array is reversed,
+ * 1 for FBR0 etc
+ */
memcpy(skb_put(skb, rfd->len),
- rx_local->fbr[ring_index]->virt[buff_index],
+ rx_local->fbr[(ring_index == 0 ? 1 : 0)]->virt[buff_index],
rfd->len);
skb->dev = adapter->netdev;
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: use dma_alloc... instead of pci_alloc...
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
` (10 preceding siblings ...)
2011-10-19 23:01 ` staging: et131x: Fix issues when USE_FBR0 is not defined Mark Einon
@ 2011-10-19 23:01 ` Mark Einon
2011-10-19 23:01 ` staging: et131x: Match dma_alloc_ calls with dma_free_ calls Mark Einon
` (4 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:01 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
Use dma_allocs instead of pci_allocs, so we can use GFP_KERNEL
allocations.
Also removed this item from the TODO list
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/README | 1 -
drivers/staging/et131x/et131x.c | 39 ++++++++++++++++++++++-----------------
2 files changed, 22 insertions(+), 18 deletions(-)
diff --git a/drivers/staging/et131x/README b/drivers/staging/et131x/README
index 1e0fcf4..87b9360 100644
--- a/drivers/staging/et131x/README
+++ b/drivers/staging/et131x/README
@@ -9,7 +9,6 @@ driver as they did not build properly at the time.
TODO:
- Use of kmem_cache seems a bit unusual
- - Use dma_alloc_... in place of pci_alloc_...
- It's too late stopping the tx queue when there is no room for the current packet. The condition should be detected for the next packet.
- PCI_VDEVICE ?
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 0fbb77d..06ba4a9 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -1965,9 +1965,10 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
/* Allocate an area of memory for Free Buffer Ring 1 */
bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries) + 0xfff;
- rx_ring->fbr[0]->ring_virtaddr = pci_alloc_consistent(adapter->pdev,
- bufsize,
- &rx_ring->fbr[0]->ring_physaddr);
+ rx_ring->fbr[0]->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
+ bufsize,
+ &rx_ring->fbr[0]->ring_physaddr,
+ GFP_KERNEL);
if (!rx_ring->fbr[0]->ring_virtaddr) {
dev_err(&adapter->pdev->dev,
"Cannot alloc memory for Free Buffer Ring 1\n");
@@ -1995,9 +1996,10 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
#ifdef USE_FBR0
/* Allocate an area of memory for Free Buffer Ring 0 */
bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries) + 0xfff;
- rx_ring->fbr[1]->ring_virtaddr = pci_alloc_consistent(adapter->pdev,
+ rx_ring->fbr[1]->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
bufsize,
- &rx_ring->fbr[1]->ring_physaddr);
+ &rx_ring->fbr[1]->ring_physaddr,
+ GFP_KERNEL);
if (!rx_ring->fbr[1]->ring_virtaddr) {
dev_err(&adapter->pdev->dev,
"Cannot alloc memory for Free Buffer Ring 0\n");
@@ -2042,8 +2044,8 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
fbr_chunksize =
(FBR_CHUNKS * rx_ring->fbr[0]->buffsize) + fbr1_align - 1;
rx_ring->fbr[0]->mem_virtaddrs[i] =
- pci_alloc_consistent(adapter->pdev, fbr_chunksize,
- &rx_ring->fbr[0]->mem_physaddrs[i]);
+ dma_alloc_coherent(&adapter->pdev->dev, fbr_chunksize,
+ &rx_ring->fbr[0]->mem_physaddrs[i], GFP_KERNEL);
if (!rx_ring->fbr[0]->mem_virtaddrs[i]) {
dev_err(&adapter->pdev->dev,
@@ -2094,8 +2096,8 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
fbr_chunksize =
((FBR_CHUNKS + 1) * rx_ring->fbr[1]->buffsize) - 1;
rx_ring->fbr[1]->mem_virtaddrs[i] =
- pci_alloc_consistent(adapter->pdev, fbr_chunksize,
- &rx_ring->fbr[1]->mem_physaddrs[i]);
+ dma_alloc_coherent(&adapter->pdev->dev, fbr_chunksize,
+ &rx_ring->fbr[1]->mem_physaddrs[i], GFP_KERNEL);
if (!rx_ring->fbr[1]->mem_virtaddrs[i]) {
dev_err(&adapter->pdev->dev,
@@ -2137,9 +2139,10 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
pktstat_ringsize =
sizeof(struct pkt_stat_desc) * adapter->rx_ring.psr_num_entries;
- rx_ring->ps_ring_virtaddr = pci_alloc_consistent(adapter->pdev,
+ rx_ring->ps_ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
pktstat_ringsize,
- &rx_ring->ps_ring_physaddr);
+ &rx_ring->ps_ring_physaddr,
+ GFP_KERNEL);
if (!rx_ring->ps_ring_virtaddr) {
dev_err(&adapter->pdev->dev,
@@ -2157,9 +2160,10 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
*/
/* Allocate an area of memory for writeback of status information */
- rx_ring->rx_status_block = pci_alloc_consistent(adapter->pdev,
+ rx_ring->rx_status_block = dma_alloc_coherent(&adapter->pdev->dev,
sizeof(struct rx_status_block),
- &rx_ring->rx_status_bus);
+ &rx_ring->rx_status_bus,
+ GFP_KERNEL);
if (!rx_ring->rx_status_block) {
dev_err(&adapter->pdev->dev,
"Cannot alloc memory for Status Block\n");
@@ -2992,8 +2996,8 @@ int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
*/
desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX) + 4096 - 1;
tx_ring->tx_desc_ring =
- (struct tx_desc *) pci_alloc_consistent(adapter->pdev, desc_size,
- &tx_ring->tx_desc_ring_pa);
+ (struct tx_desc *) dma_alloc_coherent(&adapter->pdev->dev, desc_size,
+ &tx_ring->tx_desc_ring_pa, GFP_KERNEL);
if (!adapter->tx_ring.tx_desc_ring) {
dev_err(&adapter->pdev->dev,
"Cannot alloc memory for Tx Ring\n");
@@ -3008,9 +3012,10 @@ int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
* storing the adjusted address.
*/
/* Allocate memory for the Tx status block */
- tx_ring->tx_status = pci_alloc_consistent(adapter->pdev,
+ tx_ring->tx_status = dma_alloc_coherent(&adapter->pdev->dev,
sizeof(u32),
- &tx_ring->tx_status_pa);
+ &tx_ring->tx_status_pa,
+ GFP_KERNEL);
if (!adapter->tx_ring.tx_status_pa) {
dev_err(&adapter->pdev->dev,
"Cannot alloc memory for Tx status block\n");
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: Match dma_alloc_ calls with dma_free_ calls
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
` (11 preceding siblings ...)
2011-10-19 23:01 ` staging: et131x: use dma_alloc... instead of pci_alloc Mark Einon
@ 2011-10-19 23:01 ` Mark Einon
2011-10-19 23:01 ` staging: et131x: Tidy up PCI device table definition Mark Einon
` (3 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:01 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
Previous update was to replace pci_alloc with dma_alloc calls. I missed
replacing the corresponding pci_free_ calls with the dma versions. Now
done. Thanks to Denis Kirjanov <kirjanov@gmail.com> for pointing this
out.
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/et131x.c | 16 ++++++++--------
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 06ba4a9..28d54b3 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -2238,7 +2238,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
(rx_ring->fbr[0]->buffsize * FBR_CHUNKS) +
fbr1_align - 1;
- pci_free_consistent(adapter->pdev,
+ dma_free_coherent(&adapter->pdev->dev,
bufsize,
rx_ring->fbr[0]->mem_virtaddrs[index],
rx_ring->fbr[0]->mem_physaddrs[index]);
@@ -2254,7 +2254,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries)
+ 0xfff;
- pci_free_consistent(adapter->pdev, bufsize,
+ dma_free_coherent(&adapter->pdev->dev, bufsize,
rx_ring->fbr[0]->ring_virtaddr,
rx_ring->fbr[0]->ring_physaddr);
@@ -2272,7 +2272,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
(rx_ring->fbr[1]->buffsize *
(FBR_CHUNKS + 1)) - 1;
- pci_free_consistent(adapter->pdev,
+ dma_free_coherent(&adapter->pdev->dev,
bufsize,
rx_ring->fbr[1]->mem_virtaddrs[index],
rx_ring->fbr[1]->mem_physaddrs[index]);
@@ -2288,7 +2288,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries)
+ 0xfff;
- pci_free_consistent(adapter->pdev,
+ dma_free_coherent(&adapter->pdev->dev,
bufsize,
rx_ring->fbr[1]->ring_virtaddr,
rx_ring->fbr[1]->ring_physaddr);
@@ -2303,7 +2303,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
sizeof(struct pkt_stat_desc) *
adapter->rx_ring.psr_num_entries;
- pci_free_consistent(adapter->pdev, pktstat_ringsize,
+ dma_free_coherent(&adapter->pdev->dev, pktstat_ringsize,
rx_ring->ps_ring_virtaddr,
rx_ring->ps_ring_physaddr);
@@ -2312,7 +2312,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
/* Free area of memory for the writeback of status information */
if (rx_ring->rx_status_block) {
- pci_free_consistent(adapter->pdev,
+ dma_free_coherent(&adapter->pdev->dev,
sizeof(struct rx_status_block),
rx_ring->rx_status_block, rx_ring->rx_status_bus);
rx_ring->rx_status_block = NULL;
@@ -3038,7 +3038,7 @@ void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
/* Free memory relating to Tx rings here */
desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX)
+ 4096 - 1;
- pci_free_consistent(adapter->pdev,
+ dma_free_coherent(&adapter->pdev->dev,
desc_size,
adapter->tx_ring.tx_desc_ring,
adapter->tx_ring.tx_desc_ring_pa);
@@ -3047,7 +3047,7 @@ void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
/* Free memory for the Tx status block */
if (adapter->tx_ring.tx_status) {
- pci_free_consistent(adapter->pdev,
+ dma_free_coherent(&adapter->pdev->dev,
sizeof(u32),
adapter->tx_ring.tx_status,
adapter->tx_ring.tx_status_pa);
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: Tidy up PCI device table definition
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
` (12 preceding siblings ...)
2011-10-19 23:01 ` staging: et131x: Match dma_alloc_ calls with dma_free_ calls Mark Einon
@ 2011-10-19 23:01 ` Mark Einon
2011-10-19 23:01 ` staging: et131x: on transmit, stop the queue if the next packet will fail Mark Einon
` (2 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:01 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
Used the convenience macros DEFINE_PCI_DEVICE_TABLE and PCI_VDEVICE to
tidy up the device table definition.
Also remove the corresponding TODO item from the README.
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/README | 1 -
drivers/staging/et131x/et131x.c | 12 ++++--------
2 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/et131x/README b/drivers/staging/et131x/README
index 87b9360..0928eb5 100644
--- a/drivers/staging/et131x/README
+++ b/drivers/staging/et131x/README
@@ -10,7 +10,6 @@ driver as they did not build properly at the time.
TODO:
- Use of kmem_cache seems a bit unusual
- It's too late stopping the tx queue when there is no room for the current packet. The condition should be detected for the next packet.
- - PCI_VDEVICE ?
Please send patches to:
Greg Kroah-Hartman <gregkh@suse.de>
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 28d54b3..cc41111 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -169,8 +169,7 @@ MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver "
#define ET1310_PCI_REPLAY 0xC2
#define ET1310_PCI_L0L1LATENCY 0xCF
-/* PCI Vendor/Product IDs */
-#define ET131X_PCI_VENDOR_ID 0x11C1 /* Agere Systems */
+/* PCI Product IDs */
#define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
#define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
@@ -4647,14 +4646,11 @@ static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume);
#define ET131X_PM_OPS NULL
#endif
-static struct pci_device_id et131x_pci_table[] __devinitdata = {
- {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_GIG, PCI_ANY_ID,
- PCI_ANY_ID, 0, 0, 0UL},
- {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_FAST, PCI_ANY_ID,
- PCI_ANY_ID, 0, 0, 0UL},
+static DEFINE_PCI_DEVICE_TABLE(et131x_pci_table) = {
+ { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_GIG), 0UL},
+ { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_FAST), 0UL},
{0,}
};
-
MODULE_DEVICE_TABLE(pci, et131x_pci_table);
static struct pci_driver et131x_driver = {
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: on transmit, stop the queue if the next packet will fail
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
` (13 preceding siblings ...)
2011-10-19 23:01 ` staging: et131x: Tidy up PCI device table definition Mark Einon
@ 2011-10-19 23:01 ` Mark Einon
2011-10-19 23:01 ` staging: et131x: Convert rest of pci memory management to dma api Mark Einon
2011-10-19 23:01 ` staging: et131x: Remove unused defines Mark Einon
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:01 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
* Currently the tx queue is only stopped when the current packet fails.
Check if the next packet will fail, and stop the queue if so.
* Removed associated item from TODO list in the README.
* Also minor fixup as adapter was being declared as null and immediately set
to a value.
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/README | 1 -
drivers/staging/et131x/et131x.c | 13 ++++++-------
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/staging/et131x/README b/drivers/staging/et131x/README
index 0928eb5..3458aa7 100644
--- a/drivers/staging/et131x/README
+++ b/drivers/staging/et131x/README
@@ -9,7 +9,6 @@ driver as they did not build properly at the time.
TODO:
- Use of kmem_cache seems a bit unusual
- - It's too late stopping the tx queue when there is no room for the current packet. The condition should be detected for the next packet.
Please send patches to:
Greg Kroah-Hartman <gregkh@suse.de>
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index cc41111..993f93a 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -3448,9 +3448,7 @@ static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter)
int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
{
int status = 0;
- struct et131x_adapter *adapter = NULL;
-
- adapter = netdev_priv(netdev);
+ struct et131x_adapter *adapter = netdev_priv(netdev);
/* Send these packets
*
@@ -5347,6 +5345,11 @@ static void et131x_multicast(struct net_device *netdev)
static int et131x_tx(struct sk_buff *skb, struct net_device *netdev)
{
int status = 0;
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+
+ /* stop the queue if it's getting full */
+ if(adapter->tx_ring.used >= NUM_TCB - 1 && !netif_queue_stopped(netdev))
+ netif_stop_queue(netdev);
/* Save the timestamp for the TX timeout watchdog */
netdev->trans_start = jiffies;
@@ -5357,10 +5360,6 @@ static int et131x_tx(struct sk_buff *skb, struct net_device *netdev)
/* Check status and manage the netif queue if necessary */
if (status != 0) {
if (status == -ENOMEM) {
- /* Put the queue to sleep until resources are
- * available
- */
- netif_stop_queue(netdev);
status = NETDEV_TX_BUSY;
} else {
status = NETDEV_TX_OK;
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: Convert rest of pci memory management to dma api
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
` (14 preceding siblings ...)
2011-10-19 23:01 ` staging: et131x: on transmit, stop the queue if the next packet will fail Mark Einon
@ 2011-10-19 23:01 ` Mark Einon
2011-10-19 23:01 ` staging: et131x: Remove unused defines Mark Einon
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:01 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
Replaced pci map/unmap and set_mask calls with their dma equivalents.
Also updated comments to reflect this.
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/et131x.c | 56 +++++++++++++++++++-------------------
1 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 993f93a..1c11dfd 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -1976,7 +1976,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
/* Save physical address
*
- * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
+ * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
* ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
* are ever returned, make sure the high part is retrieved here
* before storing the adjusted address.
@@ -2007,7 +2007,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
/* Save physical address
*
- * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
+ * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
* ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
* are ever returned, make sure the high part is retrieved here before
* storing the adjusted address.
@@ -2152,7 +2152,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
(unsigned long) rx_ring->ps_ring_physaddr);
/*
- * NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
+ * NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
* ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
* are ever returned, make sure the high part is retrieved here before
* storing the adjusted address.
@@ -2172,7 +2172,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
printk(KERN_INFO "PRS %lx\n", (unsigned long)rx_ring->rx_status_bus);
/* Recv
- * pci_pool_create initializes a lookaside list. After successful
+ * kmem_cache_create initializes a lookaside list. After successful
* creation, nonpaged fixed-size blocks can be allocated from and
* freed to the lookaside list.
* RFDs will be allocated from this pool.
@@ -2408,7 +2408,7 @@ void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
/* Load the completion writeback physical address
*
- * NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
+ * NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
* ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
* are ever returned, make sure the high part is retrieved here
* before storing the adjusted address.
@@ -3005,7 +3005,7 @@ int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
/* Save physical address
*
- * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
+ * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
* ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
* are ever returned, make sure the high part is retrieved here before
* storing the adjusted address.
@@ -3202,59 +3202,59 @@ static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb)
skb->len - skb->data_len;
/* NOTE: Here, the dma_addr_t returned from
- * pci_map_single() is implicitly cast as a
+ * dma_map_single() is implicitly cast as a
* u32. Although dma_addr_t can be
* 64-bit, the address returned by
- * pci_map_single() is always 32-bit
+ * dma_map_single() is always 32-bit
* addressable (as defined by the pci/dma
* subsystem)
*/
desc[frag++].addr_lo =
- pci_map_single(adapter->pdev,
+ dma_map_single(&adapter->pdev->dev,
skb->data,
skb->len -
skb->data_len,
- PCI_DMA_TODEVICE);
+ DMA_TO_DEVICE);
} else {
desc[frag].addr_hi = 0;
desc[frag].len_vlan =
(skb->len - skb->data_len) / 2;
/* NOTE: Here, the dma_addr_t returned from
- * pci_map_single() is implicitly cast as a
+ * dma_map_single() is implicitly cast as a
* u32. Although dma_addr_t can be
* 64-bit, the address returned by
- * pci_map_single() is always 32-bit
+ * dma_map_single() is always 32-bit
* addressable (as defined by the pci/dma
* subsystem)
*/
desc[frag++].addr_lo =
- pci_map_single(adapter->pdev,
+ dma_map_single(&adapter->pdev->dev,
skb->data,
((skb->len -
skb->data_len) / 2),
- PCI_DMA_TODEVICE);
+ DMA_TO_DEVICE);
desc[frag].addr_hi = 0;
desc[frag].len_vlan =
(skb->len - skb->data_len) / 2;
/* NOTE: Here, the dma_addr_t returned from
- * pci_map_single() is implicitly cast as a
+ * dma_map_single() is implicitly cast as a
* u32. Although dma_addr_t can be
* 64-bit, the address returned by
- * pci_map_single() is always 32-bit
+ * dma_map_single() is always 32-bit
* addressable (as defined by the pci/dma
* subsystem)
*/
desc[frag++].addr_lo =
- pci_map_single(adapter->pdev,
+ dma_map_single(&adapter->pdev->dev,
skb->data +
((skb->len -
skb->data_len) / 2),
((skb->len -
skb->data_len) / 2),
- PCI_DMA_TODEVICE);
+ DMA_TO_DEVICE);
}
} else {
desc[frag].addr_hi = 0;
@@ -3262,17 +3262,17 @@ static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb)
frags[i - 1].size;
/* NOTE: Here, the dma_addr_t returned from
- * pci_map_page() is implicitly cast as a u32.
+ * dma_map_page() is implicitly cast as a u32.
* Although dma_addr_t can be 64-bit, the address
- * returned by pci_map_page() is always 32-bit
+ * returned by dma_map_page() is always 32-bit
* addressable (as defined by the pci/dma subsystem)
*/
desc[frag++].addr_lo =
- pci_map_page(adapter->pdev,
+ dma_map_page(&adapter->pdev->dev,
frags[i - 1].page,
frags[i - 1].page_offset,
frags[i - 1].size,
- PCI_DMA_TODEVICE);
+ DMA_TO_DEVICE);
}
}
@@ -3522,9 +3522,9 @@ static inline void free_send_packet(struct et131x_adapter *adapter,
(adapter->tx_ring.tx_desc_ring +
INDEX10(tcb->index_start));
- pci_unmap_single(adapter->pdev,
+ dma_unmap_single(&adapter->pdev->dev,
desc->addr_lo,
- desc->len_vlan, PCI_DMA_TODEVICE);
+ desc->len_vlan, DMA_TO_DEVICE);
add_10bit(&tcb->index_start, 1);
if (INDEX10(tcb->index_start) >=
@@ -4428,15 +4428,15 @@ static int __devinit et131x_pci_setup(struct pci_dev *pdev,
}
/* Check the DMA addressing support of this device */
- if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
- result = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
+ if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
+ result = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
if (result) {
dev_err(&pdev->dev,
"Unable to obtain 64 bit DMA for consistent allocations\n");
goto err_release_res;
}
- } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
- result = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
+ } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
+ result = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
if (result) {
dev_err(&pdev->dev,
"Unable to obtain 32 bit DMA for consistent allocations\n");
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* staging: et131x: Remove unused defines
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
` (15 preceding siblings ...)
2011-10-19 23:01 ` staging: et131x: Convert rest of pci memory management to dma api Mark Einon
@ 2011-10-19 23:01 ` Mark Einon
16 siblings, 0 replies; 18+ messages in thread
From: Mark Einon @ 2011-10-19 23:01 UTC (permalink / raw)
To: gregkh; +Cc: devel, linux-kernel, Mark Einon
Some defines are no longer referenced in the code, so removed them.
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
drivers/staging/et131x/et131x.c | 11 -----------
1 files changed, 0 insertions(+), 11 deletions(-)
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 1c11dfd..1efa27c 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -145,21 +145,14 @@ MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver "
/* MP_ADAPTER flags */
#define fMP_ADAPTER_RECV_LOOKASIDE 0x00000004
#define fMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
-#define fMP_ADAPTER_SECONDARY 0x00000010
/* MP_SHARED flags */
-#define fMP_ADAPTER_SHUTDOWN 0x00100000
#define fMP_ADAPTER_LOWER_POWER 0x00200000
#define fMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
-#define fMP_ADAPTER_RESET_IN_PROGRESS 0x01000000
-#define fMP_ADAPTER_NO_CABLE 0x02000000
#define fMP_ADAPTER_HARDWARE_ERROR 0x04000000
-#define fMP_ADAPTER_REMOVE_IN_PROGRESS 0x08000000
-#define fMP_ADAPTER_HALT_IN_PROGRESS 0x10000000
#define fMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
-#define fMP_ADAPTER_NOT_READY_MASK 0x3ff00000
/* Some offsets in PCI config space that are actually used. */
#define ET1310_PCI_MAX_PYLD 0x4C
@@ -205,7 +198,6 @@ MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver "
#define NUM_PACKETS_HANDLED 256
-#define ALCATEL_BAD_STATUS 0xe47f0000
#define ALCATEL_MULTICAST_PKT 0x01000000
#define ALCATEL_BROADCAST_PKT 0x02000000
@@ -452,8 +444,6 @@ struct tx_ring {
* Once the desired performance has been achieved, the optimal registry values
* should be re-populated to these #defines:
*/
-#define NUM_TRAFFIC_CLASSES 1
-
#define TX_ERROR_PERIOD 1000
#define LO_MARK_PERCENT_FOR_PSR 15
@@ -4715,7 +4705,6 @@ void et131x_disable_interrupts(struct et131x_adapter *adapter)
writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
}
-
/**
* et131x_isr - The Interrupt Service Routine for the driver.
* @irq: the IRQ on which the interrupt was received.
--
1.7.6.4
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2011-10-19 23:07 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-10-19 23:00 staging: et131x: Move function declarations from et131x.h to et131x.c Mark Einon
2011-10-19 23:00 ` staging: et131x: Move non-register defines " Mark Einon
2011-10-19 23:00 ` staging: et131x: move et1310_address_map.h contents into et131x.h Mark Einon
2011-10-19 23:00 ` staging: et131x: move et1310_phy.h " Mark Einon
2011-10-19 23:00 ` staging: et131x: move et131x_adapter.h contents into et131x.c Mark Einon
2011-10-19 23:00 ` staging: et131x: move et131x_defs.h " Mark Einon
2011-10-19 23:00 ` staging: et131x: move et1310_rx.h " Mark Einon
2011-10-19 23:00 ` staging: et131x: move et1310_tx.h " Mark Einon
2011-10-19 23:00 ` staging: et131x: Update TODO list - remove 'put driver into single file' Mark Einon
2011-10-19 23:01 ` staging: et131x: Moving two extern inline functions to .c file Mark Einon
2011-10-19 23:01 ` staging: et131x: Make rx_ring.fbr{0,1} share a common structure Mark Einon
2011-10-19 23:01 ` staging: et131x: Fix issues when USE_FBR0 is not defined Mark Einon
2011-10-19 23:01 ` staging: et131x: use dma_alloc... instead of pci_alloc Mark Einon
2011-10-19 23:01 ` staging: et131x: Match dma_alloc_ calls with dma_free_ calls Mark Einon
2011-10-19 23:01 ` staging: et131x: Tidy up PCI device table definition Mark Einon
2011-10-19 23:01 ` staging: et131x: on transmit, stop the queue if the next packet will fail Mark Einon
2011-10-19 23:01 ` staging: et131x: Convert rest of pci memory management to dma api Mark Einon
2011-10-19 23:01 ` staging: et131x: Remove unused defines Mark Einon
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