From: Cyril Chemparathy <cyril@ti.com>
To: <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>
Cc: <arnd@arndb.de>, <catalin.marinas@arm.com>,
<grant.likely@secretlab.ca>, <nico@linaro.org>,
<linux@arm.linux.org.uk>, <will.deacon@arm.com>,
Cyril Chemparathy <cyril@ti.com>,
Vitaly Andrianov <vitalya@ti.com>
Subject: [PATCH v3 13/17] ARM: LPAE: factor out T1SZ and TTBR1 computations
Date: Tue, 11 Sep 2012 13:39:11 -0400 [thread overview]
Message-ID: <1347385155-11643-14-git-send-email-cyril@ti.com> (raw)
In-Reply-To: <1347385155-11643-1-git-send-email-cyril@ti.com>
This patch moves the TTBR1 offset calculation and the T1SZ calculation out
of the TTB setup assembly code. This should not affect functionality in
any way, but improves code readability as well as readability of subsequent
patches in this series.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
---
arch/arm/include/asm/pgtable-3level-hwdef.h | 10 ++++++++++
arch/arm/mm/proc-v7-3level.S | 16 ++++------------
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index d795282..b501650 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -74,4 +74,14 @@
#define PHYS_MASK_SHIFT (40)
#define PHYS_MASK ((1ULL << PHYS_MASK_SHIFT) - 1)
+#if defined CONFIG_VMSPLIT_2G
+#define TTBR1_OFFSET (1 << 4) /* skip two L1 entries */
+#elif defined CONFIG_VMSPLIT_3G
+#define TTBR1_OFFSET (4096 * (1 + 3)) /* only L2, skip pgd + 3*pmd */
+#else
+#define TTBR1_OFFSET 0
+#endif
+
+#define TTBR1_SIZE (((PAGE_OFFSET >> 30) - 1) << 16)
+
#endif
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index c4f4251..5d93f00 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -128,18 +128,10 @@ ENDPROC(cpu_v7_set_pte_ext)
* booting secondary CPUs would end up using TTBR1 for the identity
* mapping set up in TTBR0.
*/
- bhi 9001f @ PHYS_OFFSET > PAGE_OFFSET?
- orr \tmp, \tmp, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ
-#if defined CONFIG_VMSPLIT_2G
- /* PAGE_OFFSET == 0x80000000, T1SZ == 1 */
- add \ttbr1, \ttbr1, #1 << 4 @ skip two L1 entries
-#elif defined CONFIG_VMSPLIT_3G
- /* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */
- add \ttbr1, \ttbr1, #4096 * (1 + 3) @ only L2 used, skip pgd+3*pmd
-#endif
- /* CONFIG_VMSPLIT_1G does not need TTBR1 adjustment */
-9001: mcr p15, 0, \tmp, c2, c0, 2 @ TTB control register
- mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1
+ orrls \tmp, \tmp, #TTBR1_SIZE @ TTBCR.T1SZ
+ mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR
+ addls \ttbr1, \ttbr1, #TTBR1_OFFSET
+ mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1
.endm
__CPUINIT
--
1.7.9.5
next prev parent reply other threads:[~2012-09-11 17:43 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-11 17:38 [PATCH v3 00/17] LPAE fixes and extensions for Keystone Cyril Chemparathy
2012-09-11 17:38 ` [PATCH v3 01/17] ARM: add mechanism for late code patching Cyril Chemparathy
2012-09-21 18:09 ` Nicolas Pitre
2012-09-21 22:30 ` Cyril Chemparathy
2012-09-11 17:39 ` [PATCH v3 02/17] ARM: add self test for runtime patch mechanism Cyril Chemparathy
2012-09-21 17:40 ` Nicolas Pitre
2012-09-21 22:25 ` Cyril Chemparathy
2012-09-11 17:39 ` [PATCH v3 03/17] ARM: use late patch framework for phys-virt patching Cyril Chemparathy
2012-09-21 18:15 ` Nicolas Pitre
2012-09-11 17:39 ` [PATCH v3 04/17] ARM: LPAE: use phys_addr_t on virt <--> phys conversion Cyril Chemparathy
2012-09-11 17:39 ` [PATCH v3 05/17] ARM: LPAE: support 64-bit virt_to_phys patching Cyril Chemparathy
2012-09-11 17:39 ` [PATCH v3 06/17] ARM: LPAE: use signed arithmetic for mask definitions Cyril Chemparathy
2012-09-11 17:39 ` [PATCH v3 07/17] ARM: LPAE: use phys_addr_t in alloc_init_pud() Cyril Chemparathy
2012-09-11 17:39 ` [PATCH v3 08/17] ARM: LPAE: use phys_addr_t in free_memmap() Cyril Chemparathy
2012-09-11 17:39 ` [PATCH v3 09/17] ARM: LPAE: use phys_addr_t for initrd location and size Cyril Chemparathy
2012-09-21 18:30 ` Nicolas Pitre
2012-09-11 17:39 ` [PATCH v3 10/17] ARM: LPAE: use phys_addr_t in switch_mm() Cyril Chemparathy
2012-09-21 18:33 ` Nicolas Pitre
2012-09-21 18:41 ` Russell King - ARM Linux
2012-09-21 18:53 ` Nicolas Pitre
2012-09-11 17:39 ` [PATCH v3 11/17] ARM: LPAE: use 64-bit accessors for TTBR registers Cyril Chemparathy
2012-09-11 17:39 ` [PATCH v3 12/17] ARM: LPAE: define ARCH_LOW_ADDRESS_LIMIT for bootmem Cyril Chemparathy
2012-09-11 17:39 ` Cyril Chemparathy [this message]
2012-09-11 17:39 ` [PATCH v3 14/17] ARM: LPAE: accomodate >32-bit addresses for page table base Cyril Chemparathy
2012-09-11 17:39 ` [PATCH v3 15/17] ARM: mm: use physical addresses in highmem sanity checks Cyril Chemparathy
2012-09-11 17:39 ` [PATCH v3 16/17] ARM: mm: cleanup checks for membank overlap with vmalloc area Cyril Chemparathy
2012-09-11 17:39 ` [PATCH v3 17/17] ARM: mm: clean up membank size limit checks Cyril Chemparathy
2012-09-21 18:42 ` Nicolas Pitre
2012-09-21 22:49 ` Cyril Chemparathy
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