From: Andi Kleen <andi@firstfloor.org>
To: linux-kernel@vger.kernel.org
Cc: acme@redhat.com, peterz@infradead.org, jolsa@redhat.com,
eranian@google.com, mingo@kernel.org, namhyung@kernel.org,
Andi Kleen <ak@linux.intel.com>,
avi@redhat.com, gleb@redhat.com
Subject: [PATCH 05/32] perf, kvm: Support the intx/intx_cp modifiers in KVM arch perfmon emulation v3
Date: Tue, 30 Oct 2012 17:33:56 -0700 [thread overview]
Message-ID: <1351643663-23828-6-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1351643663-23828-1-git-send-email-andi@firstfloor.org>
From: Andi Kleen <ak@linux.intel.com>
This is not arch perfmon, but older CPUs will just ignore it. This makes
it possible to do at least some TSX measurements from a KVM guest
Cc: avi@redhat.com
Cc: gleb@redhat.com
v2: Various fixes to address review feedback
v3: Ignore the bits when no CPUID. No #GP. Force raw events with TSX bits.
Cc: gleb@redhat.com
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/include/asm/kvm_host.h | 1 +
arch/x86/kvm/pmu.c | 34 ++++++++++++++++++++++++++--------
2 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index b2e11f4..6783289 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -318,6 +318,7 @@ struct kvm_pmu {
u64 global_ovf_ctrl;
u64 counter_bitmask[2];
u64 global_ctrl_mask;
+ u64 cpuid_word9;
u8 version;
struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];
struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED];
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
index cfc258a..8bc954a 100644
--- a/arch/x86/kvm/pmu.c
+++ b/arch/x86/kvm/pmu.c
@@ -160,7 +160,7 @@ static void stop_counter(struct kvm_pmc *pmc)
static void reprogram_counter(struct kvm_pmc *pmc, u32 type,
unsigned config, bool exclude_user, bool exclude_kernel,
- bool intr)
+ bool intr, bool intx, bool intx_cp)
{
struct perf_event *event;
struct perf_event_attr attr = {
@@ -173,6 +173,11 @@ static void reprogram_counter(struct kvm_pmc *pmc, u32 type,
.exclude_kernel = exclude_kernel,
.config = config,
};
+ /* Will be ignored on CPUs that don't support this. */
+ if (intx)
+ attr.config |= HSW_INTX;
+ if (intx_cp)
+ attr.config |= HSW_INTX_CHECKPOINTED;
attr.sample_period = (-pmc->counter) & pmc_bitmask(pmc);
@@ -206,7 +211,8 @@ static unsigned find_arch_event(struct kvm_pmu *pmu, u8 event_select,
return arch_events[i].event_type;
}
-static void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
+static void reprogram_gp_counter(struct kvm_pmu *pmu, struct kvm_pmc *pmc,
+ u64 eventsel)
{
unsigned config, type = PERF_TYPE_RAW;
u8 event_select, unit_mask;
@@ -224,9 +230,16 @@ static void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
event_select = eventsel & ARCH_PERFMON_EVENTSEL_EVENT;
unit_mask = (eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
+ if (!(boot_cpu_has(X86_FEATURE_HLE) ||
+ boot_cpu_has(X86_FEATURE_RTM)) ||
+ !(pmu->cpuid_word9 & (X86_FEATURE_HLE|X86_FEATURE_RTM)))
+ eventsel &= ~(HSW_INTX|HSW_INTX_CHECKPOINTED);
+
if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE |
ARCH_PERFMON_EVENTSEL_INV |
- ARCH_PERFMON_EVENTSEL_CMASK))) {
+ ARCH_PERFMON_EVENTSEL_CMASK |
+ HSW_INTX |
+ HSW_INTX_CHECKPOINTED))) {
config = find_arch_event(&pmc->vcpu->arch.pmu, event_select,
unit_mask);
if (config != PERF_COUNT_HW_MAX)
@@ -239,7 +252,9 @@ static void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
reprogram_counter(pmc, type, config,
!(eventsel & ARCH_PERFMON_EVENTSEL_USR),
!(eventsel & ARCH_PERFMON_EVENTSEL_OS),
- eventsel & ARCH_PERFMON_EVENTSEL_INT);
+ eventsel & ARCH_PERFMON_EVENTSEL_INT,
+ (eventsel & HSW_INTX),
+ (eventsel & HSW_INTX_CHECKPOINTED));
}
static void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 en_pmi, int idx)
@@ -256,7 +271,7 @@ static void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 en_pmi, int idx)
arch_events[fixed_pmc_events[idx]].event_type,
!(en & 0x2), /* exclude user */
!(en & 0x1), /* exclude kernel */
- pmi);
+ pmi, false, false);
}
static inline u8 fixed_en_pmi(u64 ctrl, int idx)
@@ -289,7 +304,7 @@ static void reprogram_idx(struct kvm_pmu *pmu, int idx)
return;
if (pmc_is_gp(pmc))
- reprogram_gp_counter(pmc, pmc->eventsel);
+ reprogram_gp_counter(pmu, pmc, pmc->eventsel);
else {
int fidx = idx - INTEL_PMC_IDX_FIXED;
reprogram_fixed_counter(pmc,
@@ -400,8 +415,8 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
} else if ((pmc = get_gp_pmc(pmu, index, MSR_P6_EVNTSEL0))) {
if (data == pmc->eventsel)
return 0;
- if (!(data & 0xffffffff00200000ull)) {
- reprogram_gp_counter(pmc, data);
+ if (!(data & 0xfffffffc00200000ull)) {
+ reprogram_gp_counter(pmu, pmc, data);
return 0;
}
}
@@ -470,6 +485,9 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu)
pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) |
(((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
pmu->global_ctrl_mask = ~pmu->global_ctrl;
+
+ entry = kvm_find_cpuid_entry(vcpu, 7, 0);
+ pmu->cpuid_word9 = entry ? entry->ebx : 0;
}
void kvm_pmu_init(struct kvm_vcpu *vcpu)
--
1.7.7.6
next prev parent reply other threads:[~2012-10-31 0:44 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-31 0:33 perf PMU support for Haswell v5 Andi Kleen
2012-10-31 0:33 ` [PATCH 01/32] perf, x86: Add PEBSv2 record support Andi Kleen
2012-10-31 0:33 ` [PATCH 02/32] perf, x86: Basic Haswell PMU support v2 Andi Kleen
2012-10-31 0:33 ` [PATCH 03/32] perf, x86: Basic Haswell PEBS support v3 Andi Kleen
2012-10-31 0:33 ` [PATCH 04/32] perf, x86: Support the TSX intx/intx_cp qualifiers v2 Andi Kleen
2012-10-31 0:33 ` Andi Kleen [this message]
2012-10-31 10:27 ` [PATCH 05/32] perf, kvm: Support the intx/intx_cp modifiers in KVM arch perfmon emulation v3 Gleb Natapov
2012-10-31 10:32 ` Andi Kleen
2012-10-31 10:38 ` Gleb Natapov
2012-10-31 16:43 ` Andi Kleen
2012-11-01 16:50 ` Andi Kleen
2012-10-31 0:33 ` [PATCH 06/32] perf, x86: Support PERF_SAMPLE_ADDR on Haswell Andi Kleen
2012-10-31 0:33 ` [PATCH 07/32] perf, x86: Support Haswell v4 LBR format Andi Kleen
2012-10-31 0:33 ` [PATCH 08/32] perf, x86: Disable LBR recording for unknown LBR_FMT Andi Kleen
2012-10-31 0:34 ` [PATCH 09/32] perf, x86: Support LBR filtering by INTX/NOTX/ABORT v2 Andi Kleen
2012-10-31 0:34 ` [PATCH 10/32] perf, tools: Add abort_tx,no_tx,in_tx branch filter options to perf record -j v3 Andi Kleen
2012-10-31 0:34 ` [PATCH 11/32] perf, tools: Support sorting by intx, abort branch flags Andi Kleen
2012-10-31 0:34 ` [PATCH 12/32] perf, x86: Support full width counting Andi Kleen
2012-10-31 0:34 ` [PATCH 13/32] perf, x86: Avoid checkpointed counters causing excessive TSX aborts v3 Andi Kleen
2012-10-31 0:34 ` [PATCH 14/32] perf, core: Add a concept of a weightened sample Andi Kleen
2012-10-31 0:34 ` [PATCH 15/32] perf, x86: Support weight samples for PEBS Andi Kleen
2012-10-31 0:34 ` [PATCH 16/32] perf, tools: Add support for weight v3 Andi Kleen
2012-10-31 0:34 ` [PATCH 17/32] perf, tools: Handle XBEGIN like a jump Andi Kleen
2012-11-14 6:35 ` [tip:perf/core] perf annotate: " tip-bot for Andi Kleen
2012-10-31 0:34 ` [PATCH 18/32] perf, x86: Support for printing PMU state on spurious PMIs v3 Andi Kleen
2012-10-31 0:34 ` [PATCH 19/32] perf, core: Add generic transaction flags v2 Andi Kleen
2012-10-31 0:34 ` [PATCH 20/32] perf, x86: Add Haswell specific transaction flag reporting Andi Kleen
2012-10-31 0:34 ` [PATCH 21/32] perf, tools: Add support for record transaction flags v2 Andi Kleen
2012-10-31 0:34 ` [PATCH 22/32] perf, tools: Point --sort documentation to --help Andi Kleen
2012-10-31 0:34 ` [PATCH 23/32] perf, tools: Add browser support for transaction flags v2 Andi Kleen
2012-10-31 9:02 ` [PATCH] perf, tools: Fix WERROR=1 build with transction flags and fix browser Andi Kleen
2012-10-31 0:34 ` [PATCH 24/32] perf, tools: Add arbitary aliases and support names with - Andi Kleen
2012-10-31 0:34 ` [PATCH 25/32] tools, perf: Add a precise event qualifier Andi Kleen
2012-10-31 0:34 ` [PATCH 26/32] perf, x86: improve sysfs event mapping with event string Andi Kleen
2012-10-31 0:34 ` [PATCH 27/32] perf, x86: Support CPU specific sysfs events Andi Kleen
2012-11-07 14:41 ` Stephane Eranian
2012-10-31 0:34 ` [PATCH 28/32] perf, x86: Add Haswell TSX event aliases v2 Andi Kleen
2012-10-31 0:34 ` [PATCH 29/32] perf, tools: Add perf stat --transaction v2 Andi Kleen
2012-10-31 0:34 ` [PATCH 30/32] perf, x86: Add a Haswell precise instructions event v2 Andi Kleen
2012-10-31 0:34 ` [PATCH 31/32] perf, tools: Default to cpu// for events v3 Andi Kleen
2012-10-31 0:34 ` [PATCH 32/32] perf, tools: List kernel supplied event aliases in perf list v2 Andi Kleen
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