From: bdegraaf@codeaurora.org
To: Laura Abbott <labbott@redhat.com>
Cc: catalin.marinas@arm.com, will.deacon@arm.com,
james.morse@arm.com, mark.rutland@arm.com,
andre.przywara@arm.com, jungseoklee85@gmail.com,
apinski@cavium.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, timur@codeaurora.org,
cov@codeaurora.org
Subject: Re: [RFC] arm64: Ensure proper addressing for ldnp/stnp
Date: Mon, 19 Sep 2016 14:41:10 -0400 [thread overview]
Message-ID: <13521f9f5ebe1cd0a85bf31b5ad5cba0@codeaurora.org> (raw)
In-Reply-To: <50fcc549-d785-6332-83bd-292a4f44e8d4@redhat.com>
On 2016-09-19 14:28, Laura Abbott wrote:
> On 09/19/2016 10:36 AM, Brent DeGraaf wrote:
>> According to section 6.3.8 of the ARM Programmer's Guide, non-temporal
>> loads and stores do not verify that address dependency is met between
>> a
>> load of an address to a register and a subsequent non-temporal load or
>> store using that address on the executing PE. Therefore, context
>> switch
>> code and subroutine calls that use non-temporally accessed addresses
>> as
>> parameters that might depend on a load of an address into an argument
>> register must ensure that ordering requirements are met by introducing
>> a barrier prior to the successive non-temporal access. Add
>> appropriate
>> barriers whereever this specific situation comes into play.
>>
>
> Was this found by code inspection or is there a (public) exciting test
> case to observe this behavior?
>
> Thanks,
> Laura
>
Code inspection only.
Brent
prev parent reply other threads:[~2016-09-19 18:41 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-19 17:36 Brent DeGraaf
2016-09-19 18:01 ` Robin Murphy
2016-09-19 18:25 ` bdegraaf
2016-09-20 11:00 ` Robin Murphy
2016-09-20 13:02 ` bdegraaf
2016-09-19 18:28 ` Laura Abbott
2016-09-19 18:41 ` bdegraaf [this message]
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