From: Andi Kleen <andi@firstfloor.org>
To: mingo@kernel.org
Cc: linux-kernel@vger.kernel.org, a.p.zijlstra@chello.nl,
akpm@linux-foundation.org, acme@redhat.com, eranian@google.com,
jolsa@redhat.com, namhyung@kernel.org,
Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 09/12] perf, x86: Disable LBR recording for unknown LBR_FMT
Date: Fri, 25 Jan 2013 14:00:42 -0800 [thread overview]
Message-ID: <1359151245-13179-10-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1359151245-13179-1-git-send-email-andi@firstfloor.org>
From: Andi Kleen <ak@linux.intel.com>
When the LBR format is unknown disable LBR recording. This prevents
crashes when the LBR address is misdecoded and mis-sign extended.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/perf_event_intel_lbr.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 2af6695b..ad5af13 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -13,6 +13,7 @@ enum {
LBR_FORMAT_EIP = 0x02,
LBR_FORMAT_EIP_FLAGS = 0x03,
LBR_FORMAT_EIP_FLAGS2 = 0x04,
+ LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_EIP_FLAGS2,
};
/*
@@ -392,7 +393,7 @@ int intel_pmu_setup_lbr_filter(struct perf_event *event)
/*
* no LBR on this PMU
*/
- if (!x86_pmu.lbr_nr)
+ if (!x86_pmu.lbr_nr || x86_pmu.intel_cap.lbr_format > LBR_FORMAT_MAX_KNOWN)
return -EOPNOTSUPP;
/*
--
1.7.7.6
next prev parent reply other threads:[~2013-01-25 22:02 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-25 22:00 Basic perf PMU support for Haswell v1 Andi Kleen
2013-01-25 22:00 ` [PATCH 01/12] perf, x86: Add PEBSv2 record support Andi Kleen
2013-01-28 13:15 ` Stephane Eranian
2013-01-28 16:10 ` Andi Kleen
2013-01-31 17:15 ` Stephane Eranian
2013-01-25 22:00 ` [PATCH 02/12] perf, x86: Basic Haswell PMU support v2 Andi Kleen
2013-01-28 15:34 ` Stephane Eranian
2013-01-28 16:16 ` Andi Kleen
2013-01-25 22:00 ` [PATCH 03/12] perf, x86: Basic Haswell PEBS support v3 Andi Kleen
2013-01-28 15:56 ` Stephane Eranian
2013-01-25 22:00 ` [PATCH 04/12] perf, x86: Support the TSX intx/intx_cp qualifiers v2 Andi Kleen
2013-01-26 11:54 ` Ingo Molnar
2013-01-26 21:00 ` Andi Kleen
2013-01-27 13:14 ` Ingo Molnar
[not found] ` <20130128050234.GQ30577@one.firstfloor.org>
2013-01-28 10:47 ` Ingo Molnar
2013-01-28 16:52 ` Stephane Eranian
2013-01-28 17:37 ` Andi Kleen
2013-01-25 22:00 ` [PATCH 05/12] perf, x86: Support Haswell v4 LBR format Andi Kleen
2013-01-28 21:47 ` Stephane Eranian
2013-01-28 22:08 ` Andi Kleen
2013-01-28 22:20 ` Stephane Eranian
2013-01-25 22:00 ` [PATCH 06/12] perf, x86: Support full width counting Andi Kleen
2013-01-25 22:00 ` [PATCH 07/12] perf, x86: Avoid checkpointed counters causing excessive TSX aborts v3 Andi Kleen
2013-01-28 22:32 ` Stephane Eranian
2013-01-28 23:16 ` Andi Kleen
2013-01-29 0:30 ` Stephane Eranian
2013-01-29 1:00 ` Andi Kleen
2013-01-30 8:51 ` Stephane Eranian
2013-01-30 20:58 ` Andi Kleen
2013-01-25 22:00 ` [PATCH 08/12] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset Andi Kleen
2013-01-25 22:00 ` Andi Kleen [this message]
2013-01-25 22:00 ` [PATCH 10/12] perf, x86: Support LBR filtering by INTX/NOTX/ABORT v2 Andi Kleen
2013-01-25 22:00 ` [PATCH 11/12] perf, tools: Support sorting by intx, abort branch flags v2 Andi Kleen
2013-01-25 22:00 ` [PATCH 12/12] perf, tools: Add abort_tx,no_tx,in_tx branch filter options to perf record -j v3 Andi Kleen
2013-01-31 17:19 ` Basic perf PMU support for Haswell v1 Stephane Eranian
2013-01-31 17:47 ` Andi Kleen
2013-01-31 22:51 Basic perf PMU support for Haswell v2 Andi Kleen
2013-01-31 22:51 ` [PATCH 09/12] perf, x86: Disable LBR recording for unknown LBR_FMT Andi Kleen
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