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From: Gregory CLEMENT <gregory.clement@free-electrons.com>
To: Daniel Lezcano <daniel.lezcano@linaro.org>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	linux-pm@vger.kernel.org, Jason Cooper <jason@lakedaemon.net>,
	Andrew Lunn <andrew@lunn.ch>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
	Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
	linux-arm-kernel@lists.infradead.org,
	Lior Amsalem <alior@marvell.com>,
	Tawfik Bayouk <tawfik@marvell.com>,
	Nadav Haklai <nadavh@marvell.com>,
	linux-kernel@vger.kernel.org
Subject: [PATCH v6 06/11] ARM: mvebu: Low level function to disable HW coherency support
Date: Fri, 28 Mar 2014 12:13:26 +0100	[thread overview]
Message-ID: <1396005211-15573-7-git-send-email-gregory.clement@free-electrons.com> (raw)
In-Reply-To: <1396005211-15573-1-git-send-email-gregory.clement@free-electrons.com>

When going to deep idle we need to disable the SoC snooping (aka
hardware coherency support). Playing with the coherency fabric
requires to use assembly code to be sure that the compiler doesn't
reorder the instructions nor do wrong optimization.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm/mach-mvebu/coherency_ll.S | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index f2e2e8677c4b..6828f9f157b0 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -102,6 +102,26 @@ ENTRY(ll_enable_coherency)
 	mov	pc, lr
 ENDPROC(ll_enable_coherency)
 
+ENTRY(ll_disable_coherency)
+	/*
+	 * r0 being untouched in ll_get_coherency_base and
+	 * ll_get_cpuid, we can use it to save lr modifing it with the
+	 * following bl
+	 */
+	mov r0, lr
+	bl	ll_get_coherency_base
+	bl	ll_get_cpuid
+	mov lr, r0
+	add	r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
+1:
+	ldrex	r2, [r0]
+	bic	r2, r2, r3
+	strex	r1, r2, [r0]
+	cmp	r1, #0
+	bne	1b
+	dsb
+	mov	pc, lr
+ENDPROC(ll_disable_coherency)
 
 	.align 2
 3:
-- 
1.8.1.2


  parent reply	other threads:[~2014-03-28 11:14 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-03-28 11:13 [PATCH v6 00/11] CPU idle for Armada XP Gregory CLEMENT
2014-03-28 11:13 ` [PATCH v6 01/11] ARM: PJ4B: Add cpu_suspend/cpu_resume hooks for PJ4B Gregory CLEMENT
2014-03-28 11:13 ` [PATCH v6 02/11] ARM: mvebu: remove the address parameter for ll_set_cpu_coherent Gregory CLEMENT
2014-03-28 11:13 ` [PATCH v6 03/11] ARM: mvebu: ll_set_cpu_coherent always uses the current CPU Gregory CLEMENT
2014-03-28 11:13 ` [PATCH v6 04/11] ARM: mvebu: Remove the unused argument of set_cpu_coherent() Gregory CLEMENT
2014-03-28 11:13 ` [PATCH v6 05/11] ARM: mvebu: Split low level functions to manipulate HW coherency Gregory CLEMENT
2014-03-28 11:13 ` Gregory CLEMENT [this message]
2014-03-28 11:13 ` [PATCH v6 07/11] ARM: mvebu: Allow to power down L2 cache controller in idle mode Gregory CLEMENT
2014-03-28 11:13 ` [PATCH v6 08/11] ARM: mvebu: Add the PMSU related part of the cpu idle functions Gregory CLEMENT
2014-03-28 11:13 ` [PATCH v6 09/11] ARM: mvebu: Register notifier callback for the cpuidle transition Gregory CLEMENT
2014-04-03  8:18   ` Daniel Lezcano
2014-03-28 11:13 ` [PATCH v6 10/11] cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC Gregory CLEMENT
2014-04-03  8:16   ` Daniel Lezcano
2014-04-04  8:20     ` Gregory CLEMENT
2014-03-28 11:13 ` [PATCH v6 11/11] ARM: mvebu: register the cpuidle driver for the Armada XP SoCs Gregory CLEMENT

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