Re: [PATCH v2 1/2] x86/cpu: Disable CR pinning during CPU bringup

[Sohil Mehta <sohil.mehta@intel.com>]

On 3/12/2026 7:08 AM, Nikunj A. Dadhania wrote:

>   1) Universally set X86_CR4_FSGSBASE in cr4_init() and call cr4_init()
>      from trap_init() on the boot CPU


cr4_init() seems like the wrong place to do this. I don't think this a
primarily a CR4 issue. Deferring CR4 pinning maybe have uncovered the
FSGSBASE issue.

But, essentially the difference lies in when we enable exception
handling related features on the BSP vs APs. It involves setting a few
other things than CR4 programming.

See:

/*
 * Setup everything needed to handle exceptions from the IDT, including
the IST
 * exceptions which use paranoid_entry().
 */
void cpu_init_exception_handling(bool boot_cpu)

IIUC, anything that is needed to handle exceptions should be initialized
here. As FSGSBASE is used in the paranoid_entry() code, should its
enabling be moved to cpu_init_exception_handling()?

Note, we already have other things there for #VC handling:

	/* GHCB needs to be setup to handle #VC. */
	setup_ghcb();

>   2) Disable CR pinning during secondary CPU bringup
>   3) Add #VC handler for FRED and use boot_ghcb during early boot
>